Changeset 17178 in vbox for trunk

Timestamp:

Feb 26, 2009 5:23:42 PM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

43457

Message:

VBOX_WITH_PGMPOOL_PAGING_ONLY: Properly flush the TLB for PAE PDPT entries.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• PGMAll.cpp (modified) (4 diffs)
• PGMAllPool.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -876 +876 @@
     int            rc;
 
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-    /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
-    PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
-# endif
-
     /* Allocate page directory if not present. */
     if (    !pPdpe->n.u1Present
@@ -889 +884 @@
         RTGCPTR64   GCPdPt;
         PGMPOOLKIND enmKind;
+
+# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+        /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
+        PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
+# endif
 
         if (fNestedPaging || !fPaging)
@@ -925 +925 @@
         }
         AssertRCReturn(rc, rc);
+
+        /* The PD was cached or created; hook it up now. */
+        pPdpe->u |= pShwPage->Core.Key
+                 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
+
+# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+        /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
+         * non-present PDPT will continue to cause page faults.
+         */
+        ASMReloadCR3();
+        PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
+# endif
     }
     else
@@ -930 +942 @@
         pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
         AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
-    }
-    /* The PD was cached or created; hook it up now. */
-    pPdpe->u |= pShwPage->Core.Key
-             | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
-
-# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
-    PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
-# endif
+
+        Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key));
+    }
     *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
     return VINF_SUCCESS;

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -3203 +3203 @@
         case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
         case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
+#if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+            /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
+             * non-present PDPT will continue to cause page faults.
+             */
+            ASMReloadCR3();
+#endif
+            /* no break */
         case PGMPOOLKIND_PAE_PD_PHYS:
         case PGMPOOLKIND_PAE_PDPT_PHYS:
@@ -3210 +3217 @@
         case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
         case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
-# if !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
+#if !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
         case PGMPOOLKIND_ROOT_PAE_PD:
 #endif