VirtualBox

Changeset 17586 in vbox for trunk/src/VBox/VMM/PGMInternal.h


Ignore:
Timestamp:
Mar 9, 2009 3:28:25 PM (16 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
44039
Message:

Removed all dead non-VBOX_WITH_PGMPOOL_PAGING_ONLY code.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/PGMInternal.h

    r17513 r17586  
    5353 * @{
    5454 */
    55 
    56 /*
    57  * Enable to use the PGM pool for all levels in the paging chain in all paging modes.
    58  */
    59 #define VBOX_WITH_PGMPOOL_PAGING_ONLY
    6055
    6156/**
    … …  
    14601455/** The first normal index. */
    14611456#define PGMPOOL_IDX_FIRST_SPECIAL       1
    1462 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14631457/** Page directory (32-bit root). */
    14641458#define PGMPOOL_IDX_PD                  1
    … …  
    14711465/** The first normal index. */
    14721466#define PGMPOOL_IDX_FIRST               5
    1473 #else
    1474 /** Page directory (32-bit root). */
    1475 #define PGMPOOL_IDX_PD                  1
    1476 /** The extended PAE page directory (2048 entries, works as root currently). */
    1477 #define PGMPOOL_IDX_PAE_PD              2
    1478 /** PAE Page Directory Table 0. */
    1479 #define PGMPOOL_IDX_PAE_PD_0            3
    1480 /** PAE Page Directory Table 1. */
    1481 #define PGMPOOL_IDX_PAE_PD_1            4
    1482 /** PAE Page Directory Table 2. */
    1483 #define PGMPOOL_IDX_PAE_PD_2            5
    1484 /** PAE Page Directory Table 3. */
    1485 #define PGMPOOL_IDX_PAE_PD_3            6
    1486 /** Page Directory Pointer Table (PAE root, not currently used). */
    1487 #define PGMPOOL_IDX_PDPT                7
    1488 /** AMD64 CR3 level index.*/
    1489 #define PGMPOOL_IDX_AMD64_CR3           8
    1490 /** Nested paging root.*/
    1491 #define PGMPOOL_IDX_NESTED_ROOT         9
    1492 /** The first normal index. */
    1493 #define PGMPOOL_IDX_FIRST               10
    1494 #endif
    14951467/** The last valid index. (inclusive, 14 bits) */
    14961468#define PGMPOOL_IDX_LAST                0x3fff
    … …  
    16061578    PGMPOOLKIND_EPT_PT_FOR_PHYS,
    16071579
    1608 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    1609     /** Shw: Root 32-bit page directory. */
    1610     PGMPOOLKIND_ROOT_32BIT_PD,
    1611     /** Shw: Root PAE page directory */
    1612     PGMPOOLKIND_ROOT_PAE_PD,
    1613     /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
    1614     PGMPOOLKIND_ROOT_PDPT,
    1615 #endif
    16161580    /** Shw: Root Nested paging table. */
    16171581    PGMPOOLKIND_ROOT_NESTED,
    … …  
    16861650     * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
    16871651    bool volatile       fReusedFlushPending;
    1688 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    16891652    /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
    16901653    bool                fLocked;
    1691 #else
    1692     /** Used to indicate that the guest is mapping the page is also used as a CR3.
    1693      * In these cases the access handler acts differently and will check
    1694      * for mapping conflicts like the normal CR3 handler.
    1695      * @todo When we change the CR3 shadowing to use pool pages, this flag can be
    1696      *       replaced by a list of pages which share access handler.
    1697      */
    1698     bool                fCR3Mix;
    1699 #endif
    17001654} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
    17011655
    … …  
    21622116    DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    21632117    DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2164 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2165     DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2166     DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
    2167 #endif
    2168 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2169     R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
    2170     R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
    2171     R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
    2172     R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
    2173 #endif
    21742118    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    21752119    DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    21762120    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2177 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2178     DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2179     DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
    2180 #endif
    2181 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2182     RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
    2183     RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
    2184 #endif
    21852121    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    21862122    DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    21872123    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2188 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2189     DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2190     DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
    2191 #endif
    2192 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2193     R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
    2194     R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
    2195 #endif
    21962124    /** @} */
    21972125
    … …  
    22932221    uint32_t                        u32Alignment;
    22942222#endif
    2295 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2296     /** The physical address of the currently monitored guest CR3 page.
    2297      * When this value is NIL_RTGCPHYS no page is being monitored. */
    2298     RTGCPHYS                        GCPhysGstCR3Monitored;
    2299 #endif
    23002223    /** @name 32-bit Guest Paging.
    23012224     * @{ */
    … …  
    23502273    /** @} */
    23512274
    2352 # ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2353     /** @name Shadow paging
    2354      * @{ */
    2355     /** The root page table - R3 Ptr. */
    2356     R3PTRTYPE(void *)               pShwRootR3;
    2357 #  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    2358     /** The root page table - R0 Ptr. */
    2359     R0PTRTYPE(void *)               pShwRootR0;
    2360 #  endif
    2361     /** The root page table - RC Ptr. */
    2362     RCPTRTYPE(void *)               pShwRootRC;
    2363 #  if HC_ARCH_BITS == 64
    2364     uint32_t                        u32Padding1; /**< alignment padding. */
    2365 #  endif
    2366     /** The Physical Address (HC) of the current active shadow CR3. */
    2367     RTHCPHYS                        HCPhysShwCR3;
    2368 # endif
    23692275    /** Pointer to the page of the current active CR3 - R3 Ptr. */
    23702276    R3PTRTYPE(PPGMPOOLPAGE)         pShwPageCR3R3;
    … …  
    23812287# endif
    23822288    /** @} */
    2383 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2384     /** @name 32-bit Shadow Paging
    2385      * @{ */
    2386     /** The 32-Bit PD - R3 Ptr. */
    2387     R3PTRTYPE(PX86PD)               pShw32BitPdR3;
    2388     /** The 32-Bit PD - R0 Ptr. */
    2389     R0PTRTYPE(PX86PD)               pShw32BitPdR0;
    2390     /** The 32-Bit PD - RC Ptr. */
    2391     RCPTRTYPE(PX86PD)               pShw32BitPdRC;
    2392 # if HC_ARCH_BITS == 64
    2393     uint32_t                        u32Padding10; /**< alignment padding. */
    2394 # endif
    2395     /** The Physical Address (HC) of the 32-Bit PD. */
    2396     RTHCPHYS                        HCPhysShw32BitPD;
    2397     /** @} */
    2398 
    2399     /** @name PAE Shadow Paging
    2400      * @{ */
    2401     /** The four PDs for the low 4GB - R3 Ptr.
    2402      * Even though these are 4 pointers, what they point at is a single table.
    2403      * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
    2404     R3PTRTYPE(PX86PDPAE)            apShwPaePDsR3[4];
    2405 # ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    2406     /** The four PDs for the low 4GB - R0 Ptr.
    2407      * Same kind of mapping as apHCPaePDs. */
    2408     R0PTRTYPE(PX86PDPAE)            apShwPaePDsR0[4];
    2409 # endif
    2410     /** The four PDs for the low 4GB - RC Ptr.
    2411      * Same kind of mapping as apHCPaePDs. */
    2412     RCPTRTYPE(PX86PDPAE)            apShwPaePDsRC[4];
    2413     /** The Physical Address (HC) of the four PDs for the low 4GB.
    2414      * These are *NOT* 4 contiguous pages. */
    2415     RTHCPHYS                        aHCPhysPaePDs[4];
    2416     /** The Physical Address (HC) of the PAE PDPT. */
    2417     RTHCPHYS                        HCPhysShwPaePdpt;
    2418     /** The PAE PDPT - R3 Ptr. */
    2419     R3PTRTYPE(PX86PDPT)             pShwPaePdptR3;
    2420     /** The PAE PDPT - R0 Ptr. */
    2421     R0PTRTYPE(PX86PDPT)             pShwPaePdptR0;
    2422     /** The PAE PDPT - RC Ptr. */
    2423     RCPTRTYPE(PX86PDPT)             pShwPaePdptRC;
    2424     /** @} */
    2425 # if HC_ARCH_BITS == 64
    2426     RTRCPTR                         alignment5; /**< structure size alignment. */
    2427 # endif
    2428     /** @name Nested Shadow Paging
    2429      * @{ */
    2430     /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
    2431     RTR3PTR                         pShwNestedRootR3;
    2432 # ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    2433     /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
    2434     RTR0PTR                         pShwNestedRootR0;
    2435 # endif
    2436     /** The Physical Address (HC) of the nested paging root. */
    2437     RTHCPHYS                        HCPhysShwNestedRoot;
    2438     /** @}  */
    2439 #endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
    24402289
    24412290    /** @name Function pointers for Shadow paging.
    … …  
    24632312    DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    24642313    DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2465 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2466     DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2467     DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
    2468 #endif
    2469 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2470     R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
    2471     R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
    2472     R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
    2473     R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
    2474 #endif
    24752314    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    24762315    DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    24772316    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2478 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2479     DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2480     DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
    2481 #endif
    2482 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2483     RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
    2484     RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
    2485 #endif
    24862317#if HC_ARCH_BITS == 64
    24872318    RTRCPTR                         alignment3; /**< structure size alignment. */
    … …  
    24912322    DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    24922323    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
    2493 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2494     DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    2495     DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
    2496 #endif
    2497 #ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    2498     R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
    2499     R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
    2500 #endif
    25012324    /** @} */
    25022325
    … …  
    30722895int             pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
    30732896#endif
    3074 #if !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && (defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0))
    3075 void           *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
    3076 #endif
    30772897int             pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
    30782898PPGMPOOLPAGE    pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
    … …  
    31012921#endif
    31022922
    3103 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    31042923void            pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE);
    31052924void            pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
    31062925int             pgmShwSyncPaePDPtr(PVM pVM, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
    3107 #endif
    31082926int             pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
    31092927int             pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
    … …  
    35323350        return pv;
    35333351    }
    3534 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    35353352    AssertFatalMsgFailed(("pgmPoolMapPageInlined invalid page index %x\n", pPage->idx));
    3536 #else
    3537     return pgmPoolMapPageFallback(pPGM, pPage);
    3538 #endif
    35393353}
    35403354
    … …  
    42124026DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
    42134027{
    4214 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    42154028    return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
    4216 #else
    4217 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4218     PX86PD          pShwPd;
    4219     Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
    4220     int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
    4221     AssertRCReturn(rc, NULL);
    4222     return pShwPd;
    4223 # else
    4224     return pPGM->CTX_SUFF(pShw32BitPd);
    4225 # endif
    4226 #endif
    42274029}
    42284030
    … …  
    42754077DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
    42764078{
    4277 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    42784079    return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
    4279 #else
    4280 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4281     PX86PDPT pShwPdpt;
    4282     Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
    4283     int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
    4284     AssertRCReturn(rc, 0);
    4285     return pShwPdpt;
    4286 # else
    4287     return pPGM->CTX_SUFF(pShwPaePdpt);
    4288 # endif
    4289 #endif
    42904080}
    42914081
    … …  
    43004090DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
    43014091{
    4302 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    43034092    const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
    43044093    PX86PDPT        pPdpt = pgmShwGetPaePDPTPtr(pPGM);
    … …  
    43124101
    43134102    return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
    4314 #else
    4315     const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
    4316 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4317     PX86PDPAE       pPD;
    4318     int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
    4319     AssertRCReturn(rc, 0);
    4320     return pPD;
    4321 # else
    4322     PX86PDPAE       pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
    4323     Assert(pPD);
    4324     return pPD;
    4325 # endif
    4326 #endif
    43274103}
    43284104
    … …  
    43374113DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, PX86PDPT pPdpt, RTGCPTR GCPtr)
    43384114{
    4339 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    43404115    const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
    43414116
    … …  
    43484123
    43494124    return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
    4350 #else
    4351     AssertFailed();
    4352     return NULL;
    4353 #endif
    43544125}
    43554126
    … …  
    44024173DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
    44034174{
    4404 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    44054175    return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
    4406 #else
    4407 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4408     PX86PML4 pShwPml4;
    4409     Assert(pPGM->HCPhysShwCR3 != 0 && pPGM->HCPhysShwCR3 != NIL_RTHCPHYS);
    4410     int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwCR3, &pShwPml4);
    4411     AssertRCReturn(rc, 0);
    4412     return pShwPml4;
    4413 # else
    4414     Assert(pPGM->CTX_SUFF(pShwRoot));
    4415     return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
    4416 # endif
    4417 #endif
    44184176}
    44194177
    … …  
    47354493#endif /* PGMPOOL_WITH_CACHE */
    47364494
    4737 #ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    4738 
    47394495/**
    47404496 * Locks a page to prevent flushing (important for cr3 root pages or shadow pae pd pages).
    … …  
    47814537}
    47824538
    4783 #endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
    4784 
    47854539/**
    47864540 * Tells if mappings are to be put into the shadow page table or not
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette