VirtualBox

Changeset 19812 in vbox


Ignore:
Timestamp:
May 19, 2009 11:54:55 AM (16 years ago)
Author:
vboxsync
Message:

Implemented HWACCMFlushAllTLBs

Location:
trunk
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/hwaccm.h

    r19808 r19812  
    8181#ifndef IN_RC
    8282VMMDECL(int)     HWACCMFlushTLB(PVMCPU pVCpu);
     83VMMDECL(int)     HWACCMFlushAllTLBs(PVM pVM);
    8384VMMDECL(int)     HWACCMInvalidatePhysPage(PVMCPU pVCpu, RTGCPHYS GCPhys);
    8485VMMDECL(bool)    HWACCMIsNestedPagingActive(PVM pVM);

  • trunk/include/VBox/vm.h

    r19810 r19812  
    293293 * (NON-GLOBAL FLUSH) */
    294294#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL    RT_BIT_32(17)
     295/** Check for pending TLB shootdown actions. */
     296#define VMCPU_FF_TLB_SHOOTDOWN              RT_BIT_32(18)
     297/** Check for pending TLB flush action. */
     298#define VMCPU_FF_TLB_FLUSH_BIT              19
     299#define VMCPU_FF_TLB_FLUSH                  RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
    295300/** Check the interupt and trap gates */
    296301#define VMCPU_FF_TRPM_SYNC_IDT              RT_BIT_32(20)
    … …  
    303308/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
    304309#define VMCPU_FF_INHIBIT_INTERRUPTS         RT_BIT_32(24)
    305 /** Check for pending TLB shootdown actions. */
    306 #define VMCPU_FF_TLB_SHOOTDOWN              RT_BIT_32(25)
    307310/** CSAM needs to scan the page that's being executed */
    308311#define VMCPU_FF_CSAM_SCAN_PAGE             RT_BIT_32(26)
    … …  
    451454#define VM_FF_TESTANDCLEAR(pVM, iBit)        (ASMBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit))
    452455
     456/** @def VMCPU_FF_TESTANDCLEAR
     457 * Checks if one (!) force action in the specified set is pending and clears it atomically
     458 *
     459 * @returns true if the bit was set.
     460 * @returns false if the bit was clear.
     461 * @param   pVCpu   VMCPU Handle.
     462 * @param   iBit    Bit position to check and clear
     463 */
     464#define VMCPU_FF_TESTANDCLEAR(pVCpu, iBit)    (ASMBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit))
     465
    453466/** @def VMCPU_FF_ISPENDING
    454467 * Checks if one or more force action in the specified set is pending for the given VCPU.
    455468 *
    456  * @param   pVCpu     VMCPU Handle.
     469 * @param   pVCpu   VMCPU Handle.
    457470 * @param   fFlags  The flags to check for.
    458471 */

  • trunk/src/VBox/VMM/HWACCM.cpp

    r19697 r19812  
    351351        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID,              "/HWACCM/CPU%d/Flush/TLB/ASID");
    352352        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga,        "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
    353         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown,           "/HWACCM/CPU%d/Flush/TLB/Shootdown");
     353        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown,           "/HWACCM/CPU%d/Flush/Shootdown/Page");
     354        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush,      "/HWACCM/CPU%d/Flush/Shootdown/TLB");
    354355       
    355356        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset,              "/HWACCM/CPU%d/TSC/Offset");

  • trunk/src/VBox/VMM/HWACCMInternal.h

    r19697 r19812  
    641641    STAMCOUNTER             StatFlushTLBInvlpga;
    642642    STAMCOUNTER             StatTlbShootdown;
     643    STAMCOUNTER             StatTlbShootdownFlush;
    643644
    644645    STAMCOUNTER             StatSwitchGuestIrq;

  • trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp

    r19808 r19812  
    8080}
    8181
     82#ifndef IN_RC
     83/**
     84 * Flush the TLBs of all VCPUs
     85 *
     86 * @returns VBox status code.
     87 * @param   pVM       The VM to operate on.
     88 */
     89VMMDECL(int) HWACCMFlushAllTLBs(PVM pVM)
     90{
     91    if (pVM->cCPUs == 1)
     92        return HWACCMFlushTLB(&pVM->aCpus[0]);
     93
     94    VMCPUID idThisCpu = VMMGetCpuId(pVM);
     95
     96    for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
     97    {
     98        PVMCPU pVCpu = &pVM->aCpus[idCpu];
     99
     100        VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
     101        if (idThisCpu == idCpu)
     102            continue;
     103
     104        if (VMCPU_GET_STATE(pVCpu) == VMCPUSTATE_STARTED_EXEC)
     105        {
     106            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdownFlush);
     107#ifdef IN_RING0
     108            RTMpPokeCpu(idCpu);
     109#else
     110            VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
     111#endif
     112        }
     113        else
     114            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBManual);
     115    }
     116    return VINF_SUCCESS;
     117}
     118#endif
     119
    82120/**
    83121 * Checks if nested paging is enabled

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r19698 r19812  
    914914    }
    915915
    916     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
    917 
    918916    /* When external interrupts are pending, we should exit the VM when IF is set. */
    919917    /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
    … …  
    987985        goto end;
    988986    }
     987
     988    /* Disable interrupts to make sure a poke will interrupt execution.
     989     * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
     990     */
     991    RTCCUINTREG uFlags = ASMIntDisableFlags();
     992    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
    989993
    990994    pCpu = HWACCMR0GetCurrentCpu();
    … …  
    10021006
    10031007    pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
     1008
     1009    /* Check for tlb shootdown flushes. */
     1010    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
     1011        pVCpu->hwaccm.s.fForceTLBFlush = true;
    10041012
    10051013    /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
    … …  
    10731081    TMNotifyEndOfExecution(pVCpu);
    10741082    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
     1083    ASMSetFlags(uFlags);
    10751084    STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
    10761085

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r19773 r19812  
    18281828        Assert(!pCpu->fFlushTLB);
    18291829
     1830    /* Check for tlb shootdown flushes. */
     1831    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
     1832        pVCpu->hwaccm.s.fForceTLBFlush = true;
     1833
    18301834    pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
    18311835    pCpu->fFlushTLB           = false;
    … …  
    18871891
    18881892    pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
     1893
     1894    /* Check for tlb shootdown flushes. */
     1895    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
     1896        pVCpu->hwaccm.s.fForceTLBFlush = true;
    18891897
    18901898    /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
    … …  
    21072115    /** @todo check timers?? */
    21082116
    2109     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
    2110 
    21112117    /* TPR caching using CR8 is only available in 64 bits mode */
    21122118    /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
    … …  
    21852191    if (rc != VINF_SUCCESS)
    21862192        goto end;
     2193
     2194    /* Disable interrupts to make sure a poke will interrupt execution.
     2195     * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
     2196     */
     2197    RTCCUINTREG uFlags = ASMIntDisableFlags();
     2198    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
    21872199
    21882200    /* Deal with tagged TLB setup and invalidation. */
    … …  
    22242236    TMNotifyEndOfExecution(pVCpu);
    22252237    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
     2238    ASMSetFlags(uFlags);
    22262239
    22272240    AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
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