Changeset 21705 in vbox for trunk/src/VBox/VMM/HWACCM.cpp

Timestamp:

Jul 17, 2009 3:28:03 PM (15 years ago)

Author:

vboxsync

Message:

Logging changes

File:

• trunk/src/VBox/VMM/HWACCM.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -1401 +1401 @@
 DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
 {
+    Log(("hwaccmR3RemovePatches\n"));
     for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
     {
@@ -1454 +1455 @@
 VMMR3DECL(int)  HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
 {
+    Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
+
     /* Current TPR patching only applies to AMD cpus.
      * May need to be extended to Intel CPUs without the APIC TPR hardware optimization.
@@ -1479 +1482 @@
 VMMR3DECL(int)  HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
 {
+    Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
+
     Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
     Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
@@ -1571 +1576 @@
     unsigned     cbOp;
 
-    Log(("Replace TPR access at %RGv\n", pCtx->rip));
+    Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
 
     int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
@@ -1707 +1712 @@
 #endif
 
-    Log(("Patch TPR access at %RGv\n", pCtx->rip));
+    Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
 
     rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);