Changeset 26157 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 2, 2010 6:02:15 PM (15 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 22 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r25780 r26157 2105 2105 if (fGCEnabled) 2106 2106 { 2107 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");2107 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)"); 2108 2108 if (RT_FAILURE(rc)) 2109 2109 return rc; 2110 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");2110 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)"); 2111 2111 if (RT_FAILURE(rc)) 2112 2112 return rc; -
trunk/src/VBox/Devices/EFI/DevEFI.cpp
r26110 r26157 318 318 LogRel(("EFI Panic: Unexpected trap!!\n")); 319 319 #ifdef VBOX_STRICT 320 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: Unexpected trap during early bootstrap!\n");320 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: Unexpected trap during early bootstrap!\n"); 321 321 #else 322 322 AssertReleaseMsgFailed(("Unexpected trap during early EFI bootstrap!!\n")); … … 332 332 LogRel(("EFI Panic: %s\n", pThis->szPanicMsg)); 333 333 #ifdef VBOX_STRICT 334 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: %s\n", pThis->szPanicMsg);334 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "EFI Panic: %s\n", pThis->szPanicMsg); 335 335 #else 336 336 return VERR_INTERNAL_ERROR; … … 432 432 FwCommonPlantMpsTable(pDevIns, 433 433 pThis->au8DMIPage + VBOX_DMI_TABLE_SIZE, 434 pThis->cCpus); 434 pThis->cCpus); 435 435 436 436 /* -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r26001 r26157 6056 6056 if (pThis->fGCEnabled) 6057 6057 { 6058 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");6058 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)"); 6059 6059 if (RT_FAILURE(rc)) 6060 6060 return rc; 6061 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");6061 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)"); 6062 6062 if (RT_FAILURE(rc)) 6063 6063 return rc; 6064 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");6064 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)"); 6065 6065 if (RT_FAILURE(rc)) 6066 6066 return rc; 6067 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");6067 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)"); 6068 6068 if (RT_FAILURE(rc)) 6069 6069 return rc; 6070 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");6070 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)"); 6071 6071 if (RT_FAILURE(rc)) 6072 6072 return rc; 6073 6073 #ifdef CONFIG_BOCHS_VBE 6074 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");6074 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)"); 6075 6075 if (RT_FAILURE(rc)) 6076 6076 return rc; 6077 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");6077 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)"); 6078 6078 if (RT_FAILURE(rc)) 6079 6079 return rc; … … 6083 6083 and try to map other devices there */ 6084 6084 /* Old Bochs. */ 6085 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");6085 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)"); 6086 6086 if (RT_FAILURE(rc)) 6087 6087 return rc; 6088 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");6088 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)"); 6089 6089 if (RT_FAILURE(rc)) 6090 6090 return rc; … … 6141 6141 if (pThis->fGCEnabled) 6142 6142 { 6143 rc = PDMDevHlpMMIORegister GC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");6143 rc = PDMDevHlpMMIORegisterRC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill"); 6144 6144 if (RT_FAILURE(rc)) 6145 6145 return rc; -
trunk/src/VBox/Devices/Input/DevPS2.cpp
r26001 r26157 1647 1647 if (fGCEnabled) 1648 1648 { 1649 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x60, 1, 0, "kbdIOPortDataWrite", "kbdIOPortDataRead", NULL, NULL, "PC Keyboard - Data");1649 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x60, 1, 0, "kbdIOPortDataWrite", "kbdIOPortDataRead", NULL, NULL, "PC Keyboard - Data"); 1650 1650 if (RT_FAILURE(rc)) 1651 1651 return rc; 1652 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x64, 1, 0, "kbdIOPortCommandWrite", "kbdIOPortStatusRead", NULL, NULL, "PC Keyboard - Command / Status");1652 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x64, 1, 0, "kbdIOPortCommandWrite", "kbdIOPortStatusRead", NULL, NULL, "PC Keyboard - Command / Status"); 1653 1653 if (RT_FAILURE(rc)) 1654 1654 return rc; -
trunk/src/VBox/Devices/Network/DevE1000.cpp
r26001 r26157 1342 1342 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n", 1343 1343 INSTANCE(pState), RT_SRC_POS_ARGS, rc)); 1344 PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,1344 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS, 1345 1345 "%s Failed to enter critical section, rc=%Rrc\n", 1346 1346 INSTANCE(pState), rc); … … 3665 3665 case 4: mask = 0xFFFFFFFF; break; 3666 3666 default: 3667 return PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,3667 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS, 3668 3668 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n", 3669 3669 szInst, uOffset, cb); … … 3677 3677 mask <<= shift; 3678 3678 if (!mask) 3679 return PDMDev iceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,3679 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS, 3680 3680 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n", 3681 3681 szInst, uOffset, cb); … … 3846 3846 { 3847 3847 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb)); 3848 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);3848 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb); 3849 3849 } 3850 3850 else … … 3879 3879 { 3880 3880 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb)); 3881 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);3881 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb); 3882 3882 } 3883 3883 else … … 3930 3930 { 3931 3931 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb)); 3932 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);3932 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb); 3933 3933 } 3934 3934 else … … 3953 3953 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious 3954 3954 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */ 3955 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);3955 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port); 3956 3956 } 3957 3957 } … … 4041 4041 if (pState->fGCEnabled) 4042 4042 { 4043 rc = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,4043 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0, 4044 4044 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000"); 4045 4045 } … … 4058 4058 if (pState->fGCEnabled) 4059 4059 { 4060 rc = PDMDevHlpMMIORegister GC(pPciDev->pDevIns, GCPhysAddress, cb, 0,4060 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, 0, 4061 4061 "e1kMMIOWrite", "e1kMMIORead", NULL); 4062 4062 } … … 5175 5175 5176 5176 /* Create transmit queue */ 5177 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5178 5177 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5178 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3); 5179 5179 if (RT_FAILURE(rc)) 5180 5180 return rc; … … 5183 5183 5184 5184 /* Create the RX notifier signaller. */ 5185 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5186 5185 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5186 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3); 5187 5187 if (RT_FAILURE(rc)) 5188 5188 return rc; … … 5283 5283 e1kHardReset(pState); 5284 5284 5285 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");5285 rc = PDMDevHlpThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX"); 5286 5286 if (RT_FAILURE(rc)) 5287 5287 return rc; -
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r26001 r26157 3664 3664 case 4: *pu32 = pcnetIoportReadU32(pThis, Port, &rc); break; 3665 3665 default: 3666 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3666 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3667 3667 "pcnetIOPortRead: unsupported op size: offset=%#10x cb=%u\n", 3668 3668 Port, cb); … … 3707 3707 case 4: rc = pcnetIoportWriteU32(pThis, Port, u32); break; 3708 3708 default: 3709 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3709 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3710 3710 "pcnetIOPortWrite: unsupported op size: offset=%#10x cb=%u\n", 3711 3711 Port, cb); … … 3755 3755 case 4: *(uint32_t *)pv = pcnetMMIOReadU32(pThis, GCPhysAddr); break; 3756 3756 default: 3757 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3757 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3758 3758 "pcnetMMIORead: unsupported op size: address=%RGp cb=%u\n", 3759 3759 GCPhysAddr, cb); … … 3808 3808 case 4: pcnetMMIOWriteU32(pThis, GCPhysAddr, *(uint32_t *)pv); break; 3809 3809 default: 3810 rc = PDMDev iceDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,3810 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, 3811 3811 "pcnetMMIOWrite: unsupported op size: address=%RGp cb=%u\n", 3812 3812 GCPhysAddr, cb); … … 3936 3936 if (pThis->fGCEnabled) 3937 3937 { 3938 rc = PDMDevHlpIOPortRegister GC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",3938 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite", 3939 3939 "pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom"); 3940 3940 if (RT_FAILURE(rc)) 3941 3941 return rc; 3942 rc = PDMDevHlpIOPortRegister GC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",3942 rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite", 3943 3943 "pcnetIOPortRead", NULL, NULL, "PCNet"); 3944 3944 if (RT_FAILURE(rc)) … … 5160 5160 * Create the transmit queue. 5161 5161 */ 5162 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5163 5162 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5163 pcnetXmitQueueConsumer, true, "PCNet-Xmit", &pThis->pXmitQueueR3); 5164 5164 if (RT_FAILURE(rc)) 5165 5165 return rc; … … 5170 5170 * Create the RX notifer signaller. 5171 5171 */ 5172 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,5173 5172 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 5173 pcnetCanRxQueueConsumer, true, "PCNet-Rcv", &pThis->pCanRxQueueR3); 5174 5174 if (RT_FAILURE(rc)) 5175 5175 return rc; … … 5230 5230 5231 5231 /* Create asynchronous thread */ 5232 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pThis->pSendThread, pThis, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX");5232 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pSendThread, pThis, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX"); 5233 5233 AssertRCReturn(rc, rc); 5234 5234 -
trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
r26055 r26157 1428 1428 NULL, NULL, "VirtioNet"); 1429 1429 AssertRCReturn(rc, rc); 1430 rc = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, pState->VPCI.addrIOPort,1430 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->VPCI.addrIOPort, 1431 1431 cb, 0, "vnetIOPortOut", "vnetIOPortIn", 1432 1432 NULL, NULL, "VirtioNet"); … … 1711 1711 1712 1712 /* Create the RX notifier signaller. */ 1713 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,1714 1713 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 1714 vnetCanRxQueueConsumer, true, "VNet-Rcv", &pState->pCanRxQueueR3); 1715 1715 if (RT_FAILURE(rc)) 1716 1716 return rc; -
trunk/src/VBox/Devices/PC/DevACPI.cpp
r26115 r26157 471 471 [14] reserved 472 472 [13] COUNT_SIZE_CAP counter size 473 [12:8] number of comparators in first timer block 473 [12:8] number of comparators in first timer block 474 474 [7:0] hardware rev ID */ 475 475 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */ … … 1790 1790 #undef R 1791 1791 1792 /* register GC stuff */1792 /* register RC stuff */ 1793 1793 if (pThis->fGCEnabled) 1794 1794 { 1795 rc = PDMDevHlpIOPortRegister GC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),1795 rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET), 1796 1796 1, 0, NULL, "acpiPMTmrRead", 1797 1797 NULL, NULL, "ACPI PM Timer"); -
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r25058 r26157 2914 2914 pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns); 2915 2915 2916 rc = PDMDevHlpMMIORegister GC(pDevIns, ApicBase, 0x1000, 0,2916 rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, 0, 2917 2917 "apicMMIOWrite", "apicMMIORead", NULL); 2918 2918 if (RT_FAILURE(rc)) … … 3269 3269 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns); 3270 3270 3271 rc = PDMDevHlpMMIORegister GC(pDevIns, 0xfec00000, 0x1000, 0,3271 rc = PDMDevHlpMMIORegisterRC(pDevIns, 0xfec00000, 0x1000, 0, 3272 3272 "ioapicMMIOWrite", "ioapicMMIORead", NULL); 3273 3273 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r24012 r26157 991 991 if (fGCEnabled) 992 992 { 993 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");993 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0"); 994 994 if (RT_FAILURE(rc)) 995 995 return rc; 996 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");996 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1"); 997 997 if (RT_FAILURE(rc)) 998 998 return rc; … … 1019 1019 { 1020 1020 RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns); 1021 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),1021 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]), 1022 1022 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr"); 1023 1023 if (RT_FAILURE(rc)) 1024 1024 return rc; 1025 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),1025 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]), 1026 1026 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr"); 1027 1027 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/PC/DevPcArch.c
r25647 r26157 64 64 int rc; 65 65 NOREF(pvUser); NOREF(pDevIns); NOREF(pu32); 66 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb);66 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb); 67 67 if (rc == VINF_SUCCESS) 68 68 rc = VERR_IOM_IOPORT_UNUSED; … … 115 115 case 0xfc: 116 116 default: 117 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);117 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 118 118 break; 119 119 } … … 122 122 } 123 123 else 124 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);124 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 125 125 return rc; 126 126 } … … 177 177 return VINF_SUCCESS; 178 178 } 179 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb);179 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d\n", Port, cb); 180 180 } 181 181 … … 210 210 return VINF_SUCCESS; 211 211 } 212 return PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32);212 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Port=%#x cb=%d u32=%#x\n", Port, cb, u32); 213 213 } 214 214 -
trunk/src/VBox/Devices/PC/DevPit-i8254.cpp
r24265 r26157 1052 1052 if (fGCEnabled) 1053 1053 { 1054 rc = PDMDevHlpIOPortRegister GC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");1054 rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer"); 1055 1055 if (RT_FAILURE(rc)) 1056 1056 return rc; … … 1070 1070 if (fGCEnabled) 1071 1071 { 1072 rc = PDMDevHlpIOPortRegister GC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");1072 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker"); 1073 1073 if (RT_FAILURE(rc)) 1074 1074 return rc; -
trunk/src/VBox/Devices/PC/DevRTC.cpp
r25127 r26157 962 962 if (fGCEnabled) 963 963 { 964 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->IOPortBase, 2, 0,964 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, 2, 0, 965 965 "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS"); 966 966 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Parallel/DevParallel.cpp
r26001 r26157 791 791 if (pThis->fGCEnabled) 792 792 { 793 rc = PDMDevHlpIOPortRegister GC(pDevIns, io_base, 8, 0, "parallelIOPortWrite",793 rc = PDMDevHlpIOPortRegisterRC(pDevIns, io_base, 8, 0, "parallelIOPortWrite", 794 794 "parallelIOPortRead", NULL, NULL, "Parallel"); 795 795 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Samples/VBoxSampleDevice.cpp
r22985 r26157 58 58 */ 59 59 AssertMsgReturn(pDevIns->u32Version == PDM_DEVINS_VERSION, ("%#x, expected %#x\n", pDevIns->u32Version, PDM_DEVINS_VERSION), VERR_VERSION_MISMATCH); 60 AssertMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLP _VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLP_VERSION), VERR_VERSION_MISMATCH);60 AssertMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLPR3_VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLPR3_VERSION), VERR_VERSION_MISMATCH); 61 61 62 62 return VINF_SUCCESS; … … 70 70 */ 71 71 AssertLogRelMsgReturn(pDevIns->u32Version == PDM_DEVINS_VERSION, ("%#x, expected %#x\n", pDevIns->u32Version, PDM_DEVINS_VERSION), VERR_VERSION_MISMATCH); 72 AssertLogRelMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLP _VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLP_VERSION), VERR_VERSION_MISMATCH);72 AssertLogRelMsgReturn(pDevIns->pDevHlpR3->u32Version == PDM_DEVHLPR3_VERSION, ("%#x, expected %#x\n", pDevIns->pDevHlpR3->u32Version, PDM_DEVHLPR3_VERSION), VERR_VERSION_MISMATCH); 73 73 74 74 /* -
trunk/src/VBox/Devices/Serial/DevSerial.cpp
r26001 r26157 922 922 if (pThis->fGCEnabled) 923 923 { 924 rc = PDMDevHlpIOPortRegister GC(pDevIns, io_base, 8, 0, "serialIOPortWrite",924 rc = PDMDevHlpIOPortRegisterRC(pDevIns, io_base, 8, 0, "serialIOPortWrite", 925 925 "serialIOPortRead", NULL, NULL, "Serial"); 926 926 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r26001 r26157 2315 2315 if (pThis->fGCEnabled) 2316 2316 { 2317 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,2317 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 2318 2318 "ahciMMIOWrite", "ahciMMIORead", NULL); 2319 2319 if (RT_FAILURE(rc)) … … 2354 2354 if (pThis->fGCEnabled) 2355 2355 { 2356 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,2356 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0, 2357 2357 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake"); 2358 2358 if (RT_FAILURE(rc)) … … 6377 6377 6378 6378 /* Create the async IO thread. */ 6379 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,6380 6379 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0, 6380 RTTHREADTYPE_IO, szName); 6381 6381 if (RT_FAILURE(rc)) 6382 6382 { … … 6641 6641 * Create the transmit queue. 6642 6642 */ 6643 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), 30*32 /*Maximum of 30 ports multiplied with 32 tasks each port*/, 0,6644 6643 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), 30*32 /*Maximum of 30 ports multiplied with 32 tasks each port*/, 0, 6644 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3); 6645 6645 if (RT_FAILURE(rc)) 6646 6646 return rc; … … 6832 6832 6833 6833 6834 rc = PDMDevHlp PDMThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,6835 6834 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0, 6835 RTTHREADTYPE_IO, szName); 6836 6836 AssertMsgRC(rc, ("%s: Async IO Thread creation for %s failed rc=%Rrc\n", szName, rc)); 6837 6837 } … … 6931 6931 if (pThis->fGCEnabled) 6932 6932 { 6933 rc = PDMDevHlpIOPortRegister GC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i,6933 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase1, 8, (RTGCPTR)i, 6934 6934 "ahciIOPortWrite1", "ahciIOPortRead1", NULL, NULL, "AHCI GC"); 6935 6935 if (RT_FAILURE(rc)) … … 6952 6952 if (pThis->fGCEnabled) 6953 6953 { 6954 rc = PDMDevHlpIOPortRegister GC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i,6954 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pCtl->IOPortBase2, 1, (RTGCPTR)i, 6955 6955 "ahciIOPortWrite2", "ahciIOPortRead2", NULL, NULL, "AHCI GC"); 6956 6956 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r26049 r26157 5225 5225 if (pThis->fGCEnabled) 5226 5226 { 5227 rc2 = PDMDevHlpIOPortRegister GC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,5227 rc2 = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8, 5228 5228 (RTGCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA"); 5229 5229 AssertRC(rc2); … … 6694 6694 if (fGCEnabled) 6695 6695 { 6696 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i,6696 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i, 6697 6697 "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1"); 6698 6698 if (RT_FAILURE(rc)) … … 6720 6720 if (fGCEnabled) 6721 6721 { 6722 rc = PDMDevHlpIOPortRegister GC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,6722 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i, 6723 6723 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2"); 6724 6724 if (RT_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r26001 r26157 1920 1920 if (pThis->fGCEnabled) 1921 1921 { 1922 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,1922 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 1923 1923 "buslogicMMIOWrite", "buslogicMMIORead", NULL); 1924 1924 if (RT_FAILURE(rc)) … … 1945 1945 if (pThis->fGCEnabled) 1946 1946 { 1947 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, 32,1947 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32, 1948 1948 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic"); 1949 1949 if (RT_FAILURE(rc)) … … 2608 2608 2609 2609 /* Intialize task queue. */ 2610 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0,2611 2610 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 5, 0, 2611 buslogicNotifyQueueConsumer, true, "BugLogicTask", &pThis->pNotifierQueueR3); 2612 2612 if (RT_FAILURE(rc)) 2613 2613 return rc; -
trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
r26001 r26157 3666 3666 if (pThis->fGCEnabled) 3667 3667 { 3668 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,3668 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 3669 3669 "lsilogicMMIOWrite", "lsilogicMMIORead", NULL); 3670 3670 if (RT_FAILURE(rc)) … … 3692 3692 if (pThis->fGCEnabled) 3693 3693 { 3694 rc = PDMDevHlpMMIORegister GC(pDevIns, GCPhysAddress, cb, 0,3694 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, 0, 3695 3695 "lsilogicDiagnosticWrite", "lsilogicDiagnosticRead", NULL); 3696 3696 if (RT_FAILURE(rc)) … … 3715 3715 if (pThis->fGCEnabled) 3716 3716 { 3717 rc = PDMDevHlpIOPortRegister GC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,3717 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE, 3718 3718 0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, "LsiLogic"); 3719 3719 if (RT_FAILURE(rc)) … … 4501 4501 4502 4502 /* Intialize task queue. */ 4503 rc = PDMDevHlp PDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,4504 4503 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0, 4504 lsilogicNotifyQueueConsumer, true, "LsiLogic-Task", &pThis->pNotificationQueueR3); 4505 4505 if (RT_FAILURE(rc)) 4506 4506 return rc; -
trunk/src/VBox/Devices/Storage/VBoxSCSI.cpp
r21321 r26157 192 192 /* This is a read from the device. */ 193 193 ASMAtomicXchgBool(&pVBoxSCSI->fBusy, true); 194 rc = VERR_MORE_DATA; /* @todo:Better return value to indicate ready command? */194 rc = VERR_MORE_DATA; /** @todo Better return value to indicate ready command? */ 195 195 } 196 196 } … … 308 308 RTGCPTR GCDst = *pGCPtrDst; 309 309 uint32_t cbTransfer = *pcTransfer * cb; 310 int rc = VINF_SUCCESS;311 310 312 311 LogFlowFunc(("pDevIns=%#p pVBoxSCSI=%#p iRegister=%d cTransfer=%u cb=%u\n", … … 317 316 Assert(pVBoxSCSI->pBuf); 318 317 319 rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVMCPU(pDevIns), GCDst, pVBoxSCSI->pBuf, cbTransfer);318 int rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVMCPU(pDevIns), GCDst, pVBoxSCSI->pBuf, cbTransfer); 320 319 AssertRC(rc); 321 320 … … 337 336 338 337 int vboxscsiWriteString(PPDMDEVINS pDevIns, PVBOXSCSI pVBoxSCSI, uint8_t iRegister, 339 RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)338 RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb) 340 339 { 341 340 RTGCPTR GCSrc = *pGCPtrSrc; 342 341 uint32_t cbTransfer = *pcTransfer * cb; 343 int rc = VINF_SUCCESS;344 342 345 343 /* Read string only valid for data in register. */ … … 347 345 AssertMsg(cbTransfer == 512, ("Only 512 byte transfers are allowed\n")); 348 346 349 rc = PGMPhysSimpleReadGCPtr(PDMDevHlpGetVMCPU(pDevIns), pVBoxSCSI->pBuf, GCSrc, cbTransfer); 347 348 int rc = PDMDevHlpPhysReadGCVirt(pDevIns, pVBoxSCSI->pBuf, GCSrc, cbTransfer); 350 349 AssertRC(rc); 351 350 -
trunk/src/VBox/Devices/VirtIO/Virtio.cpp
r25985 r26157 378 378 { 379 379 *pu32 = 0xFFFFFFFF; 380 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: "380 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: " 381 381 "no valid port at offset port=%RTiop " 382 382 "cb=%08x\n", szInst, port, cb); … … 513 513 rc = pfnSetConfig(pState, port - VPCI_CONFIG, cb, &u32); 514 514 else 515 rc = PDMDev iceDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb);515 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset port=%RTiop cb=%08x\n", szInst, port, cb); 516 516 break; 517 517 }
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