Changeset 28388 in vbox for trunk/src/VBox/Devices/Storage/DevAHCI.cpp
- Timestamp:
- Apr 15, 2010 7:31:27 PM (15 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r28380 r28388 226 226 227 227 /** 228 * Transfer type. 229 */ 230 typedef enum AHCITXDIR 231 { 232 /** Invalid */ 233 AHCITXDIR_INVALID = 0, 234 /** None */ 235 AHCITXDIR_NONE, 236 /** Read */ 237 AHCITXDIR_READ, 238 /** Write */ 239 AHCITXDIR_WRITE, 240 /** Flush */ 241 AHCITXDIR_FLUSH 242 } AHCITXDIR; 243 244 /** 228 245 * A task state. 229 246 */ … … 243 260 RTGCPHYS GCPhysCmdHdrAddr; 244 261 /** Data direction. */ 245 uint8_t uTxDir;262 AHCITXDIR enmTxDir; 246 263 /** Start offset. */ 247 264 uint64_t uOffset; … … 2696 2713 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK; 2697 2714 pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciPortTaskState->cmdFis[AHCI_CMDFIS_SECTN] & ~7) 2698 | ((pAhciPortTaskState-> uTxDir != PDMBLOCKTXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)2715 | ((pAhciPortTaskState->enmTxDir != AHCITXDIR_WRITE) ? ATAPI_INT_REASON_IO : 0) 2699 2716 | (!pAhciPortTaskState->cbTransfer ? ATAPI_INT_REASON_CD : 0); 2700 2717 pAhciPort->uATAPISenseKey = SCSI_SENSE_NONE; … … 3546 3563 } 3547 3564 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048); 3548 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;3565 iTxDir = AHCITXDIR_READ; 3549 3566 } 3550 3567 break; … … 3595 3612 /* normal read */ 3596 3613 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2048); 3597 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;3614 iTxDir = AHCITXDIR_READ; 3598 3615 break; 3599 3616 case 0xf8: 3600 3617 /* read all data */ 3601 3618 atapiReadSectors(pAhciPort, pAhciPortTaskState, iATAPILBA, cSectors, 2352); 3602 iTxDir = PDMBLOCKTXDIR_FROM_DEVICE;3619 iTxDir = AHCITXDIR_READ; 3603 3620 break; 3604 3621 default: … … 4209 4226 pAhciPortTaskState->paSGEntries[0].u.temp.pvBuf = pAhciPortTaskState->pvBufferUnaligned; 4210 4227 4211 if (pAhciPortTaskState-> uTxDir == PDMBLOCKTXDIR_TO_DEVICE)4228 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE) 4212 4229 ahciCopyFromSGListIntoBuffer(pDevIns, &pAhciPortTaskState->paSGEntries[0]); 4213 4230 … … 4261 4278 if (pAhciPortTaskState->pfnPostProcess) 4262 4279 { 4263 ahciLog(("%s: Request with post processing.\n" ));4280 ahciLog(("%s: Request with post processing.\n", __FUNCTION__)); 4264 4281 4265 4282 ahciScatterGatherListGetTotalBufferSize(pAhciPort, pAhciPortTaskState); … … 4379 4396 * segments into the temporary buffer. 4380 4397 */ 4381 if (pAhciPortTaskState-> uTxDir == PDMBLOCKTXDIR_TO_DEVICE)4398 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE) 4382 4399 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr); 4383 4400 … … 4625 4642 * segments into the temporary buffer. 4626 4643 */ 4627 if (pAhciPortTaskState-> uTxDir == PDMBLOCKTXDIR_TO_DEVICE)4644 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE) 4628 4645 ahciCopyFromSGListIntoBuffer(pDevIns, pSGInfoCurr); 4629 4646 } … … 4667 4684 PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pSGInfoCurr->u.direct.PageLock); 4668 4685 } 4669 else if (pAhciPortTaskState-> uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)4686 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ) 4670 4687 { 4671 4688 /* Copy the data into the guest segments now. */ … … 4848 4865 &pAhciPortTaskState->cmdHdr, sizeof(CmdHdr)); 4849 4866 4850 if (pAhciPortTaskState-> uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)4867 if (pAhciPortTaskState->enmTxDir == AHCITXDIR_READ) 4851 4868 { 4852 4869 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, pAhciPortTaskState->cbTransfer); 4853 4870 pAhciPort->Led.Actual.s.fReading = 0; 4854 4871 } 4855 else 4872 else if (pAhciPortTaskState->enmTxDir == AHCITXDIR_WRITE) 4856 4873 { 4857 4874 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, pAhciPortTaskState->cbTransfer); … … 4908 4925 * @param pCmdHdr Pointer to the command header. 4909 4926 */ 4910 static intahciProcessCmd(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis)4911 { 4912 int rc = PDMBLOCKTXDIR_NONE;4927 static AHCITXDIR ahciProcessCmd(PAHCIPort pAhciPort, PAHCIPORTTASKSTATE pAhciPortTaskState, uint8_t *pCmdFis) 4928 { 4929 AHCITXDIR rc = AHCITXDIR_NONE; 4913 4930 bool fLBA48 = false; 4914 4931 CmdHdr *pCmdHdr = &pAhciPortTaskState->cmdHdr; … … 4924 4941 if (pAhciPort->pDrvBlock && !pAhciPort->fATAPI) 4925 4942 { 4943 int rc2; 4926 4944 uint16_t u16Temp[256]; 4927 4945 … … 4930 4948 4931 4949 /* Create scatter gather list. */ 4932 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, false);4933 if (RT_FAILURE(rc ))4934 AssertMsgFailed(("Creating list failed rc=%Rrc\n", rc ));4950 rc2 = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, false); 4951 if (RT_FAILURE(rc2)) 4952 AssertMsgFailed(("Creating list failed rc=%Rrc\n", rc2)); 4935 4953 4936 4954 /* Copy the buffer. */ … … 4938 4956 4939 4957 /* Destroy list. */ 4940 rc = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState);4941 if (RT_FAILURE(rc ))4942 AssertMsgFailed(("Freeing list failed rc=%Rrc\n", rc ));4958 rc2 = ahciScatterGatherListDestroy(pAhciPort, pAhciPortTaskState); 4959 if (RT_FAILURE(rc2)) 4960 AssertMsgFailed(("Freeing list failed rc=%Rrc\n", rc2)); 4943 4961 4944 4962 pAhciPortTaskState->uATARegError = 0; … … 4971 4989 break; 4972 4990 case 0x82: /* write cache disable */ 4973 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock); 4974 pAhciPortTaskState->uATARegError = 0; 4975 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK; 4991 rc = AHCITXDIR_FLUSH; 4976 4992 break; 4977 4993 case 0x03: … … 5000 5016 case ATA_FLUSH_CACHE_EXT: 5001 5017 case ATA_FLUSH_CACHE: 5002 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock); 5003 pAhciPortTaskState->uATARegError = 0; 5004 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK; 5018 rc = AHCITXDIR_FLUSH; 5005 5019 break; 5006 5020 case ATA_PACKET: … … 5012 5026 else 5013 5027 { 5014 rc= atapiParseCmdVirtualATAPI(pAhciPort, pAhciPortTaskState);5028 int rc2 = atapiParseCmdVirtualATAPI(pAhciPort, pAhciPortTaskState); 5015 5029 } 5016 5030 break; … … 5067 5081 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512; 5068 5082 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512; 5069 rc = PDMBLOCKTXDIR_FROM_DEVICE;5083 rc = AHCITXDIR_READ; 5070 5084 break; 5071 5085 } … … 5076 5090 pAhciPortTaskState->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * 512; 5077 5091 pAhciPortTaskState->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * 512; 5078 rc = PDMBLOCKTXDIR_TO_DEVICE;5092 rc = AHCITXDIR_WRITE; 5079 5093 break; 5080 5094 } … … 5083 5097 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512; 5084 5098 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512; 5085 rc = PDMBLOCKTXDIR_FROM_DEVICE;5099 rc = AHCITXDIR_READ; 5086 5100 break; 5087 5101 } … … 5090 5104 pAhciPortTaskState->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * 512; 5091 5105 pAhciPortTaskState->uOffset = ahciGetSectorQueued(pCmdFis) * 512; 5092 rc = PDMBLOCKTXDIR_TO_DEVICE;5106 rc = AHCITXDIR_WRITE; 5093 5107 break; 5094 5108 } … … 5147 5161 5148 5162 /* Set transfer direction. */ 5149 pAhciPortTaskState-> uTxDir = (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? PDMBLOCKTXDIR_TO_DEVICE : PDMBLOCKTXDIR_FROM_DEVICE;5163 pAhciPortTaskState->enmTxDir = (pAhciPortTaskState->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? AHCITXDIR_WRITE : AHCITXDIR_READ; 5150 5164 5151 5165 /* If this is an ATAPI command read the atapi command. */ … … 5216 5230 else 5217 5231 { 5218 int iTxDir;5232 AHCITXDIR enmTxDir; 5219 5233 PAHCIPORTTASKSTATE pAhciPortTaskState; 5220 5234 … … 5272 5286 } 5273 5287 5274 iTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis);5275 5276 if ( iTxDir != PDMBLOCKTXDIR_NONE)5288 enmTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, pAhciPortTaskState->cmdFis); 5289 5290 if (enmTxDir != AHCITXDIR_NONE) 5277 5291 { 5278 5292 if (pAhciPortTaskState->fQueued) … … 5283 5297 } 5284 5298 5285 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA); 5286 5287 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE) ? false : true); 5288 if (RT_FAILURE(rc)) 5289 AssertMsgFailed(("%s: Failed to process command %Rrc\n", __FUNCTION__, rc)); 5290 5291 if (iTxDir == PDMBLOCKTXDIR_FROM_DEVICE) 5299 if (enmTxDir != AHCITXDIR_FLUSH) 5300 { 5301 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA); 5302 5303 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (enmTxDir == AHCITXDIR_READ) ? false : true); 5304 if (RT_FAILURE(rc)) 5305 AssertMsgFailed(("%s: Failed to process command %Rrc\n", __FUNCTION__, rc)); 5306 } 5307 5308 if (enmTxDir == AHCITXDIR_FLUSH) 5309 { 5310 rc = pAhciPort->pDrvBlockAsync->pfnStartFlush(pAhciPort->pDrvBlockAsync, 5311 pAhciPortTaskState); 5312 } 5313 else if (enmTxDir == AHCITXDIR_READ) 5292 5314 { 5293 5315 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1; … … 5437 5459 && RT_LIKELY(!pAhciPort->fPortReset)) 5438 5460 { 5439 int iTxDir;5461 AHCITXDIR enmTxDir; 5440 5462 uint8_t uActTag; 5441 5463 … … 5487 5509 else 5488 5510 { 5489 iTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0]); 5490 5491 if (iTxDir != PDMBLOCKTXDIR_NONE) 5511 enmTxDir = ahciProcessCmd(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0]); 5512 5513 if (enmTxDir == AHCITXDIR_FLUSH) 5514 { 5515 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock); 5516 5517 /* Log the error. */ 5518 if ( RT_FAILURE(rc) 5519 && pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS) 5520 { 5521 LogRel(("AHCI#%u: Flush returned rc=%Rrc\n", 5522 pAhciPort->iLUN, rc)); 5523 } 5524 5525 if (RT_FAILURE(rc)) 5526 { 5527 pAhciPortTaskState->uATARegError = ID_ERR; 5528 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR; 5529 } 5530 else 5531 { 5532 pAhciPortTaskState->uATARegError = 0; 5533 pAhciPortTaskState->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK; 5534 } 5535 5536 if (pAhciPortTaskState->fQueued) 5537 uQueuedTasksFinished |= (1 << pAhciPortTaskState->uTag); 5538 else 5539 { 5540 /* Task is not queued send D2H FIS */ 5541 ahciSendD2HFis(pAhciPort, pAhciPortTaskState, &pAhciPortTaskState->cmdFis[0], true); 5542 } 5543 } 5544 else if (enmTxDir != AHCITXDIR_NONE) 5492 5545 { 5493 5546 uint64_t uOffset; … … 5496 5549 PAHCIPORTTASKSTATESGENTRY pSGInfoCurr; 5497 5550 5498 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, ( iTxDir == PDMBLOCKTXDIR_FROM_DEVICE) ? false : true);5551 rc = ahciScatterGatherListCreate(pAhciPort, pAhciPortTaskState, (enmTxDir == AHCITXDIR_READ) ? false : true); 5499 5552 if (RT_FAILURE(rc)) 5500 5553 AssertMsgFailed(("%s: Failed to get number of list elments %Rrc\n", __FUNCTION__, rc)); … … 5518 5571 AssertMsg(!(cbProcess % 512), ("Number of bytes to process is not sector aligned %lu\n", cbProcess)); 5519 5572 5520 if ( iTxDir == PDMBLOCKTXDIR_FROM_DEVICE)5573 if (enmTxDir == AHCITXDIR_READ) 5521 5574 { 5522 5575 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1; … … 5556 5609 LogRel(("AHCI#%u: %s at offset %llu (%u bytes left) returned rc=%Rrc\n", 5557 5610 pAhciPort->iLUN, 5558 iTxDir == PDMBLOCKTXDIR_FROM_DEVICE5611 enmTxDir == AHCITXDIR_READ 5559 5612 ? "Read" 5560 5613 : "Write",
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