VirtualBox

Changeset 30889 in vbox for trunk/src/VBox/VMM/PGMInternal.h


Ignore:
Timestamp:
Jul 17, 2010 1:54:47 AM (14 years ago)
Author:
vboxsync
Message:

PGM: Cleanups related to pending MMIO/#PF optimizations. Risky.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/PGMInternal.h

    r30843 r30889  
    9191
    9292/**
     93 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
     94 * VMX_EXIT_EPT_MISCONFIG.
     95 */
     96#if 0 /* ! remember to disable before committing ! XXX TODO  */
     97# define PGM_WITH_MMIO_OPTIMIZATIONS
     98#endif
     99
     100/**
    93101 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
    94102 */
    … …  
    266274# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
    267275     PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
     276#endif
     277
     278/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
     279 * Maps a GC physical page address to a virtual address.
     280 *
     281 * @returns VBox status code.
     282 * @param   pVCpu   The current CPU.
     283 * @param   GCPhys  The GC physical address to map to a virtual one.
     284 * @param   ppv     Where to store the virtual address. No need to cast this.
     285 *
     286 * @remark  In RC this uses PGMGCDynMapGCPage(), so it will consume of the
     287 *          small page window employeed by that function. Be careful.
     288 * @remark  There is no need to assert on the result.
     289 */
     290#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     291# define PGM_RCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) \
     292     pgmR0DynMapGCPageInlined(&(pVCpu)->CTX_SUFF(pVM)->pgm.s, GCPhys, (void **)(ppv))
     293#else
     294# define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) \
     295     PGM_GCPHYS_2_PTR((pVCpu)->CTX_SUFF(pVM), GCPhys, ppv)
    268296#endif
    269297
    … …  
    17641792    /** Shw: PAE page directory;    Gst: PAE page directory. */
    17651793    PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
    1766     /** Shw: PAE page directory;    Gst: no paging. */
     1794    /** Shw: PAE page directory;    Gst: no paging.             Note: +NP. */
    17671795    PGMPOOLKIND_PAE_PD_PHYS,
    17681796
    … …  
    18811909     * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
    18821910    bool volatile       fReusedFlushPending;
    1883     /** Used to mark the page as dirty (write monitoring if temporarily off. */
     1911    /** Used to mark the page as dirty (write monitoring is temporarily
     1912     *  off). */
    18841913    bool                fDirty;
    18851914
    … …  
    22692298
    22702299
     2300/**
     2301 * Page fault guest state for the AMD64 paging mode.
     2302 */
     2303typedef struct PGMPTWALKCORE
     2304{
     2305    /** The guest virtual address that is being resolved by the walk
     2306     *  (input). */
     2307    RTGCPTR         GCPtr;
     2308
     2309    /** The guest physcial address that is the result of the walk.
     2310     * @remarks only valid if fSucceeded is set.  */
     2311    RTGCPHYS        GCPhys;
     2312
     2313    /** Set if the walk succeeded, i.d. GCPhys is valid. */
     2314    bool            fSucceeded;
     2315    /** The level problem arrised at.
     2316     * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
     2317     * level 8.  This is 0 on success. */
     2318    uint8_t         uLevel;
     2319    /** Set if the page isn't present. */
     2320    bool            fNotPresent;
     2321    /** Encountered a bad physical address. */
     2322    bool            fBadPhysAddr;
     2323    /** Set if there was reserved bit violations. */
     2324    bool            fRsvdError;
     2325    /** Set if it involves a big page (2/4 MB). */
     2326    bool            fBigPage;
     2327    /** Set if it involves a gigantic page (1 GB). */
     2328    bool            fGigantPage;
     2329#if 0
     2330    /** Set if write access was attempted and not possible. */
     2331    bool            fWriteError;
     2332    /** Set if execute access was attempted and not possible. */
     2333    bool            fExecuteError;
     2334#endif
     2335    /** Unused. */
     2336    bool            afUnused[3];
     2337} PGMPTWALKCORE;
     2338
     2339
     2340/**
     2341 * Guest page table walk for the AMD64 mode.
     2342 */
     2343typedef struct PGMPTWALKGSTAMD64
     2344{
     2345    /** The common core. */
     2346    PGMPTWALKCORE   Core;
     2347
     2348    PX86PML4        pPml4;
     2349    PX86PML4E       pPml4e;
     2350    X86PML4E        Pml4e;
     2351
     2352    PX86PDPT        pPdpt;
     2353    PX86PDPE        pPdpe;
     2354    X86PDPE         Pdpe;
     2355
     2356    PX86PDPAE       pPd;
     2357    PX86PDEPAE      pPde;
     2358    X86PDEPAE       Pde;
     2359
     2360    PX86PTPAE       pPt;
     2361    PX86PTEPAE      pPte;
     2362    X86PTEPAE       Pte;
     2363} PGMPTWALKGSTAMD64;
     2364/** Pointer to a AMD64 guest page table walk. */
     2365typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
     2366/** Pointer to a const AMD64 guest page table walk. */
     2367typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
     2368
     2369/**
     2370 * Guest page table walk for the PAE mode.
     2371 */
     2372typedef struct PGMPTWALKGSTPAE
     2373{
     2374    /** The common core. */
     2375    PGMPTWALKCORE   Core;
     2376
     2377    PX86PDPT        pPdpt;
     2378    PX86PDPE        pPdpe;
     2379    X86PDPE         Pdpe;
     2380
     2381    PX86PDPAE       pPd;
     2382    PX86PDEPAE      pPde;
     2383    X86PDEPAE       Pde;
     2384
     2385    PX86PTPAE       pPt;
     2386    PX86PTEPAE      pPte;
     2387    X86PTEPAE       Pte;
     2388} PGMPTWALKGSTPAE;
     2389/** Pointer to a PAE guest page table walk. */
     2390typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
     2391/** Pointer to a const AMD64 guest page table walk. */
     2392typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
     2393
     2394/**
     2395 * Guest page table walk for the 32-bit mode.
     2396 */
     2397typedef struct PGMPTWALKGST32BIT
     2398{
     2399    /** The common core. */
     2400    PGMPTWALKCORE   Core;
     2401
     2402    PX86PD          pPd;
     2403    PX86PDE         pPde;
     2404    X86PDE          Pde;
     2405
     2406    PX86PT          pPt;
     2407    PX86PTE         pPte;
     2408    X86PTE          Pte;
     2409} PGMPTWALKGST32BIT;
     2410/** Pointer to a 32-bit guest page table walk. */
     2411typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
     2412/** Pointer to a const 32-bit guest page table walk. */
     2413typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
     2414
     2415
    22712416/** @name Paging mode macros
    2272  * @{ */
     2417 * @{
     2418 */
    22732419#ifdef IN_RC
    22742420# define PGM_CTX(a,b)                   a##RC##b
    … …  
    24972643     * detection. */
    24982644    bool                            fPhysWriteMonitoringEngaged;
     2645    /** Set if the CPU has less than 52-bit physical address width.
     2646     * This is used  */
     2647    bool                            fLessThan52PhysicalAddressBits;
    24992648    /** Alignment padding. */
    2500     bool                            afAlignment0[2];
     2649    bool                            afAlignment0[1];
    25012650
    25022651    /*
    … …  
    25192668    /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
    25202669    RTGCPHYS                        GCPhys4MBPSEMask;
     2670    /** Mask containing the invalid bits of a guest physical address.
     2671     * @remarks this does not stop at bit 52.  */
     2672    RTGCPHYS                        GCPhysInvAddrMask;
    25212673
    25222674    /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
    … …  
    27062858    RTGCPTR                         pvZeroPgRC;
    27072859    /** @}*/
     2860
     2861    /** @name   The Invalid MMIO page.
     2862     * This page is filled with 0xfeedface.
     2863     * @{ */
     2864    /** The host physical address of the invalid MMIO page. */
     2865    RTHCPHYS                        HCPhysMmioPg;
     2866    /** The host pysical address of the invalid MMIO page pluss all invalid
     2867     * physical address bits set.  This is used to trigger X86_TRAP_PF_RSVD.
     2868     * @remarks Check fLessThan52PhysicalAddressBits before use. */
     2869    RTHCPHYS                        HCPhysInvMmioPg;
     2870    /** The ring-3 mapping of the invalid MMIO page. */
     2871    RTR3PTR                         pvMmioPgR3;
     2872    /** @} */
     2873
    27082874
    27092875    /** The number of handy pages. */
    … …  
    29203086 * @param   pPGM   Pointer to PGMCPU instance data.
    29213087 */
    2922 #define PGMCPU2VM(pPGM)  ( (PVM)((char*)pPGM - pPGM->offVM) )
     3088#define PGMCPU2VM(pPGM)         ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
    29233089
    29243090/**
    … …  
    29273093 * @param   pPGM   Pointer to PGMCPU instance data.
    29283094 */
    2929 #define PGMCPU2PGM(pPGMCpu)  ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
     3095#define PGMCPU2PGM(pPGMCpu)     ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
    29303096
    29313097/**
    … …  
    29793145    /** The guest's page directory, static RC mapping. */
    29803146    RCPTRTYPE(PX86PD)               pGst32BitPdRC;
     3147    /** Mask containing the MBZ bits of a big page PDE. */
     3148    uint32_t                        fGst32BitMbzBigPdeMask;
     3149    /** Set if the page size extension (PSE) is enabled. */
     3150    bool                            fGst32BitPageSizeExtension;
     3151    /** Alignment padding. */
     3152    bool                            afAlignment4[3];
    29813153    /** @} */
    29823154
    … …  
    30093181    /** The physical addresses of the monitored guest page directories (PAE). */
    30103182    RTGCPHYS                        aGCPhysGstPaePDsMonitored[4];
     3183    /** Mask containing the MBZ PTE bits. */
     3184    uint64_t                        fGstPaeMbzPteMask;
     3185    /** Mask containing the MBZ PDE bits. */
     3186    uint64_t                        fGstPaeMbzPdeMask;
     3187    /** Mask containing the MBZ big page PDE bits. */
     3188    uint64_t                        fGstPaeMbzBigPdeMask;
     3189    /** Mask containing the MBZ PDPE bits. */
     3190    uint64_t                        fGstPaeMbzPdpeMask;
    30113191    /** @} */
    30123192
    … …  
    30213201    RTR0PTR                         alignment6b; /**< alignment equalizer. */
    30223202#endif
     3203    /** Mask containing the MBZ PTE bits. */
     3204    uint64_t                        fGstAmd64MbzPteMask;
     3205    /** Mask containing the MBZ PDE bits. */
     3206    uint64_t                        fGstAmd64MbzPdeMask;
     3207    /** Mask containing the MBZ big page PDE bits. */
     3208    uint64_t                        fGstAmd64MbzBigPdeMask;
     3209    /** Mask containing the MBZ PDPE bits. */
     3210    uint64_t                        fGstAmd64MbzPdpeMask;
     3211    /** Mask containing the MBZ big page PDPE bits. */
     3212    uint64_t                        fGstAmd64MbzBigPdpeMask;
     3213    /** Mask containing the MBZ PML4E bits. */
     3214    uint64_t                        fGstAmd64MbzPml4eMask;
    30233215    /** @} */
    30243216
    … …  
    34513643int             pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
    34523644
    3453 PX86PD          pgmGstLazyMap32BitPD(PPGMCPU pPGM);
    3454 PX86PDPT        pgmGstLazyMapPaePDPT(PPGMCPU pPGM);
    3455 PX86PDPAE       pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt);
    3456 PX86PML4        pgmGstLazyMapPml4(PPGMCPU pPGM);
     3645int             pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
     3646int             pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
     3647int             pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
     3648int             pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
    34573649
    34583650# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
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