Changeset 31569 in vbox for trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
- Timestamp:
- Aug 11, 2010 1:41:52 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (66 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r31565 r31569 70 70 * Local Functions * 71 71 *******************************************************************************/ 72 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, intrc, PCPUMCTX pCtx);72 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx); 73 73 static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu); 74 74 static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu); … … 726 726 * Injects an event (trap or external interrupt) 727 727 * 728 * @returns VBox status code. 728 * @returns VBox status code. Note that it may return VINF_EM_RESET to 729 * indicate a triple fault when injecting X86_XCPT_DF. 730 * 729 731 * @param pVM The VM to operate on. 730 732 * @param pVCpu The VMCPU to operate on. … … 2263 2265 2264 2266 VBOXSTRICTRC rc = VINF_SUCCESS; 2267 int rc2; 2265 2268 RTGCUINTREG val; 2266 2269 RTGCUINTREG exitReason = (RTGCUINTREG)VMX_EXIT_INVALID; … … 2299 2302 RTCCUINTREG val2; 2300 2303 2301 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2);2302 AssertRC(rc );2304 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2); 2305 AssertRC(rc2); 2303 2306 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2)); 2304 2307 … … 2311 2314 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n")); 2312 2315 2313 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2);2314 AssertRC(rc );2316 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2); 2317 AssertRC(rc2); 2315 2318 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2)); 2316 2319 … … 2329 2332 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n")); 2330 2333 2331 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2);2332 AssertRC(rc );2334 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2); 2335 AssertRC(rc2); 2333 2336 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2)); 2334 2337 … … 2341 2344 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n")); 2342 2345 2343 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2);2344 AssertRC(rc );2346 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2); 2347 AssertRC(rc2); 2345 2348 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2)); 2346 2349 … … 2393 2396 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); 2394 2397 /* Irq inhibition is no longer active; clear the corresponding VMX state. */ 2395 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);2396 AssertRC(rc );2398 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0); 2399 AssertRC(rc2); 2397 2400 } 2398 2401 } … … 2400 2403 { 2401 2404 /* Irq inhibition is no longer active; clear the corresponding VMX state. */ 2402 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);2403 AssertRC(rc );2405 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0); 2406 AssertRC(rc2); 2404 2407 } 2405 2408 … … 2425 2428 { 2426 2429 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)); 2427 AssertRC(rc);2428 2430 if (rc != VINF_SUCCESS) 2429 2431 { 2430 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", rc)); 2432 AssertRC(VBOXSTRICTRC_VAL(rc)); 2433 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc))); 2431 2434 goto end; 2432 2435 } … … 2504 2507 bool fPending; 2505 2508 2506 intrc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);2509 rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending); 2507 2510 AssertRC(rc2); 2508 2511 /* The TPR can be found at offset 0x80 in the APIC mmio page. */ … … 2516 2519 */ 2517 2520 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */ 2518 AssertRC( rc);2521 AssertRC(VBOXSTRICTRC_VAL(rc)); 2519 2522 2520 2523 if (pVM->hwaccm.s.fTPRPatchingActive) … … 2616 2619 /* Non-register state Guest Context */ 2617 2620 /** @todo change me according to cpu state */ 2618 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);2619 AssertRC(rc );2621 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE); 2622 AssertRC(rc2); 2620 2623 2621 2624 /** Set TLB flush state as checked until we return from the world switch. */ … … 2705 2708 2706 2709 /* Investigate why there was a VM-exit. */ 2707 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);2710 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason); 2708 2711 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]); 2709 2712 2710 2713 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */ 2711 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);2712 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);2713 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);2714 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError); 2715 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr); 2716 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo); 2714 2717 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */ 2715 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);2716 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);2717 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);2718 AssertRC(rc );2718 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode); 2719 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo); 2720 rc2 |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification); 2721 AssertRC(rc2); 2719 2722 2720 2723 /* Sync back the guest state */ 2721 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);2722 AssertRC(rc );2724 rc2 = VMXR0SaveGuestState(pVM, pVCpu, pCtx); 2725 AssertRC(rc2); 2723 2726 2724 2727 /* Note! NOW IT'S SAFE FOR LOGGING! */ … … 2727 2730 2728 2731 /* Check if an injected event was interrupted prematurely. */ 2729 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);2730 AssertRC(rc );2732 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val); 2733 AssertRC(rc2); 2731 2734 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val); 2732 2735 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo) … … 2741 2744 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo)) 2742 2745 { 2743 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);2744 AssertRC(rc );2746 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val); 2747 AssertRC(rc2); 2745 2748 pVCpu->hwaccm.s.Event.errCode = val; 2746 2749 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val)); … … 2775 2778 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80]) 2776 2779 { 2777 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);2778 AssertRC(rc );2780 rc2 = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]); 2781 AssertRC(rc2); 2779 2782 } 2780 2783 … … 2782 2785 2783 2786 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */ 2787 Assert(rc == VINF_SUCCESS); /* might consider VERR_IPE_UNINITIALIZED_STATUS here later... */ 2784 2788 switch (exitReason) 2785 2789 { … … 2843 2847 Log(("Forward #NM fault to the guest\n")); 2844 2848 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM); 2845 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);2846 AssertRC(rc );2849 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0); 2850 AssertRC(rc2); 2847 2851 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); 2848 2852 goto ResumeExecution; … … 2864 2868 /* Now we must update CR2. */ 2865 2869 pCtx->cr2 = exitQualification; 2866 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);2867 AssertRC(rc );2870 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 2871 AssertRC(rc2); 2868 2872 2869 2873 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); … … 2923 2927 { 2924 2928 Log(("Enable VT-x virtual APIC access filtering\n")); 2925 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);2926 AssertRC(rc );2929 rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P); 2930 AssertRC(rc2); 2927 2931 } 2928 2932 } … … 2930 2934 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */ 2931 2935 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification); 2932 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));2936 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc))); 2933 2937 2934 2938 if (rc == VINF_SUCCESS) … … 2956 2960 /* Now we must update CR2. */ 2957 2961 pCtx->cr2 = exitQualification; 2958 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);2959 AssertRC(rc );2962 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 2963 AssertRC(rc2); 2960 2964 2961 2965 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); … … 2964 2968 #ifdef VBOX_STRICT 2965 2969 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK) 2966 Log2(("PGMTrap0eHandler failed with %d\n", rc));2970 Log2(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc))); 2967 2971 #endif 2968 2972 /* Need to go back to the recompiler to emulate the instruction. */ … … 2982 2986 } 2983 2987 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip)); 2984 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);2985 AssertRC(rc );2988 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 2989 AssertRC(rc2); 2986 2990 2987 2991 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); … … 3027 3031 3028 3032 /* Resync DR7 */ 3029 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);3030 AssertRC(rc );3033 rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]); 3034 AssertRC(rc2); 3031 3035 3032 3036 Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip, exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7])); 3033 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);3034 AssertRC(rc );3037 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 3038 AssertRC(rc2); 3035 3039 3036 3040 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); … … 3038 3042 } 3039 3043 /* Return to ring 3 to deal with the debug exit code. */ 3040 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));3044 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3041 3045 break; 3042 3046 } … … 3048 3052 { 3049 3053 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip)); 3050 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);3051 AssertRC(rc );3054 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 3055 AssertRC(rc2); 3052 3056 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); 3053 3057 goto ResumeExecution; … … 3058 3062 goto ResumeExecution; 3059 3063 } 3060 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));3064 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3061 3065 break; 3062 3066 } … … 3074 3078 { 3075 3079 Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode)); 3076 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);3077 AssertRC(rc );3080 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 3081 AssertRC(rc2); 3078 3082 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); 3079 3083 goto ResumeExecution; … … 3084 3088 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip)); 3085 3089 3086 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);3087 if (RT_SUCCESS(rc ))3090 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 3091 if (RT_SUCCESS(rc2)) 3088 3092 { 3089 3093 bool fUpdateRIP = true; 3090 3094 3095 rc = VINF_SUCCESS; 3091 3096 Assert(cbOp == pDis->opsize); 3092 3097 switch (pDis->pCurInstr->opcode) … … 3101 3106 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->opsize); 3102 3107 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)); 3103 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);3104 AssertRC(rc );3108 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI); 3109 AssertRC(rc2); 3105 3110 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti); 3106 3111 break; … … 3131 3136 } 3132 3137 3133 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);3134 if (RT_FAILURE(rc ))3138 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); 3139 if (RT_FAILURE(rc2)) 3135 3140 { 3136 3141 rc = VERR_EM_INTERPRETER; … … 3138 3143 } 3139 3144 eflags.u = 0; 3140 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);3141 if (RT_FAILURE(rc ))3145 rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); 3146 if (RT_FAILURE(rc2)) 3142 3147 { 3143 3148 rc = VERR_EM_INTERPRETER; … … 3173 3178 } 3174 3179 3175 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);3176 if (RT_FAILURE(rc ))3180 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack); 3181 if (RT_FAILURE(rc2)) 3177 3182 { 3178 3183 rc = VERR_EM_INTERPRETER; … … 3184 3189 eflags.Bits.u1VM = 0; 3185 3190 3186 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);3187 if (RT_FAILURE(rc ))3191 rc2 = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); 3192 if (RT_FAILURE(rc2)) 3188 3193 { 3189 3194 rc = VERR_EM_INTERPRETER; … … 3209 3214 } 3210 3215 3211 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);3212 if (RT_FAILURE(rc ))3216 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); 3217 if (RT_FAILURE(rc2)) 3213 3218 { 3214 3219 rc = VERR_EM_INTERPRETER; 3215 3220 break; 3216 3221 } 3217 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));3218 if (RT_FAILURE(rc ))3222 rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame)); 3223 if (RT_FAILURE(rc2)) 3219 3224 { 3220 3225 rc = VERR_EM_INTERPRETER; … … 3243 3248 3244 3249 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); 3245 AssertRC( rc);3250 AssertRC(VBOXSTRICTRC_VAL(rc)); 3246 3251 fUpdateRIP = false; 3247 3252 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); … … 3261 3266 3262 3267 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); 3263 AssertRC( rc);3268 AssertRC(VBOXSTRICTRC_VAL(rc)); 3264 3269 fUpdateRIP = false; 3265 3270 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); … … 3278 3283 3279 3284 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); 3280 AssertRC( rc);3285 AssertRC(VBOXSTRICTRC_VAL(rc)); 3281 3286 fUpdateRIP = false; 3282 3287 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); … … 3305 3310 rc = VERR_EM_INTERPRETER; 3306 3311 3307 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));3312 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", VBOXSTRICTRC_VAL(rc))); 3308 3313 break; 3309 3314 } … … 3333 3338 3334 3339 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip)); 3335 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);3336 AssertRC(rc );3340 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 3341 AssertRC(rc2); 3337 3342 3338 3343 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3); … … 3346 3351 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode)); 3347 3352 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode); 3348 AssertRC( rc);3353 AssertRC(VBOXSTRICTRC_VAL(rc)); /* Strict RC check below. */ 3349 3354 3350 3355 /* Go back to ring 3 in case of a triple fault. */ … … 3379 3384 Assert(pVM->hwaccm.s.fNestedPaging); 3380 3385 3381 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);3382 AssertRC(rc );3386 rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys); 3387 AssertRC(rc2); 3383 3388 Assert(((exitQualification >> 7) & 3) != 2); 3384 3389 … … 3410 3415 { 3411 3416 Log(("Enable VT-x virtual APIC access filtering\n")); 3412 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);3413 AssertRC(rc );3417 rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P); 3418 AssertRC(rc2); 3414 3419 } 3415 3420 } … … 3424 3429 /* Handle the pagefault trap for the nested shadow table. */ 3425 3430 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys); 3426 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));3431 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3427 3432 if (rc == VINF_SUCCESS) 3428 3433 { /* We've successfully synced our shadow pages, so let's just continue execution. */ … … 3436 3441 #ifdef VBOX_STRICT 3437 3442 if (rc != VINF_EM_RAW_EMULATE_INSTR) 3438 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));3443 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc))); 3439 3444 #endif 3440 3445 /* Need to go back to the recompiler to emulate the instruction. */ … … 3449 3454 Assert(pVM->hwaccm.s.fNestedPaging); 3450 3455 3451 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);3452 AssertRC(rc );3456 rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys); 3457 AssertRC(rc2); 3453 3458 Log(("VMX_EXIT_EPT_MISCONFIG for %RGp\n", GCPhys)); 3454 3459 … … 3460 3465 } 3461 3466 3462 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> %Rrc\n", GCPhys, (RTGCPTR)pCtx->rip, rc));3467 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> %Rrc\n", GCPhys, (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc))); 3463 3468 break; 3464 3469 } … … 3468 3473 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF)); 3469 3474 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT; 3470 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);3471 AssertRC(rc );3475 rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls); 3476 AssertRC(rc2); 3472 3477 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow); 3473 3478 goto ResumeExecution; /* we check for pending guest interrupts there */ … … 3493 3498 goto ResumeExecution; 3494 3499 } 3495 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));3500 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc))); 3496 3501 rc = VINF_EM_RAW_EMULATE_INSTR; 3497 3502 break; … … 3543 3548 goto ResumeExecution; 3544 3549 } 3545 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));3550 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, VBOXSTRICTRC_VAL(rc))); 3546 3551 break; 3547 3552 } … … 3559 3564 goto ResumeExecution; 3560 3565 } 3561 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", rc));3566 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc))); 3562 3567 break; 3563 3568 } … … 3574 3579 3575 3580 /* Our patch code uses LSTAR for TPR caching. */ 3576 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);3577 AssertRC(rc );3581 rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff); 3582 AssertRC(rc2); 3578 3583 } 3579 3584 … … 3601 3606 goto ResumeExecution; 3602 3607 } 3603 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));3608 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc))); 3604 3609 break; 3605 3610 } … … 3694 3699 /* Disable drx move intercepts. */ 3695 3700 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; 3696 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);3697 AssertRC(rc );3701 rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls); 3702 AssertRC(rc2); 3698 3703 3699 3704 /* Save the host and load the guest debug state. */ 3700 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);3701 AssertRC(rc );3705 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */); 3706 AssertRC(rc2); 3702 3707 3703 3708 #ifdef LOG_ENABLED … … 3785 3790 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */ 3786 3791 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */ 3787 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);3788 if ( rc == VINF_SUCCESS)3792 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL); 3793 if (RT_SUCCESS(rc)) 3789 3794 { 3790 3795 if (fIOWrite) … … 3881 3886 3882 3887 /* Resync DR7 */ 3883 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);3884 AssertRC(rc );3888 rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]); 3889 AssertRC(rc2); 3885 3890 3886 3891 /* Construct inject info. */ … … 3890 3895 3891 3896 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip)); 3892 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);3893 AssertRC(rc );3897 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0); 3898 AssertRC(rc2); 3894 3899 3895 3900 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1); … … 3911 3916 Assert(fIOWrite); 3912 3917 else 3913 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));3918 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); 3914 3919 #endif 3915 3920 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1); … … 3997 4002 Log(("VMX_EXIT_TASK_SWITCH: reassert trap %d\n", VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hwaccm.s.Event.intInfo))); 3998 4003 Assert(!VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo)); 3999 rc = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hwaccm.s.Event.intInfo), TRPM_HARDWARE_INT);4000 AssertRC(rc );4004 rc2 = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hwaccm.s.Event.intInfo), TRPM_HARDWARE_INT); 4005 AssertRC(rc2); 4001 4006 } 4002 4007 /* else Exceptions and software interrupts can just be restarted. */ … … 4031 4036 goto ResumeExecution; 4032 4037 } 4033 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));4038 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc))); 4034 4039 break; 4035 4040 … … 4071 4076 || rc == VINF_TRPM_XCPT_DISPATCHED 4072 4077 || rc == VINF_EM_RESCHEDULE_REM, 4073 ("rc = %d\n", rc));4078 ("rc = %d\n", VBOXSTRICTRC_VAL(rc))); 4074 4079 break; 4075 4080 … … 4183 4188 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); 4184 4189 Log2(("X")); 4185 return rc;4190 return VBOXSTRICTRC_TODO(rc); 4186 4191 } 4187 4192 … … 4374 4379 * @param pCtx Current CPU context (not updated) 4375 4380 */ 4376 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, intrc, PCPUMCTX pCtx)4381 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx) 4377 4382 { 4378 switch ( rc)4383 switch (VBOXSTRICTRC_VAL(rc)) 4379 4384 { 4380 4385 case VERR_VMX_INVALID_VMXON_PTR: … … 4525 4530 default: 4526 4531 /* impossible */ 4527 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));4532 AssertMsgFailed(("%Rrc (%#x)\n", VBOXSTRICTRC_VAL(rc), VBOXSTRICTRC_VAL(rc))); 4528 4533 break; 4529 4534 }
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