VirtualBox

Changeset 31636 in vbox


Ignore:
Timestamp:
Aug 13, 2010 12:03:15 PM (15 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
64772
Message:

EM: Addressed VBOXSTRICTRC todo from r64673. Decided to only use VBOXSTRICTRC on the methods that would actually return VINF_EM_* stuff.

Location:
trunk
Files:
11 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/em.h

    r30788 r31636  
    132132#define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
    133133
    134 VMMDECL(void)       EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
    135 VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
    136 VMMDECL(int)        EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
    137 VMMDECL(int)        EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
    138                                           PDISCPUSTATE pDISState, unsigned *pcbInstr);
    139 VMMDECL(int)        EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
    140 VMMDECL(int)        EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType);
    141 VMMDECL(int)        EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    142 VMMDECL(int)        EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    143 VMMDECL(int)        EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    144 VMMDECL(int)        EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    145 VMMDECL(int)        EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
    146 VMMDECL(int)        EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    147 VMMDECL(int)        EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    148 VMMDECL(int)        EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    149 VMMDECL(int)        EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
    150 VMMDECL(int)        EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
    151 VMMDECL(int)        EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
    152 VMMDECL(int)        EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
    153 VMMDECL(int)        EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
    154 VMMDECL(int)        EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
     134VMMDECL(void)           EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
     135VMMDECL(RTGCUINTPTR)    EMGetInhibitInterruptsPC(PVMCPU pVCpu);
     136VMMDECL(int)            EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
     137VMMDECL(int)            EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
     138                                              PDISCPUSTATE pDISState, unsigned *pcbInstr);
     139VMMDECL(VBOXSTRICTRC)   EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
     140VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
     141VMMDECL(int)            EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     142VMMDECL(int)            EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     143VMMDECL(int)            EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     144VMMDECL(int)            EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     145VMMDECL(VBOXSTRICTRC)   EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
     146VMMDECL(int)            EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     147VMMDECL(VBOXSTRICTRC)   EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     148VMMDECL(int)            EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     149VMMDECL(int)            EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
     150VMMDECL(int)            EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
     151VMMDECL(int)            EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
     152VMMDECL(int)            EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
     153VMMDECL(int)            EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
     154VMMDECL(int)            EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
    155155VMMDECL(VBOXSTRICTRC)   EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
    156 VMMDECL(int)        EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    157 VMMDECL(int)        EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    158 VMMDECL(bool)       EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
    159 
    160 /**
    161  * Wrap EMInterpretInstructionCPUEx for supervisor code only interpretation.
    162  */
    163 DECLINLINE(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame,
    164                                           RTGCPTR pvFault, uint32_t *pcbSize)
    165 {
    166     return EMInterpretInstructionCPUEx(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMCODETYPE_SUPERVISOR);
    167 }
     156VMMDECL(int)            EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     157VMMDECL(int)            EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     158VMMDECL(bool)           EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
    168159
    169160/** @name Assembly routines

  • trunk/include/VBox/pgm.h

    r31565 r31636  
    284284
    285285
    286 VMMDECL(bool)       PGMIsLocked(PVM pVM);
    287 VMMDECL(bool)       PGMIsLockOwner(PVM pVM);
    288 
    289 VMMDECL(int)        PGMRegisterStringFormatTypes(void);
    290 VMMDECL(void)       PGMDeregisterStringFormatTypes(void);
    291 VMMDECL(RTHCPHYS)   PGMGetHyperCR3(PVMCPU pVCpu);
    292 VMMDECL(RTHCPHYS)   PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
    293 VMMDECL(RTHCPHYS)   PGMGetInterHCCR3(PVM pVM);
    294 VMMDECL(RTHCPHYS)   PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
    295 VMMDECL(RTHCPHYS)   PGMGetInter32BitCR3(PVM pVM);
    296 VMMDECL(RTHCPHYS)   PGMGetInterPaeCR3(PVM pVM);
    297 VMMDECL(RTHCPHYS)   PGMGetInterAmd64CR3(PVM pVM);
    298 VMMDECL(int)        PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
    299 VMMDECL(int)        PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
    300 VMMDECL(int)        PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
    301 VMMDECL(int)        PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
    302 VMMDECL(int)        PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
    303 VMMDECL(int)        PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
    304 VMMDECL(int)        PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
    305 VMMDECL(int)        PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
     286VMMDECL(bool)           PGMIsLocked(PVM pVM);
     287VMMDECL(bool)           PGMIsLockOwner(PVM pVM);
     288
     289VMMDECL(int)            PGMRegisterStringFormatTypes(void);
     290VMMDECL(void)           PGMDeregisterStringFormatTypes(void);
     291VMMDECL(RTHCPHYS)       PGMGetHyperCR3(PVMCPU pVCpu);
     292VMMDECL(RTHCPHYS)       PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
     293VMMDECL(RTHCPHYS)       PGMGetInterHCCR3(PVM pVM);
     294VMMDECL(RTHCPHYS)       PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
     295VMMDECL(RTHCPHYS)       PGMGetInter32BitCR3(PVM pVM);
     296VMMDECL(RTHCPHYS)       PGMGetInterPaeCR3(PVM pVM);
     297VMMDECL(RTHCPHYS)       PGMGetInterAmd64CR3(PVM pVM);
     298VMMDECL(int)            PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     299VMMDECL(int)            PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
     300VMMDECL(int)            PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
     301VMMDECL(int)            PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
     302VMMDECL(VBOXSTRICTRC)   PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     303VMMDECL(int)            PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
     304VMMDECL(int)            PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
     305VMMDECL(int)            PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    306306#ifndef IN_RING0
    307 VMMDECL(bool)       PGMMapHasConflicts(PVM pVM);
     307VMMDECL(bool)           PGMMapHasConflicts(PVM pVM);
    308308#endif
    309309#ifdef VBOX_STRICT
    310 VMMDECL(void)       PGMMapCheck(PVM pVM);
     310VMMDECL(void)           PGMMapCheck(PVM pVM);
    311311#endif
    312 VMMDECL(int)        PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
    313 VMMDECL(int)        PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
    314 VMMDECL(int)        PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
    315 VMMDECL(int)        PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
     312VMMDECL(int)            PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
     313VMMDECL(int)            PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
     314VMMDECL(int)            PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
     315VMMDECL(int)            PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
    316316/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
    317317 *        PGMShwMakePageNotPresent

  • trunk/src/VBox/VMM/EMRaw.cpp

    r30263 r31636  
    690690
    691691                uint32_t opsize;
    692                 rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
     692                rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &opsize));
    693693                if (RT_SUCCESS(rc))
    694694                {
    … …  
    11841184#endif
    11851185
    1186                     rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
     1186                    rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &size));
    11871187                    if (RT_SUCCESS(rc))
    11881188                    {

  • trunk/src/VBox/VMM/PATM/VMMGC/PATMGC.cpp

    r31402 r31636  
    522522            }
    523523
    524             rc = EMInterpretInstructionCPU(pVM, VMMGetCpu0(pVM), &cpu, pRegFrame, 0 /* not relevant here */, &size);
     524            rc = EMInterpretInstructionCPU(pVM, VMMGetCpu0(pVM), &cpu, pRegFrame, 0 /* not relevant here */,
     525                                           EMCODETYPE_SUPERVISOR, &size);
    525526            if (rc != VINF_SUCCESS)
    526527            {

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r31569 r31636  
    7575*   Internal Functions                                                         *
    7676*******************************************************************************/
    77 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType = EMCODETYPE_SUPERVISOR);
     77DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
     78                                                   RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
    7879
    7980
    … …  
    311312 *          to worry about e.g. invalid modrm combinations (!)
    312313 */
    313 VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     314VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    314315{
    315316    RTGCPTR pbCode;
    316317
    317318    LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    318     int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
     319    VBOXSTRICTRC rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
    319320    if (RT_SUCCESS(rc))
    320321    {
    … …  
    326327        {
    327328            Assert(cbOp == pDis->opsize);
    328             rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize);
     329            rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbSize);
    329330            if (RT_SUCCESS(rc))
    330331                pRegFrame->rip += cbOp; /* Move on to the next instruction. */
    … …  
    342343 * EIP is *NOT* updated!
    343344 *
    344  * @returns VBox status code.
     345 * @returns VBox strict status code.
    345346 * @retval  VINF_*                  Scheduling instructions. When these are returned, it
    346347 *                                  starts to get a bit tricky to know whether code was
    … …  
    365366 *          Make sure this can't happen!! (will add some assertions/checks later)
    366367 */
    367 VMMDECL(int) EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType)
     368VMMDECL(VBOXSTRICTRC) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
     369                                                RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
    368370{
    369371    STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
    370     int rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, enmCodeType);
     372    VBOXSTRICTRC rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
    371373    STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
    372374    if (RT_SUCCESS(rc))
    … …  
    17651767 *
    17661768 */
    1767 VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
    1768 {
    1769     int rc;
    1770 
     1769VMMDECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
     1770{
    17711771    /** @todo is addr always a flat linear address or ds based
    17721772     * (in absence of segment override prefixes)????
    … …  
    17751775    LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
    17761776#endif
    1777     rc = PGMInvalidatePage(pVCpu, pAddrGC);
     1777    VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
    17781778    if (    rc == VINF_SUCCESS
    17791779        ||  rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
    17801780        return VINF_SUCCESS;
    17811781    AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
    1782                     ("%Rrc addr=%RGv\n", rc, pAddrGC),
     1782                    ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
    17831783                    VERR_EM_INTERPRETER);
    17841784    return rc;
    … …  
    17891789 * INVLPG Emulation.
    17901790 */
    1791 static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1791static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    17921792{
    17931793    OP_PARAMVAL param1;
    17941794    RTGCPTR     addr;
    17951795
    1796     int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
     1796    VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    17971797    if(RT_FAILURE(rc))
    17981798        return VERR_EM_INTERPRETER;
    … …  
    18221822        return VINF_SUCCESS;
    18231823    AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
    1824                     ("%Rrc addr=%RGv\n", rc, addr),
     1824                    ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
    18251825                    VERR_EM_INTERPRETER);
    18261826    return rc;
    … …  
    24262426 * HLT Emulation.
    24272427 */
    2428 static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2428static VBOXSTRICTRC
     2429emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    24292430{
    24302431    return VINF_EM_HALT;
    … …  
    25732574 * MWAIT Emulation.
    25742575 */
    2575 VMMDECL(int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     2576VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    25762577{
    25772578    uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
    … …  
    26172618}
    26182619
    2619 static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2620static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    26202621{
    26212622    return EMInterpretMWait(pVM, pVCpu, pRegFrame);
    … …  
    28022803 * @copydoc EMInterpretInstructionCPU
    28032804 */
    2804 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
    2805                                           uint32_t *pcbSize, EMCODETYPE enmCodeType)
     2805DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
     2806                                                   RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
    28062807{
    28072808    Assert(enmCodeType == EMCODETYPE_SUPERVISOR || enmCodeType == EMCODETYPE_ALL);
    … …  
    29422943#endif
    29432944
    2944     int rc;
     2945    VBOXSTRICTRC rc;
    29452946#if (defined(VBOX_STRICT) || defined(LOG_ENABLED))
    29462947    LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r31565 r31636  
    694694 * Emulation of the invlpg instruction (HC only actually).
    695695 *
    696  * @returns VBox status code, special care required.
     696 * @returns Strict VBox status code, special care required.
    697697 * @retval  VINF_PGM_SYNC_CR3 - handled.
    698698 * @retval  VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
    … …  
    706706 *
    707707 * @todo    Flush page or page directory only if necessary!
     708 * @todo    VBOXSTRICTRC
    708709 */
    709710VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
    … …  
    797798 * @param   pvFault     Fault address.
    798799 */
    799 VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
     800VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    800801{
    801802    uint32_t cb;
    802     int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
     803    VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
    803804    if (rc == VERR_EM_INTERPRETER)
    804805        rc = VINF_EM_RAW_EMULATE_INSTR;
    805806    if (rc != VINF_SUCCESS)
    806         Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
     807        Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
    807808    return rc;
    808809}

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r31612 r31636  
    385385     *        It's writing to an unhandled part of the LDT page several million times.
    386386     */
    387     rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
     387    rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
    388388    LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
    389389    STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
    … …  
    799799               our shadow page tables. (Required for e.g. Solaris guests; soft
    800800               ecc, random nr generator.) */
    801             rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
     801            rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
    802802            LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
    803803            STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
    … …  
    946946            {
    947947                Assert((uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_P)) == (X86_TRAP_PF_RW | X86_TRAP_PF_P));
    948                 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
     948                rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
    949949                if (RT_SUCCESS(rc))
    950950                    STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r31593 r31636  
    120120 * @param   pPool       The pool.
    121121 * @param   pPage       A page in the chain.
     122 * @todo VBOXSTRICTRC
    122123 */
    123124int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
    … …  
    852853 * @param   GCPhysFault The fault address as guest physical address.
    853854 * @param   pvFault     The fault address.
     855 * @todo VBOXSTRICTRC
    854856 */
    855857static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
    … …  
    862864
    863865    /*
    864      * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
     866     * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
     867     * Must do this in raw mode (!); XP boot will fail otherwise.
    865868     */
    866869    uint32_t cbWritten;
    867     int rc2 = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten, EMCODETYPE_ALL);
     870    VBOXSTRICTRC rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cbWritten);
    868871    if (RT_SUCCESS(rc2))
     872    {
    869873        pRegFrame->rip += pDis->opsize;
     874        AssertMsg(rc2 == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
     875    }
    870876    else if (rc2 == VERR_EM_INTERPRETER)
    871877    {
    … …  
    886892    }
    887893    else
    888         rc = rc2;
     894        rc = VBOXSTRICTRC_VAL(rc2);
    889895
    890896    LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
    … …  
    10021008     */
    10031009    uint32_t cb;
    1004     int rc = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb, EMCODETYPE_ALL);
     1010    VBOXSTRICTRC rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cb);
    10051011    if (RT_SUCCESS(rc))
     1012    {
    10061013        pRegFrame->rip += pDis->opsize;
     1014        AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
     1015    }
    10071016    else if (rc == VERR_EM_INTERPRETER)
    10081017    {
    … …  
    10431052#endif
    10441053
    1045     LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
    1046     return rc;
     1054    LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", VBOXSTRICTRC_VAL(rc), cb));
     1055    return VBOXSTRICTRC_VAL(rc);
    10471056}
    10481057

  • trunk/src/VBox/VMM/VMMGC/TRPMGCHandlers.cpp

    r31402 r31636  
    549549            LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
    550550            uint32_t cbIgnored;
    551             rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, &cbIgnored);
     551            rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
    552552            if (RT_SUCCESS(rc))
    553553                pRegFrame->eip += Cpu.opsize;
    … …  
    794794        {
    795795            uint32_t cbIgnored;
    796             rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
     796            rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
    797797            if (RT_SUCCESS(rc))
    798798                pRegFrame->eip += pCpu->opsize;
    … …  
    873873        {
    874874            uint32_t cbIgnored;
    875             rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, &cbIgnored);
     875            rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, PC, EMCODETYPE_SUPERVISOR, &cbIgnored);
    876876            if (RT_SUCCESS(rc))
    877877                pRegFrame->eip += pCpu->opsize;

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r31569 r31636  
    32903290
    32913291                    default:
    3292                         rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
     3292                        rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &cbSize);
    32933293                        break;
    32943294                    }

  • trunk/src/recompiler/VBoxREMWrapper.cpp

    r31161 r31636  
    518518};
    519519
    520 /* EMInterpretInstructionCPUEx args */
    521 static const REMPARMDESC g_aArgsEMInterpretInstructionCPUEx[] =
     520/* EMInterpretInstructionCPU args */
     521static const REMPARMDESC g_aArgsEMInterpretInstructionCPU[] =
    522522{
    523523    { REMPARMDESC_FLAGS_INT,        sizeof(PVM),                NULL },
    … …  
    526526    { REMPARMDESC_FLAGS_INT,        sizeof(PCPUMCTXCORE),       NULL },
    527527    { REMPARMDESC_FLAGS_GCPTR,      sizeof(RTGCPTR),            NULL },
    528     { REMPARMDESC_FLAGS_INT,        sizeof(uint32_t *),         NULL },
    529     { REMPARMDESC_FLAGS_INT,        sizeof(EMCODETYPE),         NULL }
     528    { REMPARMDESC_FLAGS_INT,        sizeof(EMCODETYPE),         NULL },
     529    { REMPARMDESC_FLAGS_INT,        sizeof(uint32_t *),         NULL }
    530530};
    531531
    … …  
    12921292    { "VMR3GetVMCPUId",                         VMM_FN(VMR3GetVMCPUId),                 &g_aArgsVM[0],                              RT_ELEMENTS(g_aArgsVM),                                REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
    12931293    { "VMR3GetVMCPUNativeThread",               VMM_FN(VMR3GetVMCPUNativeThread),       &g_aArgsVM[0],                              RT_ELEMENTS(g_aArgsVM),                                REMFNDESC_FLAGS_RET_INT,    sizeof(void *),     NULL },
    1294     { "EMInterpretInstructionCPUEx",            VMM_FN(EMInterpretInstructionCPUEx),    &g_aArgsEMInterpretInstructionCPUEx[0],     RT_ELEMENTS(g_aArgsEMInterpretInstructionCPUEx),       REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
     1294    { "EMInterpretInstructionCPU",              VMM_FN(EMInterpretInstructionCPU),      &g_aArgsEMInterpretInstructionCPU[0],       RT_ELEMENTS(g_aArgsEMInterpretInstructionCPU),       REMFNDESC_FLAGS_RET_INT,    sizeof(int),        NULL },
    12951295//    { "",                        VMM_FN(),                &g_aArgsVM[0],                              RT_ELEMENTS(g_aArgsVM),                                REMFNDESC_FLAGS_RET_INT,    sizeof(int),   NULL },
    12961296};
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