Changeset 31996 in vbox for trunk

Timestamp:

Aug 26, 2010 1:32:30 PM (14 years ago)

Author:

vboxsync

Message:

Mostly safe X86_PTE_PAE_PG_MASK -> X86_PTE_PAE_PG_MASK_FULL conversions.

Location:

trunk/src/VBox

Files:

• Debugger/DBGCEmulateCodeView.cpp (modified) (3 diffs)
• VMM/MM.cpp (modified) (1 diff)
• VMM/PGMDbg.cpp (modified) (3 diffs)
• VMM/PGMGstDefs.h (modified) (3 diffs)
• VMM/PGMInline.h (modified) (2 diffs)
• VMM/PGMPool.cpp (modified) (2 diffs)
• VMM/VMMAll/PGMAll.cpp (modified) (2 diffs)
• VMM/VMMAll/PGMAllBth.h (modified) (2 diffs)
• VMM/VMMAll/PGMAllGst.h (modified) (1 diff)
• VMM/VMMAll/PGMAllHandler.cpp (modified) (11 diffs)
• VMM/VMMAll/PGMAllMap.cpp (modified) (1 diff)
• VMM/VMMAll/PGMAllPhys.cpp (modified) (1 diff)
• VMM/VMMAll/PGMAllPool.cpp (modified) (8 diffs)
• VMM/VMMGC/PGMGCGst.h (modified) (1 diff)
• VMM/testcase/tstCompiler.cpp (modified) (2 diffs)

trunk/src/VBox/Debugger/DBGCEmulateCodeView.cpp

@@ -2722 +2722 @@
             /* Page Map Level 4 Lookup. */
             /* Check if it's a valid address first? */
-            VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK;
+            VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK_FULL;
             VarCur.u.u64Number += (((uint64_t)VarGCPtr.u.GCFlat >> X86_PML4_SHIFT) & X86_PML4_MASK) * sizeof(X86PML4E);
             X86PML4E Pml4e;
@@ -3093 +3093 @@
             /* Page Map Level 4 Lookup. */
             /* Check if it's a valid address first? */
-            VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK;
+            VarCur.u.u64Number &= X86_PTE_PAE_PG_MASK_FULL;
             VarCur.u.u64Number += (((uint64_t)VarGCPtr.u.GCFlat >> X86_PML4_SHIFT) & X86_PML4_MASK) * sizeof(X86PML4E);
             X86PML4E Pml4e;
@@ -3189 +3189 @@
                          :   "%08llx 4kb phys=%08llx %s %s %s %s %s avl=%02x %s %s %s %s %s",
                          Pte.u,
-                         Pte.u & X86_PTE_PAE_PG_MASK,
+                         Pte.u & X86_PTE_PAE_PG_MASK_FULL,
                          Pte.n.u1Present         ? "p " : "np",
                          Pte.n.u1Write           ? "w" : "r",

trunk/src/VBox/VMM/MM.cpp

@@ -319 +319 @@
     else
         AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc), rc);
-    AssertLogRelMsg(!(cbRam & ~X86_PTE_PAE_PG_MASK), ("%RGp X86_PTE_PAE_PG_MASK=%RX64\n", cbRam, X86_PTE_PAE_PG_MASK));
+    AssertLogRelMsg(!(cbRam & ~X86_PTE_PAE_PG_MASK_FULL), ("%RGp X86_PTE_PAE_PG_MASK_FULL=%RX64\n", cbRam, X86_PTE_PAE_PG_MASK_FULL));
     AssertLogRelMsgReturn(cbRam <= GMM_GCPHYS_LAST, ("cbRam=%RGp GMM_GCPHYS_LAST=%RX64\n", cbRam, GMM_GCPHYS_LAST), VERR_OUT_OF_RANGE);
-    cbRam &= X86_PTE_PAE_PG_MASK;
+    cbRam &= X86_PTE_PAE_PG_MASK_FULL;
     pVM->mm.s.cbRamBase = cbRam;
 

trunk/src/VBox/VMM/PGMDbg.cpp

@@ -156 +156 @@
         return VERR_INVALID_POINTER;
     unsigned off = HCPhys & PAGE_OFFSET_MASK;
-    HCPhys &= X86_PTE_PAE_PG_MASK;
+    HCPhys &= X86_PTE_PAE_PG_MASK_FULL;
     if (HCPhys == 0)
         return VERR_INVALID_POINTER;
@@ -1104 +1104 @@
                                         Pte.u & RT_BIT(10)                ? '1' : '0',
                                         Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
-                                        Pte.u & X86_PTE_PAE_PG_MASK);
+                                        Pte.u & X86_PTE_PAE_PG_MASK_FULL);
                 if (pState->fDumpPageInfo)
-                    pgmR3DumpHierarchyShwGuestPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK, _4K);
+                    pgmR3DumpHierarchyShwGuestPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK_FULL, _4K);
                 if ((Pte.u >> 52) & 0x7ff)
                     pState->pHlp->pfnPrintf(pState->pHlp, " 62:52=%03llx%s", (Pte.u >> 52) & 0x7ff, pState->fLme ? "" : "!");
@@ -1785 +1785 @@
                                     Pte.u & RT_BIT(10)  ? '1' : '0',
                                     Pte.u & RT_BIT(11)  ? '1' : '0',
-                                    Pte.u & X86_PTE_PAE_PG_MASK);
+                                    Pte.u & X86_PTE_PAE_PG_MASK_FULL);
             if (pState->fDumpPageInfo)
-                pgmR3DumpHierarchyGstPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK, _4K);
+                pgmR3DumpHierarchyGstPageInfo(pState, Pte.u & X86_PTE_PAE_PG_MASK_FULL, _4K);
             pgmR3DumpHierarchyGstCheckReservedHighBits(pState, Pte.u);
             pState->pHlp->pfnPrintf(pState->pHlp, "\n");

trunk/src/VBox/VMM/PGMGstDefs.h

@@ -75 +75 @@
 #  define GSTPDE                                X86PDEPAE
 #  define PGSTPDE                               PX86PDEPAE
-#  define GST_PTE_PG_MASK                       X86_PTE_PAE_PG_MASK
+#  define GST_PTE_PG_MASK                       X86_PTE_PAE_PG_MASK_FULL
 #  define GST_IS_NX_ACTIVE(pVCpu)               (true && This_should_perhaps_not_be_used_in_this_context)
 #  define BTH_IS_NP_ACTIVE(pVM)                 (true)
@@ -98 +98 @@
 #   define GSTPDE                               X86PDEPAE
 #   define PGSTPDE                              PX86PDEPAE
-#   define GST_PTE_PG_MASK                      X86_PTE_PAE_PG_MASK
+#   define GST_PTE_PG_MASK                      X86_PTE_PAE_PG_MASK_FULL
 #  endif
 #  define GST_IS_NX_ACTIVE(pVCpu)               (pgmGstIsNoExecuteActive(pVCpu))
@@ -197 +197 @@
 #  define GST_PDPT_SHIFT                        X86_PDPT_SHIFT
 #  define GST_PDPT_MASK                         X86_PDPT_MASK_PAE
-#  define GST_PTE_PG_MASK                       X86_PTE_PAE_PG_MASK
+#  define GST_PTE_PG_MASK                       X86_PTE_PAE_PG_MASK_FULL
 #  define GST_CR3_PAGE_MASK                     X86_CR3_PAE_PAGE_MASK
 #  define GST_IS_PTE_VALID(pVCpu, Pte)          (!( (Pte).u   & (pVCpu)->pgm.s.fGstPaeMbzPteMask ))

trunk/src/VBox/VMM/PGMInline.h

@@ -521 +521 @@
     int rc;
     PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
-    if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
+    if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK_FULL))
     {
         STAM_COUNTER_INC(&pPGM->CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbHits));
@@ -551 +551 @@
     int rc;
     PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
-    if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
+    if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK_FULL))
     {
         STAM_COUNTER_INC(&pPGM->CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbHits));

trunk/src/VBox/VMM/PGMPool.cpp

@@ -824 +824 @@
  *
  * Remark: assumes the caller will flush all TLBs (!!)
- */     
+ */
 void pgmR3PoolWriteProtectPages(PVM pVM)
 {
@@ -931 +931 @@
                     {
                         RTHCPHYS HCPhys = NIL_RTHCPHYS;
-                        rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK, &HCPhys);
+                        rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[j].u & X86_PTE_PAE_PG_MASK_FULL, &HCPhys);
                         if (   rc != VINF_SUCCESS
                             || PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[j]) != HCPhys)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -854 +854 @@
 DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
 {
-    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
+    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK_FULL), ("fFlags=%#llx\n", fFlags));
     Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
 
@@ -1409 +1409 @@
      * Validate input.
      */
-    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
+    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK_FULL), ("fFlags=%#llx\n", fFlags));
     Assert(cb);
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -353 +353 @@
                      || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
             {
-                Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
+                Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK_FULL) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK_FULL));
 #   ifdef IN_RC
                 STAM_PROFILE_START(&pCur->Stat, h);
@@ -4205 +4205 @@
                                 continue;
 
-                            fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
+                            fIgnoreFlags = X86_PTE_PAE_PG_MASK_FULL | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
 
                             /* match the physical addresses */

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -353 +353 @@
             {
                 GSTPTE Pte = Walk.pPt->a[iPTE];
-                Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
+                Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK_FULL))
                       | (fFlags & ~GST_PTE_PG_MASK);
                 Walk.pPt->a[iPTE] = Pte;

trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp

@@ -145 +145 @@
     pNew->Core.KeyLast  = GCPhysLast;
     pNew->enmType       = enmType;
-    pNew->cPages        = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
+    pNew->cPages        = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK_FULL) + PAGE_SIZE) >> PAGE_SHIFT;
     pNew->pfnHandlerR3  = pfnHandlerR3;
     pNew->pvUserR3      = pvUserR3;
@@ -307 +307 @@
                 &&  PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE)
             {
-                RTGCPHYS GCPhys = (GCPhysStart + (PAGE_SIZE - 1)) & X86_PTE_PAE_PG_MASK;
+                RTGCPHYS GCPhys = (GCPhysStart + (PAGE_SIZE - 1)) & X86_PTE_PAE_PG_MASK_FULL;
                 if (    GCPhys > GCPhysLast
                     ||  GCPhys < GCPhysStart)
@@ -314 +314 @@
             }
             else
-                GCPhysStart &= X86_PTE_PAE_PG_MASK;
+                GCPhysStart &= X86_PTE_PAE_PG_MASK_FULL;
             Assert(!pPage || PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO); /* these are page aligned atm! */
         }
@@ -324 +324 @@
                 &&  PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE)
             {
-                RTGCPHYS GCPhys = (GCPhysLast & X86_PTE_PAE_PG_MASK) - 1;
+                RTGCPHYS GCPhys = (GCPhysLast & X86_PTE_PAE_PG_MASK_FULL) - 1;
                 if (    GCPhys < GCPhysStart
                     ||  GCPhys > GCPhysLast)
@@ -536 +536 @@
                 pCur->Core.Key      = GCPhys;
                 pCur->Core.KeyLast  = GCPhysLast;
-                pCur->cPages        = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK) + 1) >> PAGE_SHIFT;
+                pCur->cPages        = (GCPhysLast - (GCPhys & X86_PTE_PAE_PG_MASK_FULL) + 1) >> PAGE_SHIFT;
 
                 if (RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pCur->Core))
@@ -684 +684 @@
             *pNew = *pCur;
             pNew->Core.Key      = GCPhysSplit;
-            pNew->cPages        = (pNew->Core.KeyLast - (pNew->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
+            pNew->cPages        = (pNew->Core.KeyLast - (pNew->Core.Key & X86_PTE_PAE_PG_MASK_FULL) + PAGE_SIZE) >> PAGE_SHIFT;
 
             pCur->Core.KeyLast  = GCPhysSplit - 1;
-            pCur->cPages        = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
+            pCur->cPages        = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK_FULL) + PAGE_SIZE) >> PAGE_SHIFT;
 
             if (RT_LIKELY(RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core)))
@@ -750 +750 @@
                     {
                         pCur1->Core.KeyLast  = pCur2->Core.KeyLast;
-                        pCur1->cPages        = (pCur1->Core.KeyLast - (pCur1->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
+                        pCur1->cPages        = (pCur1->Core.KeyLast - (pCur1->Core.Key & X86_PTE_PAE_PG_MASK_FULL) + PAGE_SIZE) >> PAGE_SHIFT;
                         LogFlow(("PGMHandlerPhysicalJoin: %RGp-%RGp %RGp-%RGp\n",
                                  pCur1->Core.Key, pCur1->Core.KeyLast, pCur2->Core.Key, pCur2->Core.KeyLast));
@@ -1481 +1481 @@
     for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
     {
-        if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == pState->GCPhys)
+        if ((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK_FULL) == pState->GCPhys)
         {
             unsigned uState = pgmHandlerVirtualCalcState(pCur);
@@ -1574 +1574 @@
 
             AssertRCReturn(rc, 0);
-            if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst)
+            if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK_FULL) != GCPhysGst)
             {
                 AssertMsgFailed(("virt handler phys out of sync. %RGp GCPhysGst=%RGp iPage=%#x %RGv %s\n",
@@ -1713 +1713 @@
                                                                                                         GCPhysKey, true /* above-or-equal */);
                         if (    !pPhys2Virt
-                            ||  (pPhys2Virt->Core.Key & X86_PTE_PAE_PG_MASK) != State.GCPhys)
+                            ||  (pPhys2Virt->Core.Key & X86_PTE_PAE_PG_MASK_FULL) != State.GCPhys)
                             break;
 
@@ -1732 +1732 @@
 
                         /* done? */
-                        if ((GCPhysKey & X86_PTE_PAE_PG_MASK) != State.GCPhys)
+                        if ((GCPhysKey & X86_PTE_PAE_PG_MASK_FULL) != State.GCPhys)
                             break;
                     }

trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

@@ -144 +144 @@
      * Validate input.
      */
-    AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
+    AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK_FULL | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
     Assert(cb);
 

trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

@@ -1078 +1078 @@
     if (    PGM_PAGE_GET_TYPE(pPage) < PGMPAGETYPE_ROM_SHADOW
         ||  PGM_PAGE_GET_TYPE(pPage) > PGMPAGETYPE_ROM)
-        pTlbe->GCPhys = GCPhys & X86_PTE_PAE_PG_MASK;
+        pTlbe->GCPhys = GCPhys & X86_PTE_PAE_PG_MASK_FULL;
     else
         pTlbe->GCPhys = NIL_RTGCPHYS; /* ROM: Problematic because of the two pages. :-/ */

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -326 +326 @@
                     AssertRC(rc);
 
-                    Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
+                    Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK_FULL));
                     pgmPoolTracDerefGCPhysHint(pPool, pPage,
                                                PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
-                                               GstPte.u & X86_PTE_PAE_PG_MASK,
+                                               GstPte.u & X86_PTE_PAE_PG_MASK_FULL,
                                                iShw);
                     PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
@@ -350 +350 @@
 #   endif
                         AssertRC(rc);
-                        Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
+                        Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK_FULL));
                         pgmPoolTracDerefGCPhysHint(pPool, pPage,
                                                    PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
-                                                   GstPte.u & X86_PTE_PAE_PG_MASK,
+                                                   GstPte.u & X86_PTE_PAE_PG_MASK_FULL,
                                                    iShw2);
                         PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
@@ -1014 +1014 @@
             {
                 RTHCPHYS HCPhys = -1;
-                int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
+                int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK_FULL, &HCPhys);
                 if (rc != VINF_SUCCESS)
                 {
@@ -1366 +1366 @@
         {
             RTHCPHYS HCPhys = NIL_RTHCPHYS;
-            int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
+            int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL, &HCPhys);
             if (    rc != VINF_SUCCESS
                 ||  PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
@@ -1438 +1438 @@
             &&  pGstPT->a[i].n.u1Present)
         {
-            if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
+            if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL))
             {
                 *pfFlush = true;
@@ -1447 +1447 @@
         {
             /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
-            if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
+            if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL))
             {
 #ifdef VBOX_STRICT
                 RTHCPHYS HCPhys = NIL_RTGCPHYS;
-                int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
+                int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL, &HCPhys);
                 AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
 #endif
@@ -1466 +1466 @@
             /* Something was changed, so flush it. */
             Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
-                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL, i);
             PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
         }
@@ -4146 +4146 @@
         {
             Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
-                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
-            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
+                  i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL));
+            pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK_FULL, i);
             if (!pPage->cPresent)
                 break;

trunk/src/VBox/VMM/VMMGC/PGMGCGst.h

@@ -70 +70 @@
 # define GST_PD_SHIFT               X86_PD_PAE_SHIFT
 # define GST_PD_MASK                X86_PD_PAE_MASK
-# define GST_PTE_PG_MASK            X86_PTE_PAE_PG_MASK
+# define GST_PTE_PG_MASK            X86_PTE_PAE_PG_MASK_FULL
 # define GST_PT_SHIFT               X86_PT_PAE_SHIFT
 # define GST_PT_MASK                X86_PT_PAE_MASK

trunk/src/VBox/VMM/testcase/tstCompiler.cpp

@@ -174 +174 @@
 void Mix6432Consts(PX86PTEPAE64 pPteDst, PX86PTEPAE64 pPteSrc)
 {
-    pPteDst->u = pPteSrc->u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
+    pPteDst->u = pPteSrc->u & ~(X86_PTE_PAE_PG_MASK_FULL | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
 }
 
@@ -180 +180 @@
 void Mix32Var64Const64Data(PX86PTEPAE64 pPteDst, uint32_t fMask, uint32_t fFlags)
 {
-    pPteDst->u = (pPteDst->u & (fMask | X86_PTE_PAE_PG_MASK)) | (fFlags & ~X86_PTE_PAE_PG_MASK);
+    pPteDst->u = (pPteDst->u & (fMask | X86_PTE_PAE_PG_MASK_FULL)) | (fFlags & ~X86_PTE_PAE_PG_MASK_FULL);
 }