Changeset 31997 in vbox

Timestamp:

Aug 26, 2010 1:59:06 PM (14 years ago)

Author:

vboxsync

Message:

PGM: Don't shadow any extra bits in long mode PDPEs and PML4Es.

Location:

trunk/src/VBox/VMM

Files:

• PGM.cpp (modified) (1 diff)
• PGMInternal.h (modified) (1 diff)
• VMMAll/PGMAll.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/PGM.cpp

@@ -2118 +2118 @@
         pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
             X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_G | X86_PDE4M_A | X86_PDE4M_D;
+        pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask  = X86_PDPE_P  | X86_PDPE_RW  | X86_PDPE_US  | X86_PDPE_A;
+        pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
     }
 

trunk/src/VBox/VMM/PGMInternal.h

@@ -3593 +3593 @@
     /** Mask containing the MBZ PML4E bits. */
     uint64_t                        fGstAmd64MbzPml4eMask;
+    /** Mask containing the PDPE bits that we shadow. */
+    uint64_t                        fGstAmd64ShadowedPdpeMask;
+    /** Mask containing the PML4E bits that we shadow. */
+    uint64_t                        fGstAmd64ShadowedPml4eMask;
     /** @} */
 

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -1055 +1055 @@
  * @param   pVCpu       VMCPU handle.
  * @param   GCPtr       The address.
- * @param   uGstPml4e   Guest PML4 entry
- * @param   uGstPdpe    Guest PDPT entry
+ * @param   uGstPml4e   Guest PML4 entry (valid).
+ * @param   uGstPdpe    Guest PDPT entry (valid).
  * @param   ppPD        Receives address of page directory
  */
@@ -1105 +1105 @@
     }
     /* The PDPT was cached or created; hook it up now. */
-    pPml4e->u |= pShwPage->Core.Key
-              | (uGstPml4e & ~(X86_PML4E_PG_MASK_FULL | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
+    pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
 
     const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
@@ -1143 +1142 @@
     }
     /* The PD was cached or created; hook it up now. */
-    pPdpe->u |= pShwPage->Core.Key
-             | (uGstPdpe & ~(X86_PDPE_PG_MASK_FULL | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
+    pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
 
     *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
@@ -1191 +1189 @@
 
     *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
-Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
+    Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
     return VINF_SUCCESS;
 }
@@ -2242 +2240 @@
         pVCpu->pgm.s.fGst64ShadowedBigPdeMask     |= X86_PDE2M_PAE_NX;
         pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
+        pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask    |= X86_PDPE_LM_NX;
+        pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask   |= X86_PML4E_NX;
     }
     else
@@ -2261 +2261 @@
         pVCpu->pgm.s.fGst64ShadowedBigPdeMask     &= ~X86_PDE2M_PAE_NX;
         pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
+        pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask    &= ~X86_PDPE_LM_NX;
+        pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask   &= ~X86_PML4E_NX;
     }
 }