VirtualBox

Changeset 32765 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Sep 24, 2010 4:26:32 PM (14 years ago)
Author:
vboxsync
Message:

PCI: Linux guests really access extended PCI space

Location:
trunk/src/VBox
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp

    r32735 r32765  
    16741674    PCIDevSetSubSystemId        (&pThis->dev, 0x0000); /* 2e ro. */
    16751675    PCIDevSetInterruptLine      (&pThis->dev, 0x00);   /* 3c rw. */
    1676     PCIDevSetInterruptPin       (&pThis->dev, 0x01);   /* 3d ro - INTA#. */             Assert (pThis->dev.config[0x3d] == 0x01);
    1677     PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
     1676    PCIDevSetInterruptPin       (&pThis->dev, 0x01);   /* 3d ro - INTA#. */
     1677
     1678//#define HDA_AS_PCI_EXPRESS
     1679
     1680#ifdef HDA_AS_PCI_EXPRESS
     1681    PCIDevSetCapabilityList     (&pThis->dev, 0x80);
     1682#else
     1683    PCIDevSetCapabilityList     (&pThis->dev, 0x50);   /* ICH6 datasheet 18.1.16 */
     1684#endif
    16781685
    16791686    //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
    16801687    // of these values needs to be properly documented!
    16811688    /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
    1682     pThis->dev.config[0x40] = 0x01;
    1683 
    1684     pThis->dev.config[0x50] = VBOX_PCI_CAP_ID_PM;
    1685     pThis->dev.config[0x51] = 0x00; /* next */
    1686     pThis->dev.config[0x52] = VBOX_PCI_PM_CAP_DSI | 0x02;
    1687     pThis->dev.config[0x53] = 0x00; /* PM - disabled,  */
    1688 
    1689 #if 0
    1690     pThis->dev.config[0x60] = VBOX_PCI_CAP_ID_MSI;
    1691     pThis->dev.config[0x61] = 0x70; /* next */
    1692     pThis->dev.config[0x62] = 0x00;
    1693     pThis->dev.config[0x63] = VBOX_PCI_MSIX_FLAGS_ENABLE >> 8;
     1689    PCIDevSetByte(&pThis->dev, 0x40, 0x01);
     1690
     1691    /* Power Management */
     1692    PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
     1693    PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
     1694    PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
     1695
     1696#ifdef HDA_AS_PCI_EXPRESS
     1697    /* Message Signalled Interrupts, up to 28 bytes */
     1698    PCIDevSetByte(&pThis->dev,  0x60 + 0, VBOX_PCI_CAP_ID_MSI);
     1699    PCIDevSetByte(&pThis->dev,  0x60 + 1, 0x50); /* next */
     1700    PCIDevSetWord(&pThis->dev,  0x60 + 2, 0 ? VBOX_PCI_MSIX_FLAGS_ENABLE : 0);
     1701    /* Physical address of MSI, could be 64-bit if VBOX_PCI_MSI_FLAGS_64BIT */
     1702    PCIDevSetDWord(&pThis->dev, 0x60 + 4, 0 ? 0x00000001 : 0);
    16941703#endif
    16951704
    1696 #if 0
    1697     pThis->dev.config[0x90] = VBOX_PCI_CAP_ID_EXP; /* PCI_Express */
    1698     pThis->dev.config[0x90+1] = 0x50; /* next */
     1705#ifdef HDA_AS_PCI_EXPRESS
     1706    /* PCI Express */
     1707    PCIDevSetByte  (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
     1708    PCIDevSetByte  (&pThis->dev, 0x80 + 1, 0x60); /* next */
    16991709    /* Device flags */
    1700     PCIDevSetWord  (&pThis->dev, 0x90 + 2, /* version */ 0x1);
     1710    PCIDevSetWord  (&pThis->dev, 0x80 + 2,
     1711                    /* version */ 0x1     |
     1712                    /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
     1713                    /* MSI */ (100) << 9
     1714                    );
    17011715    /* Device capabilities */
    1702     PCIDevSetDWord (&pThis->dev, 0x90 + 4, 0);
     1716    PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
    17031717    /* Device control */
    1704     PCIDevSetWord  (&pThis->dev, 0x90 + 8, 0);
     1718    PCIDevSetWord  (&pThis->dev, 0x80 + 8, 0);
    17051719    /* Device status */
    1706     PCIDevSetWord  (&pThis->dev, 0x90 + 10, 0);
     1720    PCIDevSetWord  (&pThis->dev, 0x80 + 10, 0);
    17071721    /* Link caps */
    1708     PCIDevSetDWord (&pThis->dev, 0x90 + 12, 0);
     1722    PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
    17091723    /* Link control */
    1710     PCIDevSetWord  (&pThis->dev, 0x90 + 16, 0);
     1724    PCIDevSetWord  (&pThis->dev, 0x80 + 16, 0);
    17111725    /* Link status */
    1712     PCIDevSetWord  (&pThis->dev, 0x90 + 18, 0);
     1726    PCIDevSetWord  (&pThis->dev, 0x80 + 18, 0);
    17131727    /* Slot capabilities */
    1714     PCIDevSetDWord (&pThis->dev, 0x90 + 20, 0);
     1728    PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
    17151729    /* Slot control */
    1716     PCIDevSetWord  (&pThis->dev, 0x90 + 24, 0);
     1730    PCIDevSetWord  (&pThis->dev, 0x80 + 24, 0);
    17171731    /* Slot status */
    1718     PCIDevSetWord  (&pThis->dev, 0x90 + 26, 0);
     1732    PCIDevSetWord  (&pThis->dev, 0x80 + 26, 0);
    17191733    /* Root control */
    1720     PCIDevSetWord  (&pThis->dev, 0x90 + 28, 0);
     1734    PCIDevSetWord  (&pThis->dev, 0x80 + 28, 0);
    17211735    /* Root capabilities */
    1722     PCIDevSetWord  (&pThis->dev, 0x90 + 30, 0);
     1736    PCIDevSetWord  (&pThis->dev, 0x80 + 30, 0);
    17231737    /* Root status */
    1724     PCIDevSetDWord (&pThis->dev, 0x90 + 32, 0);
     1738    PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
    17251739    /* Device capabilities 2 */
    1726     PCIDevSetDWord (&pThis->dev, 0x90 + 36, 0);
     1740    PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
    17271741    /* Device control 2 */
    1728     PCIDevSetQWord (&pThis->dev, 0x90 + 40, 0);
     1742    PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
    17291743    /* Link control 2 */
    1730     PCIDevSetQWord (&pThis->dev, 0x90 + 48, 0);
     1744    PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
    17311745    /* Slot control 2 */
    1732     PCIDevSetWord  (&pThis->dev, 0x90 + 56, 0);
     1746    PCIDevSetWord  (&pThis->dev, 0x80 + 56, 0);
    17331747#endif
    17341748

  • trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

    r32715 r32765  
    184184// See 7.2.2. PCI Express Enhanced Configuration Mechanism for details of address
    185185// mapping, we take n=8 approach
    186 DECLINLINE(void) ich9pciPhysToPciAddr(RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
    187 {
     186DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
     187{
     188    GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
    188189    pPciAddr->iBus          = (GCPhysAddr >> 20) & ((1<<8)       - 1);
    189190    pPciAddr->iDeviceFunc   = (GCPhysAddr >> 15) & ((1<<(5+3))   - 1); // 5 bits - device, 3 bits - function
    … …  
    288289static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
    289290{
     291
     292    if (pAddr->iRegister > 0xff)
     293    {
     294        LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
     295        return 0;
     296    }
     297
    290298    if (pAddr->iBus != 0)
    291299    {
    … …  
    367375static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
    368376{
     377    if (pPciAddr->iRegister > 0xff)
     378    {
     379        LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister));
     380        *pu32 = 0;
     381        return 0;
     382    }
     383
     384
    369385    if (pPciAddr->iBus != 0)
    370386    {
    … …  
    536552    uint32_t u32 = 0;
    537553
    538     ich9pciPhysToPciAddr(GCPhysAddr, &aDest);
     554    ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
    539555
    540556    PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
    … …  
    556572    int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
    557573    PCI_UNLOCK(pDevIns);
    558     Assert(false);
    559574
    560575    return rc;
    … …  
    567582    uint32_t    rv = 0;
    568583
    569     ich9pciPhysToPciAddr(GCPhysAddr, &aDest);
     584    ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
    570585
    571586    PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
    … …  
    591606    PCI_UNLOCK(pDevIns);
    592607
    593     Assert(false);
    594608    return rc;
    595609}

  • trunk/src/VBox/Devices/PC/DevACPI.cpp

    r32637 r32765  
    10181018
    10191019/** MMCONFIG PCI config space access (MCFG) descriptor */
    1020 static void acpiSetupMCFG(ACPIState *s, RTGCPHYS32 addr, uint8_t    u8StartBus, uint8_t    u8EndBus)
     1020static void acpiSetupMCFG(ACPIState *s, RTGCPHYS32 addr)
    10211021{
    10221022    struct {
    … …  
    10241024        ACPITBLMCFGENTRY  entry;
    10251025    } tbl;
     1026
     1027    uint8_t    u8StartBus = 0;
     1028    uint8_t    u8EndBus   = (s->u64PciConfigMMioLength >> 20) - 1;
    10261029
    10271030    memset(&tbl, 0, sizeof(tbl));
    … …  
    23222325    if (s->fUseMcfg)
    23232326    {
    2324         acpiSetupMCFG(s, GCPhysMcfg + addend, 0, 255);
     2327        acpiSetupMCFG(s, GCPhysMcfg + addend);
    23252328        aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
    23262329        aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;

  • trunk/src/VBox/Main/ConsoleImpl2.cpp

    r32727 r32765  
    538538    if (chipsetType == ChipsetType_ICH9)
    539539    {
    540         u64McfgLength = 0x10000000;
     540        /* We'd better have 0x10000000 region, to cover 256 buses
     541           but this put too much load on hypervisor heap */
     542        u64McfgLength = 0x4000000; //0x10000000;
    541543        cbRamHole += u64McfgLength;
    542         u64McfgBase = _4G -  cbRamHole;
     544        u64McfgBase = _4G - cbRamHole;
    543545    }
    544546
    … …  
    852854        InsertConfigNode(pInst,    "Config", &pCfg);
    853855        InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
     856        if (chipsetType == ChipsetType_ICH9)
     857        {
     858            InsertConfigInteger(pCfg,  "McfgBase",   u64McfgBase);
     859            InsertConfigInteger(pCfg,  "McfgLength", u64McfgLength);
     860        }
    854861
    855862#if 0 /* enable this to test PCI bridging */
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