Changeset 32776 in vbox for trunk/src/VBox/Devices/Bus

Timestamp:

Sep 27, 2010 1:31:42 PM (14 years ago)

Author:

vboxsync

Message:

PCI: refactoring for PCIe work

Location:

trunk/src/VBox/Devices/Bus

Files:

• DevPCI.cpp (modified) (8 diffs)
• DevPciIch9.cpp (modified) (15 diffs)
• PCIInternal.h (modified) (2 diffs)

trunk/src/VBox/Devices/Bus/DevPCI.cpp

@@ -773 +773 @@
          */
         PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
-        AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
+        AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
                   ("Device is not a PCI bridge but on the list of PCI bridges\n"));
 
@@ -1721 +1721 @@
             }
         }
-        pPciDev->Int.s.fRequestedDevFn = false;
+        PCIClearRequestedDevfunc(pPciDev);
     }
     else
@@ -1742 +1742 @@
             AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
                                            iDev, pszName, pBus->devices[iDev]->name));
-            if (    pBus->devices[iDev]->Int.s.fRequestedDevFn
-                ||  (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
-                ||  (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
+            if (    PCIIsRequestedDevfunc(pBus->devices[iDev])
+                ||  (pBus->devices[iDev + 1] && PCIIsRequestedDevfunc(pBus->devices[iDev + 1]))
+                ||  (pBus->devices[iDev + 2] && PCIIsRequestedDevfunc(pBus->devices[iDev + 2]))
+                ||  (pBus->devices[iDev + 3] && PCIIsRequestedDevfunc(pBus->devices[iDev + 3]))
+                ||  (pBus->devices[iDev + 4] && PCIIsRequestedDevfunc(pBus->devices[iDev + 4]))
+                ||  (pBus->devices[iDev + 5] && PCIIsRequestedDevfunc(pBus->devices[iDev + 5]))
+                ||  (pBus->devices[iDev + 6] && PCIIsRequestedDevfunc(pBus->devices[iDev + 6]))
+                ||  (pBus->devices[iDev + 7] && PCIIsRequestedDevfunc(pBus->devices[iDev + 7])))
             {
                 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
@@ -1786 +1786 @@
             }
         } /* if conflict */
-        pPciDev->Int.s.fRequestedDevFn = true;
+        PCISetRequestedDevfunc(pPciDev);
     }
 
@@ -1798 +1798 @@
     pPciDev->Int.s.pfnConfigWrite   = pci_default_write_config;
     pBus->devices[iDev]             = pPciDev;
-    if (pPciDev->Int.s.fPciToPciBridge)
+    if (PCIIsPci2PciBridge(pPciDev))
     {
         AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
@@ -2073 +2073 @@
 
     pBus->PciDev.pDevIns              = pDevIns;
-    pBus->PciDev.Int.s.fRequestedDevFn= true;
+    PCISetRequestedDevfunc(&pBus->PciDev);
     pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
 
@@ -2084 +2084 @@
 
     pGlobals->PIIX3State.dev.pDevIns      = pDevIns;
-    pGlobals->PIIX3State.dev.Int.s.fRequestedDevFn= true;
+    PCISetRequestedDevfunc(&pGlobals->PIIX3State.dev);
     pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
     piix3_reset(&pGlobals->PIIX3State);
@@ -2453 +2453 @@
 
     pBus->PciDev.pDevIns                    = pDevIns;
-    pBus->PciDev.Int.s.fPciToPciBridge      = true;
+
+    /* Bridge-specific data */
+    PCISetPci2PciBridge(&pBus->PciDev);
     pBus->PciDev.Int.s.pfnBridgeConfigRead  = pcibridgeConfigRead;
     pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -621 +621 @@
          */
         PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
-        AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
+        AssertMsg(pBridgeTemp && PCIIsPci2PciBridge(pBridgeTemp),
                   ("Device is not a PCI bridge but on the list of PCI bridges\n"));
 
@@ -771 +771 @@
 static DECLCALLBACK(int) ich9pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
 {
-    return 0;
+
+    PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
+    
+    /*
+     * Check input.
+     */
+    if (    !pszName
+        ||  !pPciDev
+        ||  iDev >= (int)RT_ELEMENTS(pBus->apDevices))
+    {
+        AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
+        return VERR_INVALID_PARAMETER;
+    }
+
+    /*
+     * Register the device.
+     */
+    return ich9pciRegisterInternal(pBus, iDev, pPciDev, pszName);
 }
 
@@ -831 +848 @@
  * @param   pSSM            The handle to save the state to.
  */
-static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
+static DECLCALLBACK(int) ich9pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
 {
     return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
 }
 
-static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
+static int ich9pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
 {
     /*
@@ -860 +877 @@
 }
 
-static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
+static DECLCALLBACK(int) ich9pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
 {
     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
-    return pciR3CommonSaveExec(pThis, pSSM);
-}
-
-
-static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
+    return ich9pciR3CommonSaveExec(pThis, pSSM);
+}
+
+
+static DECLCALLBACK(int) ich9pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
 {
     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
-    return pciR3CommonSaveExec(pThis, pSSM);
+    return ich9pciR3CommonSaveExec(pThis, pSSM);
+}
+
+
+static void ich9pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
+{
+    PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
+
+    LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
+
+    /* If the current bus is not the target bus search for the bus which contains the device. */
+    if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
+    {
+        PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
+        if (pBridgeDevice)
+        {
+            AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
+            pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
+        }
+    }
+    else
+    {
+        /* This is the target bus, pass the write to the device. */
+        PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
+        if (pPciDev)
+        {
+            Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
+            pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
+        }
+    }
+}
+
+static uint32_t ich9pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
+{
+    PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
+    uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
+
+    LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
+
+    /* If the current bus is not the target bus search for the bus which contains the device. */
+    if (iBus != PCIDevGetByte(&pBus->aPciDev, VBOX_PCI_SECONDARY_BUS))
+    {
+        PPCIDEVICE pBridgeDevice = ich9pciFindBridge(pBus, iBus);
+        if (pBridgeDevice)
+        {
+            AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
+            u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
+        }
+    }
+    else
+    {
+        /* This is the target bus, pass the read to the device. */
+        PPCIDEVICE pPciDev = pBus->apDevices[iDevice];
+        if (pPciDev)
+        {
+            u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
+            Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
+        }
+    }
+
+    return u32Value;
 }
 
@@ -1018 +1095 @@
                 }
                 if (off == VBOX_PCI_COMMAND)
-                    PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
+                    PCIDevSetCommand(pDev, 0); /* For remapping, see ich9pciR3CommonLoadExec. */
                 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
             }
@@ -1040 +1117 @@
 
 /**
- * Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
+ * Common worker for ich9pciR3LoadExec and ich9pcibridgeR3LoadExec.
  *
  * @returns VBox status code.
@@ -1048 +1125 @@
  * @param   uPass               The pass.
  */
-static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
+static DECLCALLBACK(int) ich9pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
 {
     uint32_t    u32;
@@ -1154 +1231 @@
  * @param   pSSM            The handle to the saved state.
  */
-static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
+static DECLCALLBACK(int) ich9pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
 {
     return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
 }
 
-static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
+static DECLCALLBACK(int) ich9pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
 {
     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
         return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
-    return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
-}
-
-static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
+    return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
+}
+
+static DECLCALLBACK(int) ich9pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
 {
     PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
     if (uVersion > VBOX_ICH9PCI_SAVED_STATE_VERSION)
         return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
-    return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
+    return ich9pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
 }
 
@@ -1693 +1770 @@
         if (!strcmp(pszName, PciSlotAssignments[i].pszName))
         {
-            pPciDev->Int.s.fRequestedDevFn = true;
+            PCISetRequestedDevfunc(pPciDev);
             return (PciSlotAssignments[i].iSlot << 3) + PciSlotAssignments[i].iFunction;
         }
@@ -1709 +1786 @@
                 &&  !pBus->apDevices[iPos + 7])
         {
-            pPciDev->Int.s.fRequestedDevFn = false;
+            PCIClearRequestedDevfunc(pPciDev);
             return iPos;
         }
@@ -1720 +1797 @@
     PCIDevice** aSlot = &pBus->apDevices[iSlot << 3];
 
-    return    (aSlot[0] && aSlot[0]->Int.s.fRequestedDevFn)
-           || (aSlot[1] && aSlot[1]->Int.s.fRequestedDevFn)
-           || (aSlot[2] && aSlot[2]->Int.s.fRequestedDevFn)
-           || (aSlot[3] && aSlot[3]->Int.s.fRequestedDevFn)
-           || (aSlot[4] && aSlot[4]->Int.s.fRequestedDevFn)
-           || (aSlot[5] && aSlot[5]->Int.s.fRequestedDevFn)
-           || (aSlot[6] && aSlot[6]->Int.s.fRequestedDevFn)
-           || (aSlot[7] && aSlot[7]->Int.s.fRequestedDevFn)
+    return     (aSlot[0] && PCIIsRequestedDevfunc(aSlot[0]))
+            || (aSlot[1] && PCIIsRequestedDevfunc(aSlot[1]))
+            || (aSlot[2] && PCIIsRequestedDevfunc(aSlot[2]))
+            || (aSlot[3] && PCIIsRequestedDevfunc(aSlot[3]))
+            || (aSlot[4] && PCIIsRequestedDevfunc(aSlot[4]))
+            || (aSlot[5] && PCIIsRequestedDevfunc(aSlot[5]))
+            || (aSlot[6] && PCIIsRequestedDevfunc(aSlot[6]))
+            || (aSlot[7] && PCIIsRequestedDevfunc(aSlot[7]))
            ;
 }
@@ -1750 +1827 @@
      * its current habitant, if it wasn't hard assigned too.
      */
-    if (pPciDev->Int.s.fRequestedDevFn &&
-        pBus->apDevices[iDev]            &&
-        pBus->apDevices[iDev]->Int.s.fRequestedDevFn)
+    if (PCIIsRequestedDevfunc(pPciDev) &&
+        pBus->apDevices[iDev]          &&
+        PCIIsRequestedDevfunc(pBus->apDevices[iDev]))
     {
         /*
@@ -1796 +1873 @@
     pPciDev->Int.s.pfnConfigWrite   = ich9pciConfigWrite;
     pBus->apDevices[iDev]           = pPciDev;
-    if (pPciDev->Int.s.fPciToPciBridge)
+    if (PCIIsPci2PciBridge(pPciDev))
     {
         AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->apDevices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
@@ -1918 +1995 @@
     PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
     PciBusReg.pfnSetIrqR3             = ich9pciSetIrq;
-    PciBusReg.pfnSaveExecR3           = pciGenericSaveExec;
-    PciBusReg.pfnLoadExecR3           = pciGenericLoadExec;
+    PciBusReg.pfnSaveExecR3           = ich9pciGenericSaveExec;
+    PciBusReg.pfnLoadExecR3           = ich9pciGenericLoadExec;
     PciBusReg.pfnFakePCIBIOSR3        = ich9pciFakePCIBIOS;
     PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pciSetIrq" : NULL;
@@ -2091 +2168 @@
                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
     Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
+
+    /*
+     * Init data and register the PCI bus.
+     */
+    PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
+    pBus->pDevInsR3 = pDevIns;
+    pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
+    pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
+    pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->apDevices));
+
+    PDMPCIBUSREG PciBusReg;
+    PciBusReg.u32Version              = PDM_PCIBUSREG_VERSION;
+    PciBusReg.pfnRegisterR3           = ich9pcibridgeRegister;
+    PciBusReg.pfnIORegionRegisterR3   = ich9pciIORegionRegister;
+    PciBusReg.pfnSetConfigCallbacksR3 = ich9pciSetConfigCallbacks;
+    PciBusReg.pfnSetIrqR3             = ich9pcibridgeSetIrq;
+    PciBusReg.pfnSaveExecR3           = ich9pciGenericSaveExec;
+    PciBusReg.pfnLoadExecR3           = ich9pciGenericLoadExec;
+    PciBusReg.pfnFakePCIBIOSR3        = NULL; /* Only needed for the first bus. */
+    PciBusReg.pszSetIrqRC             = fGCEnabled ? "ich9pcibridgeSetIrq" : NULL;
+    PciBusReg.pszSetIrqR0             = fR0Enabled ? "ich9pcibridgeSetIrq" : NULL;
+    rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Failed to register ourselves as a PCI Bus"));
+    if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
+        return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
+                                   N_("PCI helper version mismatch; got %#x expected %#x"),
+                                   pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
+
+    pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
+    pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
+
+    /*
+     * Fill in PCI configs and add them to the bus.
+     */
+    PCIDevSetVendorId(  &pBus->aPciDev, 0x8086); /* Intel */
+    PCIDevSetDeviceId(  &pBus->aPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
+    PCIDevSetRevisionId(&pBus->aPciDev,   0xf2);
+    PCIDevSetClassSub(  &pBus->aPciDev,   0x04); /* pci2pci */
+    PCIDevSetClassBase( &pBus->aPciDev,   0x06); /* PCI_bridge */
+    PCIDevSetClassProg( &pBus->aPciDev,   0x01); /* Supports subtractive decoding. */
+    PCIDevSetHeaderType(&pBus->aPciDev,   0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
+    PCIDevSetCommand(   &pBus->aPciDev,   0x00);
+    PCIDevSetStatus(    &pBus->aPciDev,   0x20); /* 66MHz Capable. */
+    PCIDevSetInterruptLine(&pBus->aPciDev, 0x00); /* This device does not assert interrupts. */
+
+    /*
+     * This device does not generate interrupts. Interrupt delivery from
+     * devices attached to the bus is unaffected.
+     */
+    PCIDevSetInterruptPin (&pBus->aPciDev, 0x00);
+
+    pBus->aPciDev.pDevIns                    = pDevIns;
+
+    /* Bridge-specific data */
+    PCISetPci2PciBridge(&pBus->aPciDev);
+    pBus->aPciDev.Int.s.pfnBridgeConfigRead  = ich9pcibridgeConfigRead;
+    pBus->aPciDev.Int.s.pfnBridgeConfigWrite = ich9pcibridgeConfigWrite;
+
+    /*
+     * Register this PCI bridge. The called function will take care on which bus we will get registered.
+     */
+    rc = PDMDevHlpPCIRegister (pDevIns, &pBus->aPciDev);
+    if (RT_FAILURE(rc))
+        return rc;
+
+    /*
+     * The iBus property doesn't really represent the bus number
+     * because the guest and the BIOS can choose different bus numbers
+     * for them.
+     * The bus number is mainly for the setIrq function to indicate
+     * when the host bus is reached which will have iBus = 0.
+     * Thathswhy the + 1.
+     */
+    pBus->iBus = iInstance + 1;
+
+    /*
+     * Register SSM handlers. We use the same saved state version as for the host bridge
+     * to make changes easier.
+     */
+    rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_ICH9PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
+                                NULL, NULL, NULL,
+                                NULL, ich9pcibridgeR3SaveExec, NULL,
+                                NULL, ich9pcibridgeR3LoadExec, NULL);
+    if (RT_FAILURE(rc))
+        return rc;
+
 
     return VINF_SUCCESS;

trunk/src/VBox/Devices/Bus/PCIInternal.h

@@ -72 +72 @@
 struct PCIBus;
 
+enum {
+    /** Set if the specific device fun was requested by PDM.
+     * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */
+    PCIDEV_FLAG_REQUESTED_DEVFUNC = 1<<0,
+    /** Flag whether the device is a pci-to-pci bridge.
+     * This is set prior to device registration.  */
+    PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = 1<<1,
+    /** Flag whether the device is a PCI Express device.
+     * This is set prior to device registration.  */
+    PCIDEV_FLAG_PCI_EXPRESS_DEVICE = 1<<2
+};
+
 /**
  * PCI Device - Internal data.
@@ -94 +106 @@
     R3PTRTYPE(PFNPCICONFIGWRITE)    pfnConfigWrite;
 
-    /** Set if the specific device fun was requested by PDM.
-     * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */
-    bool                            fRequestedDevFn;
-    /** Flag whether the device is a pci-to-pci bridge.
-     * This is set prior to device registration.  */
-    bool                            fPciToPciBridge;
+    /* Flags of this PCI device, see PCIDEV_FLAG_ constants */
+    int32_t                         uFlags;
     /** Current state of the IRQ pin of the device. */
     int32_t                         uIrqPinState;