Changeset 33472 in vbox for trunk

Timestamp:

Oct 26, 2010 3:56:09 PM (14 years ago)

Author:

vboxsync

Message:

PCI: cleanup, fixes

File:

• trunk/src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (19 diffs)

trunk/src/VBox/Devices/Bus/DevPciIch9.cpp

@@ -93 +93 @@
 #endif
 
+    /** PCI bus which is attached to the host-to-PCI bridge. */
+    PCIBUS              aPciBus;
+
+
     /** I/O APIC irq levels */
     volatile uint32_t   uaPciApicIrqLevels[PCI_APIC_IRQ_PINS];
@@ -105 +109 @@
 #endif
     /* Physical address of PCI config space MMIO region */
-     uint64_t            u64PciConfigMMioAddress;
+    uint64_t            u64PciConfigMMioAddress;
     /* Length of PCI config space MMIO region */
-    uint64_t             u64PciConfigMMioLength;
+    uint64_t            u64PciConfigMMioLength;
 
 
     /** Config register. */
     uint32_t            uConfigReg;
-
-    /** PCI bus which is attached to the host-to-PCI bridge. */
-    PCIBUS              aPciBus;
-
 } PCIGLOBALS, *PPCIGLOBALS;
 
@@ -189 +189 @@
 DECLINLINE(void) ich9pciPhysToPciAddr(PPCIGLOBALS pGlobals, RTGCPHYS GCPhysAddr, PciAddress* pPciAddr)
 {
-    GCPhysAddr = GCPhysAddr - pGlobals->u64PciConfigMMioAddress;
-    pPciAddr->iBus          = (GCPhysAddr >> 20) & ((1<<8)       - 1);
+    pPciAddr->iBus          = (GCPhysAddr >> 20) & ((1<<6)       - 1);
     pPciAddr->iDeviceFunc   = (GCPhysAddr >> 12) & ((1<<(5+3))   - 1); // 5 bits - device, 3 bits - function
     pPciAddr->iRegister     = (GCPhysAddr >>  0) & ((1<<(6+4+2)) - 1); // 6 bits - register, 4 bits - extended register, 2 bits -Byte Enable
@@ -290 +289 @@
 }
 
-static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, uint32_t val, int len)
+static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr,
+                                uint32_t val, int len, int rcReschedule)
 {
 
@@ -296 +296 @@
     {
         LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));
-        return 0;
+        return VINF_SUCCESS;
     }
 
@@ -311 +311 @@
             }
 #else
-            return VINF_IOM_HC_IOPORT_WRITE;
+            return rcReschedule;
 #endif
         }
@@ -324 +324 @@
             aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);
 #else
-            return VINF_IOM_HC_IOPORT_WRITE;
+            return rcReschedule;
 #endif
         }
@@ -346 +346 @@
     ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
 
-    return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
+    return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE);
 }
 
@@ -376 +376 @@
 }
 
-static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len, uint32_t *pu32)
+static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len,
+                               uint32_t *pu32, int rcReschedule)
 {
     if (pPciAddr->iRegister > 0xff)
@@ -398 +399 @@
             }
 #else
-            return VINF_IOM_HC_IOPORT_READ;
+            return rcReschedule;
 #endif
         }
@@ -411 +412 @@
             Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));
 #else
-            return VINF_IOM_HC_IOPORT_READ;
+            return rcReschedule;
 #endif
         }
@@ -434 +435 @@
     ich9pciStateToPciAddr(pGlobals, addr, &aPciAddr);
 
-    return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32);
+    return ich9pciDataReadAddr(pGlobals, &aPciAddr, len, pu32, VINF_IOM_HC_IOPORT_READ);
 }
 
@@ -571 +572 @@
     uint32_t u32 = 0;
 
-    Log2(("ich9pciMcfgMMIOWrite: %p(%d) \n", GCPhysAddr, cb));
-
-    PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
+    Log2(("ich9pciMcfgMMIOWrite: %RGp(%d) \n", GCPhysAddr, cb));
+
+    PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_WRITE);
 
     ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
@@ -592 +593 @@
             break;
     }
-    int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb);
+    int rc = ich9pciDataWriteAddr(pGlobals, &aDest, u32, cb, VINF_IOM_HC_MMIO_WRITE);
     PCI_UNLOCK(pDevIns);
 
@@ -604 +605 @@
     uint32_t    rv = 0xffffffff;
 
-    Log2(("ich9pciMcfgMMIORead: %p(%d) \n", GCPhysAddr, cb));
-
-    PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
+    LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb));
+
+    PCI_LOCK(pDevIns, VINF_IOM_HC_MMIO_READ);
 
     ich9pciPhysToPciAddr(pGlobals, GCPhysAddr, &aDest);
 
-    int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv);
-
-    switch (cb)
-    {
-        case 1:
-            *(uint8_t*)pv   = (uint8_t)rv;
-            break;
-        case 2:
-            *(uint16_t*)pv  = (uint16_t)rv;
-            break;
-        case 4:
-            *(uint32_t*)pv  = (uint32_t)rv;
-            break;
-        default:
-            Assert(false);
-            break;
+    int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ);
+
+    Log2(("ich9pciMcfgMMIORead: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n", 
+          aDest.iBus, aDest.iDeviceFunc >> 3, aDest.iDeviceFunc & 0x7, aDest.iRegister,
+          cb, rv, rc));
+
+    if (RT_SUCCESS(rc))
+    {
+        switch (cb)
+        {
+            case 1:
+                *(uint8_t*)pv   = (uint8_t)rv;
+                break;
+            case 2:
+                *(uint16_t*)pv  = (uint16_t)rv;
+                break;
+            case 4:
+                *(uint32_t*)pv  = (uint32_t)rv;
+                break;
+            default:
+                Assert(false);
+                break;
+        }
     }
     PCI_UNLOCK(pDevIns);
@@ -1404 +1412 @@
     aPciAddr.iRegister = addr;
 
-    int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val);
+    /* cannot be rescheduled, as already in R3 */
+    int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR);
     AssertRC(rc);
     switch (len)
@@ -1426 +1435 @@
     aPciAddr.iRegister = addr;
 
-    ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len);
+    /* cannot be rescheduled, as already in R3 */
+    int rc = ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VERR_INTERNAL_ERROR);
+    AssertRC(rc);
 }
 
@@ -2300 +2311 @@
         }
 
-         if (fGCEnabled)
-         {
-
-             rc = PDMDevHlpMMIORegisterRC(pDevIns,
-                                          pGlobals->u64PciConfigMMioAddress,
-                                          pGlobals->u64PciConfigMMioLength,
-                                          0,
-                                          "ich9pciMcfgMMIOWrite",
-                                          "ich9pciMcfgMMIORead",
-                                          NULL /* fill */);
-             if (RT_FAILURE(rc))
-             {
-                 AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
-                 return rc;
-             }
-         }
-
-
-         if (fR0Enabled)
-         {
-
-             rc = PDMDevHlpMMIORegisterR0(pDevIns,
-                                          pGlobals->u64PciConfigMMioAddress,
-                                          pGlobals->u64PciConfigMMioLength,
-                                          0,
-                                          "ich9pciMcfgMMIOWrite",
-                                          "ich9pciMcfgMMIORead",
-                                          NULL /* fill */);
-             if (RT_FAILURE(rc))
-             {
-                 AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
-                 return rc;
-             }
-         }
+        if (fGCEnabled)
+        {
+            
+            rc = PDMDevHlpMMIORegisterRC(pDevIns,
+                                         pGlobals->u64PciConfigMMioAddress,
+                                         pGlobals->u64PciConfigMMioLength,
+                                         0,
+                                         "ich9pciMcfgMMIOWrite",
+                                         "ich9pciMcfgMMIORead",
+                                         NULL /* fill */);
+            if (RT_FAILURE(rc))
+            {
+                AssertMsgRC(rc, ("Cannot register MCFG MMIO (GC): %Rrc\n", rc));
+                return rc;
+            }
+        }
+        
+        
+        if (fR0Enabled)
+        {
+            
+            rc = PDMDevHlpMMIORegisterR0(pDevIns,
+                                         pGlobals->u64PciConfigMMioAddress,
+                                         pGlobals->u64PciConfigMMioLength,
+                                         0,
+                                         "ich9pciMcfgMMIOWrite",
+                                         "ich9pciMcfgMMIORead",
+                                         NULL /* fill */);
+            if (RT_FAILURE(rc))
+            {
+                AssertMsgRC(rc, ("Cannot register MCFG MMIO (R0): %Rrc\n", rc));
+                return rc;
+            }
+        }
     }
 
@@ -2399 +2410 @@
     {
         if (pBus->apDevices[i])
+        {
             pBus->apDevices[i]->Int.s.pBusRC += offDelta;
+            if (pBus->apDevices[i]->Int.s.pMsixPageRC)
+                pBus->apDevices[i]->Int.s.pMsixPageRC += offDelta;
+        }
     }