- Timestamp:
- Oct 26, 2010 6:02:48 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r33472 r33476 290 290 291 291 static int ich9pciDataWriteAddr(PPCIGLOBALS pGlobals, PciAddress* pAddr, 292 uint32_t val, int len, int rcReschedule) 293 { 292 uint32_t val, int cb, int rcReschedule) 293 { 294 int rc = VINF_SUCCESS; 294 295 295 296 if (pAddr->iRegister > 0xff) 296 297 { 297 LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, len, val));298 return VINF_SUCCESS;298 LogRel(("PCI: attempt to write extended register: %x (%d) <- val\n", pAddr->iRegister, cb, val)); 299 goto out; 299 300 } 300 301 … … 308 309 { 309 310 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite); 310 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, len);311 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, pAddr->iBus, pAddr->iDeviceFunc, pAddr->iRegister, val, cb); 311 312 } 312 313 #else 313 return rcReschedule; 314 rc = rcReschedule; 315 goto out; 314 316 #endif 315 317 } … … 321 323 #ifdef IN_RING3 322 324 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pAddr->iDeviceFunc]; 323 Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, len));324 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, len);325 Log(("ich9pciConfigWrite: %s: addr=%02x val=%08x len=%d\n", aDev->name, pAddr->iRegister, val, cb)); 326 aDev->Int.s.pfnConfigWrite(aDev, pAddr->iRegister, val, cb); 325 327 #else 326 return rcReschedule; 328 rc = rcReschedule; 329 goto out; 327 330 #endif 328 331 } 329 332 } 330 return VINF_SUCCESS; 333 334 out: 335 Log2(("ich9pciDataWriteAddr: %02x:%02x:%02x reg %x(%d) %x %Rrc\n", 336 pAddr->iBus, pAddr->iDeviceFunc >> 3, pAddr->iDeviceFunc & 0x7, pAddr->iRegister, 337 cb, val, rc)); 338 339 return rc; 331 340 } 332 341 … … 335 344 PciAddress aPciAddr; 336 345 337 Log (("ich9pciDataWrite: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));346 LogFlow(("ich9pciDataWrite: config=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len)); 338 347 339 348 if (!(pGlobals->uConfigReg & (1 << 31))) … … 347 356 348 357 return ich9pciDataWriteAddr(pGlobals, &aPciAddr, val, len, VINF_IOM_HC_IOPORT_WRITE); 358 } 359 360 static void ich9pciNoMem(void* ptr, int cb) 361 { 362 memset(ptr, 0xff, cb); 349 363 } 350 364 … … 376 390 } 377 391 378 static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int len,392 static int ich9pciDataReadAddr(PPCIGLOBALS pGlobals, PciAddress* pPciAddr, int cb, 379 393 uint32_t *pu32, int rcReschedule) 380 394 { 395 int rc = VINF_SUCCESS; 396 381 397 if (pPciAddr->iRegister > 0xff) 382 398 { 383 399 LogRel(("PCI: attempt to read extended register: %x\n", pPciAddr->iRegister)); 384 *pu32 = 0;385 return 0;400 ich9pciNoMem(pu32, cb); 401 goto out; 386 402 } 387 403 … … 396 412 { 397 413 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead); 398 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, len);414 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, pPciAddr->iBus, pPciAddr->iDeviceFunc, pPciAddr->iRegister, cb); 399 415 } 416 else 417 ich9pciNoMem(pu32, cb); 400 418 #else 401 return rcReschedule; 419 rc = rcReschedule; 420 goto out; 402 421 #endif 403 } 422 } else 423 ich9pciNoMem(pu32, cb); 404 424 } 405 425 else … … 409 429 #ifdef IN_RING3 410 430 R3PTRTYPE(PCIDevice *) aDev = pGlobals->aPciBus.apDevices[pPciAddr->iDeviceFunc]; 411 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, len);412 Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, len));431 *pu32 = aDev->Int.s.pfnConfigRead(aDev, pPciAddr->iRegister, cb); 432 Log(("ich9pciDataReadAddr: %s: addr=%02x val=%08x len=%d\n", aDev->name, pPciAddr->iRegister, *pu32, cb)); 413 433 #else 414 return rcReschedule; 434 rc = rcReschedule; 435 goto out; 415 436 #endif 416 437 } 417 } 418 419 return VINF_SUCCESS; 438 else 439 ich9pciNoMem(pu32, cb); 440 } 441 442 out: 443 Log2(("ich9pciDataReadAddr: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n", 444 pPciAddr->iBus, pPciAddr->iDeviceFunc >> 3, pPciAddr->iDeviceFunc & 0x7, pPciAddr->iRegister, 445 cb, *pu32, rc)); 446 447 return rc; 420 448 } 421 449 … … 424 452 PciAddress aPciAddr; 425 453 426 *pu32 = 0xffffffff;454 LogFlow(("ich9pciDataRead: config=%x len=%d\n", pGlobals->uConfigReg, len)); 427 455 428 456 if (!(pGlobals->uConfigReg & (1 << 31))) … … 603 631 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 604 632 PciAddress aDest; 605 uint32_t rv = 0xffffffff;633 uint32_t rv; 606 634 607 635 LogFlow(("ich9pciMcfgMMIORead: %RGp(%d) \n", GCPhysAddr, cb)); … … 612 640 613 641 int rc = ich9pciDataReadAddr(pGlobals, &aDest, cb, &rv, VINF_IOM_HC_MMIO_READ); 614 615 Log2(("ich9pciMcfgMMIORead: %02x:%02x:%02x reg %x(%d) gave %x %Rrc\n",616 aDest.iBus, aDest.iDeviceFunc >> 3, aDest.iDeviceFunc & 0x7, aDest.iRegister,617 cb, rv, rc));618 642 619 643 if (RT_SUCCESS(rc)) … … 1000 1024 { 1001 1025 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS); 1002 uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */1026 uint32_t u32Value; 1003 1027 1004 1028 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb)); … … 1013 1037 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb); 1014 1038 } 1039 else 1040 ich9pciNoMem(&u32Value, cb); 1015 1041 } 1016 1042 else … … 1023 1049 Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb)); 1024 1050 } 1051 else 1052 ich9pciNoMem(&u32Value, cb); 1025 1053 } 1026 1054 … … 1405 1433 static uint32_t ich9pciConfigRead(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t len) 1406 1434 { 1407 uint32_t u32Val = 0xffffffff; 1435 /* Will only work in LSB case */ 1436 uint32_t u32Val; 1408 1437 PciAddress aPciAddr; 1409 1438 … … 1415 1444 int rc = ich9pciDataReadAddr(pGlobals, &aPciAddr, len, &u32Val, VERR_INTERNAL_ERROR); 1416 1445 AssertRC(rc); 1417 switch (len)1418 {1419 case 1:1420 u32Val &= 0xff;1421 break;1422 case 2:1423 u32Val &= 0xffff;1424 break;1425 }1426 1446 return u32Val; 1427 1447 } … … 2313 2333 if (fGCEnabled) 2314 2334 { 2315 2335 2316 2336 rc = PDMDevHlpMMIORegisterRC(pDevIns, 2317 2337 pGlobals->u64PciConfigMMioAddress, … … 2327 2347 } 2328 2348 } 2329 2330 2349 2350 2331 2351 if (fR0Enabled) 2332 2352 { 2333 2353 2334 2354 rc = PDMDevHlpMMIORegisterR0(pDevIns, 2335 2355 pGlobals->u64PciConfigMMioAddress,
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