- Timestamp:
- Jan 18, 2011 10:43:11 AM (14 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
-
VMMR3/CPUMDbg.cpp (modified) (12 diffs)
-
VMMR3/DBGFReg.cpp (modified) (8 diffs)
-
include/DBGFInternal.h (modified) (1 diff)
-
testcase/tstVMStructRC.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp
r35513 r35601 39 39 { 40 40 PVMCPU pVCpu = (PVMCPU)pvUser; 41 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;41 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 42 42 43 43 VMCPU_ASSERT_EMT(pVCpu); … … 62 62 { 63 63 PVMCPU pVCpu = (PVMCPU)pvUser; 64 void *pv = (uint8_t *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;64 void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister; 65 65 66 66 VMCPU_ASSERT_EMT(pVCpu); … … 115 115 * @interface_method_impl{DBGFREGDESC, pfnGet} 116 116 */ 117 static DECLCALLBACK(int) cpumR3RegGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 117 static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 118 { 119 PVMCPU pVCpu = (PVMCPU)pvUser; 120 VBOXGDTR const *pGdtr = (VBOXGDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); 121 122 VMCPU_ASSERT_EMT(pVCpu); 123 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); 124 125 pValue->dtr.u32Limit = pGdtr->cbGdt; 126 pValue->dtr.u64Base = pGdtr->pGdt; 127 return VINF_SUCCESS; 128 } 129 130 131 /** 132 * @interface_method_impl{DBGFREGDESC, pfnGet} 133 */ 134 static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 135 { 136 return VERR_NOT_IMPLEMENTED; 137 } 138 139 140 /** 141 * @interface_method_impl{DBGFREGDESC, pfnGet} 142 */ 143 static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 144 { 145 PVMCPU pVCpu = (PVMCPU)pvUser; 146 VBOXIDTR const *pIdtr = (VBOXIDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); 147 148 VMCPU_ASSERT_EMT(pVCpu); 149 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); 150 151 pValue->dtr.u32Limit = pIdtr->cbIdt; 152 pValue->dtr.u64Base = pIdtr->pIdt; 153 return VINF_SUCCESS; 154 } 155 156 157 /** 158 * @interface_method_impl{DBGFREGDESC, pfnGet} 159 */ 160 static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 161 { 162 return VERR_NOT_IMPLEMENTED; 163 } 164 165 166 /** 167 * Is the FPU state in FXSAVE format or not. 168 * 169 * @returns true if it is, false if it's in FNSAVE. 170 * @param pVCpu The virtual CPU handle. 171 */ 172 DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu) 173 { 174 #ifdef RT_ARCH_AMD64 175 return true; 176 #else 177 return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR; 178 #endif 179 } 180 181 182 /** 183 * Determins the tag register value for a CPU register when the FPU state 184 * format is FXSAVE. 185 * 186 * @returns The tag register value. 187 * @param pVCpu The virtual CPU handle. 188 * @param iReg The register number (0..7). 189 */ 190 DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg) 191 { 192 /* 193 * See table 11-1 in the AMD docs. 194 */ 195 if (!(pFpu->FTW & RT_BIT_32(iReg))) 196 return 3; /* b11 - empty */ 197 198 uint16_t const uExp = pFpu->aRegs[iReg].au16[4]; 199 if (uExp == 0) 200 { 201 if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */ 202 return 1; /* b01 - zero */ 203 return 2; /* b10 - special */ 204 } 205 206 if (uExp == UINT16_C(0xffff)) 207 return 2; /* b10 - special */ 208 209 if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */ 210 return 2; /* b10 - special */ 211 212 return 0; /* b00 - valid (normal) */ 213 } 214 215 216 /** 217 * @interface_method_impl{DBGFREGDESC, pfnGet} 218 */ 219 static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 220 { 221 PVMCPU pVCpu = (PVMCPU)pvUser; 222 PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); 223 224 VMCPU_ASSERT_EMT(pVCpu); 225 Assert(pDesc->enmType == DBGFREGVALTYPE_U16); 226 227 if (cpumR3RegIsFxSaveFormat(pVCpu)) 228 pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0) 229 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2) 230 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4) 231 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6) 232 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8) 233 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10) 234 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12) 235 | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14); 236 else 237 { 238 PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu; 239 pValue->u16 = pOldFpu->FTW; 240 } 241 return VINF_SUCCESS; 242 } 243 244 245 /** 246 * @interface_method_impl{DBGFREGDESC, pfnGet} 247 */ 248 static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 249 { 250 return VERR_DBGF_READ_ONLY_REGISTER; 251 } 252 253 254 255 /* 256 * 257 * Guest register access functions. 258 * 259 */ 260 261 /** 262 * @interface_method_impl{DBGFREGDESC, pfnGet} 263 */ 264 static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 118 265 { 119 266 PVMCPU pVCpu = (PVMCPU)pvUser; 120 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;267 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 121 268 122 269 VMCPU_ASSERT_EMT(pVCpu); … … 139 286 * @interface_method_impl{DBGFREGDESC, pfnGet} 140 287 */ 141 static DECLCALLBACK(int) cpumR3Reg Set_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)288 static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 142 289 { 143 290 int rc; 144 291 PVMCPU pVCpu = (PVMCPU)pvUser; 145 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;292 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 146 293 147 294 VMCPU_ASSERT_EMT(pVCpu); … … 197 344 * @interface_method_impl{DBGFREGDESC, pfnGet} 198 345 */ 199 static DECLCALLBACK(int) cpumR3RegG et_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)346 static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 200 347 { 201 348 PVMCPU pVCpu = (PVMCPU)pvUser; 202 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;349 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 203 350 204 351 VMCPU_ASSERT_EMT(pVCpu); … … 221 368 * @interface_method_impl{DBGFREGDESC, pfnGet} 222 369 */ 223 static DECLCALLBACK(int) cpumR3Reg Set_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)370 static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 224 371 { 225 372 int rc; 226 373 PVMCPU pVCpu = (PVMCPU)pvUser; 227 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;374 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 228 375 229 376 VMCPU_ASSERT_EMT(pVCpu); … … 269 416 * @interface_method_impl{DBGFREGDESC, pfnGet} 270 417 */ 271 static DECLCALLBACK(int) cpumR3RegG et_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)418 static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 272 419 { 273 420 PVMCPU pVCpu = (PVMCPU)pvUser; 274 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;421 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 275 422 276 423 VMCPU_ASSERT_EMT(pVCpu); … … 296 443 * @interface_method_impl{DBGFREGDESC, pfnGet} 297 444 */ 298 static DECLCALLBACK(int) cpumR3Reg Set_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)445 static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 299 446 { 300 447 int rc; 301 448 PVMCPU pVCpu = (PVMCPU)pvUser; 302 void const *pv = (uint8_t const *)&pVCpu->cpum .s.Guest+ pDesc->offRegister;449 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 303 450 304 451 VMCPU_ASSERT_EMT(pVCpu); … … 349 496 * @interface_method_impl{DBGFREGDESC, pfnGet} 350 497 */ 351 static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 352 { 353 PVMCPU pVCpu = (PVMCPU)pvUser; 354 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; 355 356 VMCPU_ASSERT_EMT(pVCpu); 357 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); 358 359 pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.gdtr.cbGdt; 360 pValue->dtr.u64Base = pVCpu->cpum.s.Guest.gdtr.pGdt; 361 return VINF_SUCCESS; 362 } 363 364 365 /** 366 * @interface_method_impl{DBGFREGDESC, pfnGet} 367 */ 368 static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 369 { 370 return VERR_NOT_IMPLEMENTED; 371 } 372 373 374 /** 375 * @interface_method_impl{DBGFREGDESC, pfnGet} 376 */ 377 static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 378 { 379 PVMCPU pVCpu = (PVMCPU)pvUser; 380 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; 381 382 VMCPU_ASSERT_EMT(pVCpu); 383 Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); 384 385 pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.idtr.cbIdt; 386 pValue->dtr.u64Base = pVCpu->cpum.s.Guest.idtr.pIdt; 387 return VINF_SUCCESS; 388 } 389 390 391 /** 392 * @interface_method_impl{DBGFREGDESC, pfnGet} 393 */ 394 static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 395 { 396 return VERR_NOT_IMPLEMENTED; 397 } 398 399 400 /** 401 * Is the FPU state in FXSAVE format or not. 402 * 403 * @returns true if it is, false if it's in FNSAVE. 404 * @param pVCpu The virtual CPU handle. 405 */ 406 DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu) 407 { 408 #ifdef RT_ARCH_AMD64 409 return true; 410 #else 411 return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR; 412 #endif 413 } 414 415 416 /** 417 * Determins the tag register value for a CPU register when the FPU state 418 * format is FXSAVE. 419 * 420 * @returns The tag register value. 421 * @param pVCpu The virtual CPU handle. 422 * @param iReg The register number (0..7). 423 */ 424 DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PVMCPU pVCpu, unsigned iReg) 425 { 426 /* 427 * See table 11-1 in the AMD docs. 428 */ 429 if (!(pVCpu->cpum.s.Guest.fpu.FTW & RT_BIT_32(iReg))) 430 return 3; /* b11 - empty */ 431 432 uint16_t const uExp = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au16[4]; 433 if (uExp == 0) 434 { 435 if (pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] == 0) /* J & M == 0 */ 436 return 1; /* b01 - zero */ 437 return 2; /* b10 - special */ 438 } 439 440 if (uExp == UINT16_C(0xffff)) 441 return 2; /* b10 - special */ 442 443 if (!(pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] >> 63)) /* J == 0 */ 444 return 2; /* b10 - special */ 445 446 return 0; /* b00 - valid (normal) */ 447 } 448 449 450 /** 451 * @interface_method_impl{DBGFREGDESC, pfnGet} 452 */ 453 static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 454 { 455 PVMCPU pVCpu = (PVMCPU)pvUser; 456 void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; 457 458 VMCPU_ASSERT_EMT(pVCpu); 459 Assert(pDesc->enmType == DBGFREGVALTYPE_U16); 460 461 if (cpumR3RegIsFxSaveFormat(pVCpu)) 462 pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pVCpu, 0) 463 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 1) << 2) 464 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 2) << 4) 465 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 3) << 6) 466 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 4) << 8) 467 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 5) << 10) 468 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 6) << 12) 469 | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 7) << 14); 470 else 471 { 472 PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; 473 pValue->u16 = pOldFpu->FTW; 474 } 475 return VINF_SUCCESS; 476 } 477 478 479 /** 480 * @interface_method_impl{DBGFREGDESC, pfnGet} 481 */ 482 static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 483 { 484 return VERR_DBGF_READ_ONLY_REGISTER; 485 } 486 487 488 /** 489 * @interface_method_impl{DBGFREGDESC, pfnGet} 490 */ 491 static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 498 static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 492 499 { 493 500 PVMCPU pVCpu = (PVMCPU)pvUser; … … 518 525 } 519 526 520 /** 521 * @interface_method_impl{DBGFREGDESC, pfnGet} 522 */ 523 static DECLCALLBACK(int) cpumR3RegSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 527 528 /** 529 * @interface_method_impl{DBGFREGDESC, pfnGet} 530 */ 531 static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 524 532 { 525 533 return VERR_NOT_IMPLEMENTED; 526 534 } 535 536 537 538 /* 539 * 540 * Hypervisor register access functions. 541 * 542 */ 543 544 /** 545 * @interface_method_impl{DBGFREGDESC, pfnGet} 546 */ 547 static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 548 { 549 PVMCPU pVCpu = (PVMCPU)pvUser; 550 VMCPU_ASSERT_EMT(pVCpu); 551 552 uint64_t u64Value; 553 switch (pDesc->offRegister) 554 { 555 case 0: u64Value = UINT64_MAX; break; 556 case 2: u64Value = UINT64_MAX; break; 557 case 3: u64Value = CPUMGetHyperCR3(pVCpu); break; 558 case 4: u64Value = UINT64_MAX; break; 559 case 8: u64Value = UINT64_MAX; break; 560 default: 561 AssertFailedReturn(VERR_INTERNAL_ERROR_3); 562 } 563 switch (pDesc->enmType) 564 { 565 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; 566 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; 567 default: 568 AssertFailedReturn(VERR_INTERNAL_ERROR_4); 569 } 570 return VINF_SUCCESS; 571 } 572 573 574 /** 575 * @interface_method_impl{DBGFREGDESC, pfnGet} 576 */ 577 static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 578 { 579 /* Not settable, prevents killing your host. */ 580 return VERR_ACCESS_DENIED; 581 } 582 583 584 /** 585 * @interface_method_impl{DBGFREGDESC, pfnGet} 586 */ 587 static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 588 { 589 PVMCPU pVCpu = (PVMCPU)pvUser; 590 void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; 591 592 VMCPU_ASSERT_EMT(pVCpu); 593 594 uint64_t u64Value; 595 switch (pDesc->offRegister) 596 { 597 case 0: u64Value = CPUMGetHyperDR0(pVCpu); break; 598 case 1: u64Value = CPUMGetHyperDR1(pVCpu); break; 599 case 2: u64Value = CPUMGetHyperDR2(pVCpu); break; 600 case 3: u64Value = CPUMGetHyperDR3(pVCpu); break; 601 case 6: u64Value = CPUMGetHyperDR6(pVCpu); break; 602 case 7: u64Value = CPUMGetHyperDR7(pVCpu); break; 603 default: 604 AssertFailedReturn(VERR_INTERNAL_ERROR_3); 605 } 606 switch (pDesc->enmType) 607 { 608 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; 609 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; 610 default: 611 AssertFailedReturn(VERR_INTERNAL_ERROR_4); 612 } 613 return VINF_SUCCESS; 614 } 615 616 617 /** 618 * @interface_method_impl{DBGFREGDESC, pfnGet} 619 */ 620 static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 621 { 622 /* Not settable, prevents killing your host. */ 623 return VERR_ACCESS_DENIED; 624 } 625 626 627 /** 628 * @interface_method_impl{DBGFREGDESC, pfnGet} 629 */ 630 static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 631 { 632 /* Not availble at present, return all FFs to keep things quiet */ 633 uint64_t u64Value = UINT64_MAX; 634 switch (pDesc->enmType) 635 { 636 case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; 637 case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; 638 case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break; 639 default: 640 AssertFailedReturn(VERR_INTERNAL_ERROR_4); 641 } 642 return VINF_SUCCESS; 643 } 644 645 646 /** 647 * @interface_method_impl{DBGFREGDESC, pfnGet} 648 */ 649 static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 650 { 651 /* Not settable, return failure. */ 652 NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask); 653 return VERR_ACCESS_DENIED; 654 } 655 656 657 /** 658 * @interface_method_impl{DBGFREGDESC, pfnGet} 659 */ 660 static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 661 { 662 PVMCPU pVCpu = (PVMCPU)pvUser; 663 664 VMCPU_ASSERT_EMT(pVCpu); 665 Assert(pDesc->enmType == DBGFREGVALTYPE_R80); 666 667 if (cpumR3RegIsFxSaveFormat(pVCpu)) 668 { 669 unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7; 670 iReg += pDesc->offRegister; 671 iReg &= 7; 672 pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80; 673 } 674 else 675 { 676 PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; 677 678 unsigned iReg = (pOldFpu->FSW >> 11) & 7; 679 iReg += pDesc->offRegister; 680 iReg &= 7; 681 682 pValue->r80 = pOldFpu->regs[iReg].r80; 683 } 684 685 return VINF_SUCCESS; 686 } 687 688 689 /** 690 * @interface_method_impl{DBGFREGDESC, pfnGet} 691 */ 692 static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 693 { 694 /* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */ 695 return VERR_ACCESS_DENIED; 696 } 697 527 698 528 699 … … 831 1002 832 1003 833 834 /** 835 * The register descriptors. 836 */ 837 static DBGFREGDESC const g_aCpumRegDescs[] = 838 { 839 #define CPUMREGDESC_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 840 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 841 #define CPUMREGDESC_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 842 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 843 #define CPUMREGDESC_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 844 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 845 846 #define CPUMREGDESC_REG(UName, LName) \ 847 CPUMREGDESC_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL) 848 CPUMREGDESC_REG(RAX, rax), 849 CPUMREGDESC_REG(RCX, rcx), 850 CPUMREGDESC_REG(RDX, rdx), 851 CPUMREGDESC_REG(RBX, rbx), 852 CPUMREGDESC_REG(RSP, rsp), 853 CPUMREGDESC_REG(RBP, rbp), 854 CPUMREGDESC_REG(RSI, rsi), 855 CPUMREGDESC_REG(RDI, rdi), 856 CPUMREGDESC_REG(R8, r8), 857 CPUMREGDESC_REG(R9, r9), 858 CPUMREGDESC_REG(R10, r10), 859 CPUMREGDESC_REG(R11, r11), 860 CPUMREGDESC_REG(R12, r12), 861 CPUMREGDESC_REG(R13, r13), 862 CPUMREGDESC_REG(R14, r14), 863 CPUMREGDESC_REG(R15, r15), 864 #define CPUMREGDESC_SEG(UName, LName) \ 865 CPUMREGDESC_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \ 866 CPUMREGDESC_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \ 867 CPUMREGDESC_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \ 868 CPUMREGDESC_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ) 869 CPUMREGDESC_SEG(CS, cs), 870 CPUMREGDESC_SEG(DS, ds), 871 CPUMREGDESC_SEG(ES, es), 872 CPUMREGDESC_SEG(FS, fs), 873 CPUMREGDESC_SEG(GS, gs), 874 CPUMREGDESC_SEG(SS, ss), 875 CPUMREGDESC_REG(RIP, rip), 876 CPUMREGDESC_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), 877 CPUMREGDESC_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), 878 CPUMREGDESC_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), 879 CPUMREGDESC_RO_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), 880 CPUMREGDESC_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 881 CPUMREGDESC_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), 882 CPUMREGDESC_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 883 CPUMREGDESC_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), 884 CPUMREGDESC_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 885 CPUMREGDESC_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 886 CPUMREGDESC_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 887 #define CPUMREGDESC_ST(n) \ 888 CPUMREGDESC_RW_AS("st" #n, ST##n, R80, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN ) 889 CPUMREGDESC_ST(0), 890 CPUMREGDESC_ST(1), 891 CPUMREGDESC_ST(2), 892 CPUMREGDESC_ST(3), 893 CPUMREGDESC_ST(4), 894 CPUMREGDESC_ST(5), 895 CPUMREGDESC_ST(6), 896 CPUMREGDESC_ST(7), 897 #define CPUMREGDESC_MM(n) \ 898 CPUMREGDESC_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN ) 899 CPUMREGDESC_MM(0), 900 CPUMREGDESC_MM(1), 901 CPUMREGDESC_MM(2), 902 CPUMREGDESC_MM(3), 903 CPUMREGDESC_MM(4), 904 CPUMREGDESC_MM(5), 905 CPUMREGDESC_MM(6), 906 CPUMREGDESC_MM(7), 907 #define CPUMREGDESC_XMM(n) \ 908 CPUMREGDESC_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN ) 909 CPUMREGDESC_XMM(0), 910 CPUMREGDESC_XMM(1), 911 CPUMREGDESC_XMM(2), 912 CPUMREGDESC_XMM(3), 913 CPUMREGDESC_XMM(4), 914 CPUMREGDESC_XMM(5), 915 CPUMREGDESC_XMM(6), 916 CPUMREGDESC_XMM(7), 917 CPUMREGDESC_XMM(8), 918 CPUMREGDESC_XMM(9), 919 CPUMREGDESC_XMM(10), 920 CPUMREGDESC_XMM(11), 921 CPUMREGDESC_XMM(12), 922 CPUMREGDESC_XMM(13), 923 CPUMREGDESC_XMM(14), 924 CPUMREGDESC_XMM(15), 925 CPUMREGDESC_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 926 CPUMREGDESC_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 927 CPUMREGDESC_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 928 CPUMREGDESC_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 929 CPUMREGDESC_SEG(LDTR, ldtr), 930 CPUMREGDESC_SEG(TR, tr), 931 CPUMREGDESC_EX_AS("cr0", CR0, U32, 0, cpumR3RegGet_crX, cpumR3RegSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), 932 CPUMREGDESC_EX_AS("cr2", CR2, U64, 2, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ), 933 CPUMREGDESC_EX_AS("cr3", CR3, U64, 3, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr3 ), 934 CPUMREGDESC_EX_AS("cr4", CR4, U32, 4, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr4 ), 935 CPUMREGDESC_EX_AS("cr8", CR8, U32, 8, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ), 936 CPUMREGDESC_EX_AS("dr0", DR0, U64, 0, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), 937 CPUMREGDESC_EX_AS("dr1", DR1, U64, 1, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), 938 CPUMREGDESC_EX_AS("dr2", DR2, U64, 2, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), 939 CPUMREGDESC_EX_AS("dr3", DR3, U64, 3, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), 940 CPUMREGDESC_EX_AS("dr6", DR6, U32, 6, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr6 ), 941 CPUMREGDESC_EX_AS("dr7", DR7, U32, 7, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr7 ), 942 #define CPUMREGDESC_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ 943 CPUMREGDESC_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, a_paSubFields ) 944 CPUMREGDESC_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), 945 CPUMREGDESC_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), 946 CPUMREGDESC_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), 947 CPUMREGDESC_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), 948 CPUMREGDESC_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), 949 CPUMREGDESC_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), 950 CPUMREGDESC_MSR("tsc", IA32_TSC, U32, NULL ), 951 CPUMREGDESC_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), 952 CPUMREGDESC_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), 953 CPUMREGDESC_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), 954 CPUMREGDESC_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), 955 CPUMREGDESC_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), 956 CPUMREGDESC_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), 957 CPUMREGDESC_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), 958 CPUMREGDESC_MSR("sf_mask", K8_SF_MASK, U64, NULL ), 959 CPUMREGDESC_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), 960 CPUMREGDESC_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCTX, rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 961 CPUMREGDESC_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 962 CPUMREGDESC_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 963 CPUMREGDESC_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 964 CPUMREGDESC_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), 965 CPUMREGDESC_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), 1004 /** @name Macros for producing register descriptor table entries. 1005 * @{ */ 1006 #define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 1007 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 1008 1009 #define CPU_REG_REG(UName, LName) \ 1010 CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL) 1011 1012 #define CPU_REG_SEG(UName, LName) \ 1013 CPU_REG_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \ 1014 CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \ 1015 CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \ 1016 CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ) 1017 1018 #define CPU_REG_MM(n) \ 1019 CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN) 1020 1021 #define CPU_REG_XMM(n) \ 1022 CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN) 1023 /** @} */ 1024 1025 1026 /** 1027 * The guest register descriptors. 1028 */ 1029 static DBGFREGDESC const g_aCpumRegGstDescs[] = 1030 { 1031 #define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 1032 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 1033 #define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 1034 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 1035 #define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ 1036 CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields) 1037 #define CPU_REG_ST(n) \ 1038 CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN) 1039 1040 CPU_REG_REG(RAX, rax), 1041 CPU_REG_REG(RCX, rcx), 1042 CPU_REG_REG(RDX, rdx), 1043 CPU_REG_REG(RBX, rbx), 1044 CPU_REG_REG(RSP, rsp), 1045 CPU_REG_REG(RBP, rbp), 1046 CPU_REG_REG(RSI, rsi), 1047 CPU_REG_REG(RDI, rdi), 1048 CPU_REG_REG(R8, r8), 1049 CPU_REG_REG(R9, r9), 1050 CPU_REG_REG(R10, r10), 1051 CPU_REG_REG(R11, r11), 1052 CPU_REG_REG(R12, r12), 1053 CPU_REG_REG(R13, r13), 1054 CPU_REG_REG(R14, r14), 1055 CPU_REG_REG(R15, r15), 1056 CPU_REG_SEG(CS, cs), 1057 CPU_REG_SEG(DS, ds), 1058 CPU_REG_SEG(ES, es), 1059 CPU_REG_SEG(FS, fs), 1060 CPU_REG_SEG(GS, gs), 1061 CPU_REG_SEG(SS, ss), 1062 CPU_REG_REG(RIP, rip), 1063 CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), 1064 CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), 1065 CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), 1066 CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), 1067 CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1068 CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), 1069 CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1070 CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), 1071 CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1072 CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 1073 CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 1074 CPU_REG_ST(0), 1075 CPU_REG_ST(1), 1076 CPU_REG_ST(2), 1077 CPU_REG_ST(3), 1078 CPU_REG_ST(4), 1079 CPU_REG_ST(5), 1080 CPU_REG_ST(6), 1081 CPU_REG_ST(7), 1082 CPU_REG_MM(0), 1083 CPU_REG_MM(1), 1084 CPU_REG_MM(2), 1085 CPU_REG_MM(3), 1086 CPU_REG_MM(4), 1087 CPU_REG_MM(5), 1088 CPU_REG_MM(6), 1089 CPU_REG_MM(7), 1090 CPU_REG_XMM(0), 1091 CPU_REG_XMM(1), 1092 CPU_REG_XMM(2), 1093 CPU_REG_XMM(3), 1094 CPU_REG_XMM(4), 1095 CPU_REG_XMM(5), 1096 CPU_REG_XMM(6), 1097 CPU_REG_XMM(7), 1098 CPU_REG_XMM(8), 1099 CPU_REG_XMM(9), 1100 CPU_REG_XMM(10), 1101 CPU_REG_XMM(11), 1102 CPU_REG_XMM(12), 1103 CPU_REG_XMM(13), 1104 CPU_REG_XMM(14), 1105 CPU_REG_XMM(15), 1106 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1107 CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1108 CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1109 CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1110 CPU_REG_SEG(LDTR, ldtr), 1111 CPU_REG_SEG(TR, tr), 1112 CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), 1113 CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ), 1114 CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ), 1115 CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ), 1116 CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ), 1117 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), 1118 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), 1119 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), 1120 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), 1121 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ), 1122 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ), 1123 CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), 1124 CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), 1125 CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), 1126 CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), 1127 CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), 1128 CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), 1129 CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ), 1130 CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), 1131 CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), 1132 CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), 1133 CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), 1134 CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), 1135 CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), 1136 CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), 1137 CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ), 1138 CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), 1139 CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1140 CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1141 CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1142 CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1143 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), 1144 CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), 966 1145 DBGFREGDESC_TERMINATOR() 967 #undef CPUMREGDESC_REG 968 #undef CPUMREGDESC_SEG 969 #undef CPUMREGDESC_ST 970 #undef CPUMREGDESC_MM 971 #undef CPUMREGDESC_XMM 972 #undef CPUMREGDESC_MSR 1146 1147 #undef CPU_REG_RW_AS 1148 #undef CPU_REG_RO_AS 1149 #undef CPU_REG_MSR 1150 #undef CPU_REG_ST 1151 }; 1152 1153 1154 /** 1155 * The hypervisor (raw-mode) register descriptors. 1156 */ 1157 static DBGFREGDESC const g_aCpumRegHyperDescs[] = 1158 { 1159 #define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 1160 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 1161 #define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ 1162 { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } 1163 #define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ 1164 CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields) 1165 #define CPU_REG_ST(n) \ 1166 CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN) 1167 1168 CPU_REG_REG(RAX, rax), 1169 CPU_REG_REG(RCX, rcx), 1170 CPU_REG_REG(RDX, rdx), 1171 CPU_REG_REG(RBX, rbx), 1172 CPU_REG_REG(RSP, rsp), 1173 CPU_REG_REG(RBP, rbp), 1174 CPU_REG_REG(RSI, rsi), 1175 CPU_REG_REG(RDI, rdi), 1176 CPU_REG_REG(R8, r8), 1177 CPU_REG_REG(R9, r9), 1178 CPU_REG_REG(R10, r10), 1179 CPU_REG_REG(R11, r11), 1180 CPU_REG_REG(R12, r12), 1181 CPU_REG_REG(R13, r13), 1182 CPU_REG_REG(R14, r14), 1183 CPU_REG_REG(R15, r15), 1184 CPU_REG_SEG(CS, cs), 1185 CPU_REG_SEG(DS, ds), 1186 CPU_REG_SEG(ES, es), 1187 CPU_REG_SEG(FS, fs), 1188 CPU_REG_SEG(GS, gs), 1189 CPU_REG_SEG(SS, ss), 1190 CPU_REG_REG(RIP, rip), 1191 CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), 1192 CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), 1193 CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), 1194 CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), 1195 CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1196 CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), 1197 CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1198 CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), 1199 CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1200 CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 1201 CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), 1202 CPU_REG_ST(0), 1203 CPU_REG_ST(1), 1204 CPU_REG_ST(2), 1205 CPU_REG_ST(3), 1206 CPU_REG_ST(4), 1207 CPU_REG_ST(5), 1208 CPU_REG_ST(6), 1209 CPU_REG_ST(7), 1210 CPU_REG_MM(0), 1211 CPU_REG_MM(1), 1212 CPU_REG_MM(2), 1213 CPU_REG_MM(3), 1214 CPU_REG_MM(4), 1215 CPU_REG_MM(5), 1216 CPU_REG_MM(6), 1217 CPU_REG_MM(7), 1218 CPU_REG_XMM(0), 1219 CPU_REG_XMM(1), 1220 CPU_REG_XMM(2), 1221 CPU_REG_XMM(3), 1222 CPU_REG_XMM(4), 1223 CPU_REG_XMM(5), 1224 CPU_REG_XMM(6), 1225 CPU_REG_XMM(7), 1226 CPU_REG_XMM(8), 1227 CPU_REG_XMM(9), 1228 CPU_REG_XMM(10), 1229 CPU_REG_XMM(11), 1230 CPU_REG_XMM(12), 1231 CPU_REG_XMM(13), 1232 CPU_REG_XMM(14), 1233 CPU_REG_XMM(15), 1234 CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1235 CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1236 CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1237 CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1238 CPU_REG_SEG(LDTR, ldtr), 1239 CPU_REG_SEG(TR, tr), 1240 CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), 1241 CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ), 1242 CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ), 1243 CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ), 1244 CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ), 1245 CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), 1246 CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), 1247 CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), 1248 CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), 1249 CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ), 1250 CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ), 1251 CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), 1252 CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), 1253 CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), 1254 CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), 1255 CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), 1256 CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), 1257 CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ), 1258 CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), 1259 CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), 1260 CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), 1261 CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), 1262 CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), 1263 CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), 1264 CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), 1265 CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ), 1266 CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), 1267 CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1268 CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1269 CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1270 CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), 1271 CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), 1272 CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), 1273 DBGFREGDESC_TERMINATOR() 1274 #undef CPU_REG_RW_AS 1275 #undef CPU_REG_RO_AS 1276 #undef CPU_REG_MSR 1277 #undef CPU_REG_ST 973 1278 }; 974 1279 … … 986 1291 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) 987 1292 { 988 int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumReg Descs);1293 int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/); 989 1294 AssertLogRelRCReturn(rc, rc); 1295 rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /*fGuestRegs*/); 1296 AssertLogRelRCReturn(rc, rc); 990 1297 } 991 1298 -
trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp
r35590 r35601 268 268 * pszPrefix when creating the set name. 269 269 */ 270 static int dbgfR3RegRegisterCommon(PVM pVM, PCDBGFREGDESC paRegisters, DBGFREGSETTYPE enmType, void *pvUserArg, const char *pszPrefix, uint32_t iInstance) 270 static int dbgfR3RegRegisterCommon(PVM pVM, PCDBGFREGDESC paRegisters, DBGFREGSETTYPE enmType, void *pvUserArg, 271 const char *pszPrefix, uint32_t iInstance) 271 272 { 272 273 /* … … 457 458 if (pRegSet->cDescs > DBGFREG_ALL_COUNT) 458 459 pVM->dbgf.s.cRegs -= pRegSet->cDescs - DBGFREG_ALL_COUNT; 459 pVM->aCpus[iInstance].dbgf.s.pRegSet = pRegSet; 460 if (!strcmp(pszPrefix, "cpu")) 461 pVM->aCpus[iInstance].dbgf.s.pGuestRegSet = pRegSet; 462 else 463 pVM->aCpus[iInstance].dbgf.s.pHyperRegSet = pRegSet; 460 464 } 461 465 … … 494 498 * @param pVCpu The virtual CPU handle. 495 499 * @param paRegisters The register descriptors. 496 */ 497 VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters) 500 * @param fGuestRegs Set if it's the guest registers, clear if 501 * hypervisor registers. 502 */ 503 VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters, bool fGuestRegs) 498 504 { 499 505 if (!pVM->dbgf.s.fRegDbInitialized) … … 504 510 } 505 511 506 return dbgfR3RegRegisterCommon(pVM, paRegisters, DBGFREGSETTYPE_CPU, pVCpu, "cpu", pVCpu->idCpu);512 return dbgfR3RegRegisterCommon(pVM, paRegisters, DBGFREGSETTYPE_CPU, pVCpu, fGuestRegs ? "cpu" : "hypercpu", pVCpu->idCpu); 507 513 } 508 514 … … 788 794 * Look up the register set of the specified CPU. 789 795 */ 790 PDBGFREGSET pSet = pVM->aCpus[idCpu].dbgf.s.p RegSet;796 PDBGFREGSET pSet = pVM->aCpus[idCpu].dbgf.s.pGuestRegSet; 791 797 if (RT_LIKELY(pSet)) 792 798 { … … 1128 1134 VM_ASSERT_VALID_EXT_RETURN(pVM, NULL); 1129 1135 1130 PCDBGFREGSET pSet = pVM->aCpus[0].dbgf.s.p RegSet;1136 PCDBGFREGSET pSet = pVM->aCpus[0].dbgf.s.pGuestRegSet; 1131 1137 if (RT_UNLIKELY(!pSet)) 1132 1138 return NULL; … … 1726 1732 1727 1733 /* 1728 * My CPU registers.1734 * My guest CPU registers. 1729 1735 */ 1730 1736 size_t iCpuReg = pVCpu->idCpu * DBGFREG_ALL_COUNT; 1731 if (pVCpu->dbgf.s.p RegSet)1737 if (pVCpu->dbgf.s.pGuestRegSet) 1732 1738 { 1733 1739 if (iCpuReg < cRegs) 1734 dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.p RegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg);1740 dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.pGuestRegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg); 1735 1741 } 1736 1742 else … … 1738 1744 1739 1745 /* 1746 * My hypervisor CPU registers. 1747 */ 1748 iCpuReg = pVM->cCpus * DBGFREG_ALL_COUNT + pVCpu->idCpu * DBGFREG_ALL_COUNT; 1749 if (pVCpu->dbgf.s.pHyperRegSet) 1750 { 1751 if (iCpuReg < cRegs) 1752 dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.pHyperRegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg); 1753 } 1754 else 1755 dbgfR3RegNmQueryAllPadEntries(paRegs, cRegs, iCpuReg, DBGFREG_ALL_COUNT); 1756 1757 /* 1740 1758 * The primary CPU does all the other registers. 1741 1759 */ 1742 1760 if (pVCpu->idCpu == 0) 1743 1761 { 1744 pArgs->iReg = pVM->cCpus * DBGFREG_ALL_COUNT ;1762 pArgs->iReg = pVM->cCpus * DBGFREG_ALL_COUNT * 2; 1745 1763 RTStrSpaceEnumerate(&pVM->dbgf.s.RegSetSpace, dbgfR3RegNmQueryAllEnum, pArgs); 1746 1764 dbgfR3RegNmQueryAllPadEntries(paRegs, cRegs, pArgs->iReg, cRegs); -
trunk/src/VBox/VMM/include/DBGFInternal.h
r35550 r35601 321 321 bool afReserved[7]; 322 322 323 /** The register set for this CPU. Can be NULL. */ 324 R3PTRTYPE(struct DBGFREGSET *) pRegSet; 323 /** The guest register set for this CPU. Can be NULL. */ 324 R3PTRTYPE(struct DBGFREGSET *) pGuestRegSet; 325 /** The hypervisor register set for this CPU. Can be NULL. */ 326 R3PTRTYPE(struct DBGFREGSET *) pHyperRegSet; 325 327 } DBGFCPU; 326 328 /** Pointer to DBGFCPU data. */ -
trunk/src/VBox/VMM/testcase/tstVMStructRC.cpp
r35466 r35601 134 134 GEN_CHECK_OFF(DBGFCPU, iActiveBp); 135 135 GEN_CHECK_OFF(DBGFCPU, fSingleSteppingRaw); 136 GEN_CHECK_OFF(DBGFCPU, pRegSet); 136 GEN_CHECK_OFF(DBGFCPU, pGuestRegSet); 137 GEN_CHECK_OFF(DBGFCPU, pHyperRegSet); 137 138 138 139 GEN_CHECK_SIZE(EM);
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