Changeset 36092 in vbox for trunk/src/VBox/Devices/Bus
- Timestamp:
- Feb 26, 2011 9:07:51 PM (14 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r36079 r36092 96 96 PCIBUS aPciBus; 97 97 98 99 98 /** I/O APIC irq levels */ 100 99 volatile uint32_t uaPciApicIrqLevels[PCI_APIC_IRQ_PINS]; … … 183 182 static DECLCALLBACK(uint32_t) ich9pciConfigReadDev(PCIDevice *aDev, uint32_t u32Address, unsigned len); 184 183 DECLINLINE(PPCIDEVICE) ich9pciFindBridge(PPCIBUS pBus, uint8_t iBus); 185 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn , uint8_t cBridgeDepth, uint8_t *paBridgePositions);184 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn); 186 185 #endif 187 186 … … 697 696 * If the target bus is in the range we pass the request on to the bridge. 698 697 */ 699 PPCIDEVICE pBridge Temp= pBus->papBridgesR3[iBridge];700 AssertMsg(pBridge Temp && pciDevIsPci2PciBridge(pBridgeTemp),698 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge]; 699 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge), 701 700 ("Device is not a PCI bridge but on the list of PCI bridges\n")); 702 703 if ( iBus >= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SECONDARY_BUS) 704 && iBus <= PCIDevGetByte(pBridgeTemp, VBOX_PCI_SUBORDINATE_BUS)) 705 return pBridgeTemp; 701 uint32_t uSecondary = PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS); 702 uint32_t uSubordinate = PCIDevGetByte(pBridge, VBOX_PCI_SUBORDINATE_BUS); 703 Log2(("ich9pciFindBridge on bus %p, bridge %d: %d in %d..%d\n", pBus, iBridge, iBus, uSecondary, uSubordinate)); 704 if (iBus >= uSecondary && iBus <= uSubordinate) 705 return pBridge; 706 706 } 707 707 … … 1529 1529 1530 1530 1531 static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions) 1532 { 1533 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus, 1); 1534 /* Temporary until we know how many other bridges are behind this one. */ 1535 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff, 1); 1536 1537 /* Add position of this bridge into the array. */ 1538 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3); 1531 static void ich9pciBiosInitBridge(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn) 1532 { 1533 Log(("BIOS init device: %0x2::%02x.%d\n", uBus, uDevFn >> 3, uDevFn & 7)); 1539 1534 1540 1535 /* … … 1564 1559 /* Init devices behind the bridge and possibly other bridges as well. */ 1565 1560 for (int iDev = 0; iDev <= 255; iDev++) 1566 ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions); 1567 1568 /* The number of bridges behind the this one is now available. */ 1569 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus, 1); 1561 ich9pciBiosInitDevice(pGlobals, uBus + 1, iDev); 1570 1562 1571 1563 /* … … 1602 1594 } 1603 1595 1604 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn , uint8_t cBridgeDepth, uint8_t *paBridgePositions)1596 static void ich9pciBiosInitDevice(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn) 1605 1597 { 1606 1598 uint32_t *paddr; … … 1643 1635 case 0x0604: 1644 1636 /* PCI-to-PCI bridge. */ 1645 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus, 1);1646 1647 1637 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n")); 1648 pGlobals->uBus++; 1649 ich9pciBiosInitBridge(pGlobals, uBus, uDevFn, cBridgeDepth, paBridgePositions); 1638 ich9pciBiosInitBridge(pGlobals, uBus, uDevFn); 1650 1639 break; 1651 1640 default: … … 1701 1690 if (iPin != 0) 1702 1691 { 1703 uint8_t uBridgeDevFn = uDevFn;1704 1692 iPin--; 1705 1693 1706 /* We need to go up to the host bus to see which irq this device will assert there. */ 1707 while (cBridgeDepth != 0) 1708 { 1709 /* Get the pin the device would assert on the bridge. */ 1710 iPin = ((uBridgeDevFn >> 3) + iPin) & 3; 1711 uBridgeDevFn = paBridgePositions[cBridgeDepth]; 1712 cBridgeDepth--; 1694 if (uBus != 0) 1695 { 1696 /* Find bus this device attached to. */ 1697 PPCIBUS pBus = &pGlobals->aPciBus; 1698 while (1) 1699 { 1700 PPCIDEVICE pBridge = ich9pciFindBridge(pBus, uBus); 1701 if (!pBridge) 1702 { 1703 Assert(false); 1704 break; 1705 } 1706 if (uBus == PCIDevGetByte(pBridge, VBOX_PCI_SECONDARY_BUS)) 1707 { 1708 /* OK, found bus this device attached to. */ 1709 break; 1710 } 1711 pBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS); 1712 } 1713 1714 /* We need to go up to the host bus to see which irq pin this 1715 * device will use there. See logic in ich9pcibridgeSetIrq(). 1716 */ 1717 while (pBus->iBus != 0) 1718 { 1719 /* Get the pin the device would assert on the bridge. */ 1720 iPin = ((pBus->aPciDev.devfn >> 3) + iPin) & 3; 1721 pBus = pBus->aPciDev.Int.s.pBusR3; 1722 }; 1713 1723 } 1714 1724 1715 1725 int iIrq = aPciIrqs[ich9pciSlotGetPirq(uBus, uDevFn, iPin)]; 1726 Log(("Using pin %d and IRQ %d for device %02x:%02x.%d\n", 1727 iPin, iIrq, uBus, uDevFn>>3, uDevFn&7)); 1716 1728 ich9pciConfigWrite(pGlobals, uBus, uDevFn, VBOX_PCI_INTERRUPT_LINE, iIrq, 1); 1717 1729 } 1718 1730 } 1731 1732 /* Initializes bridges registers used for routing. */ 1733 static void ich9pciInitBridgeTopology(PPCIGLOBALS pGlobals, PPCIBUS pBus) 1734 { 1735 PPCIDEVICE pBridgeDev = &pBus->aPciDev; 1736 PCIDevSetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS, pGlobals->uBus); 1737 1738 /* For simplicity, let's start numbering PCI bridges from 0, 1739 * not 1, so don't increment count on Host->PCI bridge. 1740 */ 1741 if (strcmp(pBridgeDev->name, "i82801") != 0) 1742 pGlobals->uBus++; 1743 1744 PCIDevSetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus); 1745 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++) 1746 { 1747 PPCIDEVICE pBridge = pBus->papBridgesR3[iBridge]; 1748 AssertMsg(pBridge && pciDevIsPci2PciBridge(pBridge), 1749 ("Device is not a PCI bridge but on the list of PCI bridges\n")); 1750 PPCIBUS pChildBus = PDMINS_2_DATA(pBridge->pDevIns, PPCIBUS); 1751 ich9pciInitBridgeTopology(pGlobals, pChildBus); 1752 } 1753 PCIDevSetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus); 1754 Log2(("ich9pciInitBridgeTopology: for bus %p: primary=%d secondary=%d subordinate=%d\n", 1755 pBus, 1756 PCIDevGetByte(pBridgeDev, VBOX_PCI_PRIMARY_BUS), 1757 PCIDevGetByte(pBridgeDev, VBOX_PCI_SECONDARY_BUS), 1758 PCIDevGetByte(pBridgeDev, VBOX_PCI_SUBORDINATE_BUS) 1759 )); 1760 } 1761 1719 1762 1720 1763 static DECLCALLBACK(int) ich9pciFakePCIBIOS(PPDMDEVINS pDevIns) … … 1733 1776 pGlobals->uBus = 0; 1734 1777 1735 /* 1778 /** 1779 * Assign bridge topology, for further routing to work. 1780 */ 1781 PPCIBUS pBus = &pGlobals->aPciBus; 1782 ich9pciInitBridgeTopology(pGlobals, pBus); 1783 1784 /** 1736 1785 * Init the devices. 1737 1786 */ 1738 1787 for (i = 0; i < 256; i++) 1739 1788 { 1740 uint8_t aBridgePositions[256]; 1741 1742 memset(aBridgePositions, 0, sizeof(aBridgePositions)); 1743 Log2(("PCI: Initializing device %d (%#x)\n", 1744 i, 0x80000000 | (i << 8))); 1745 ich9pciBiosInitDevice(pGlobals, 0, i, 0, aBridgePositions); 1789 ich9pciBiosInitDevice(pGlobals, 0, i); 1746 1790 } 1747 1791 … … 2128 2172 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite, 2129 2173 ("device is a bridge but does not implement read/write functions\n")); 2174 Log2(("Setting bridge %d on bus %p\n", pBus->cBridges, pBus)); 2130 2175 pBus->papBridgesR3[pBus->cBridges] = pPciDev; 2131 2176 pBus->cBridges++;
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