VirtualBox

Ignore:
Timestamp:
Sep 8, 2011 8:34:02 AM (13 years ago)
Author:
vboxsync
Message:

HM: renamed some internal functions.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r38677 r38683  
    7070*   Local Functions                                                            *
    7171*******************************************************************************/
    72 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
    73 static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
    74 static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
    75 static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
    76 static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
    77 static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
    78 static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     72static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
     73static void hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu);
     74static void hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu);
     75static void hmR0VmxSetupTLBDummy(PVM pVM, PVMCPU pVCpu);
     76static void hmR0VmxFlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
     77static void hmR0VmxFlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
     78static void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    7979#ifdef VBOX_STRICT
    80 static bool vmxR0IsValidReadField(uint32_t idxField);
    81 static bool vmxR0IsValidWriteField(uint32_t idxField);
    82 #endif
    83 static void vmxR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
    84 
    85 static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
     80static bool hmR0VmxIsValidReadField(uint32_t idxField);
     81static bool hmR0VmxIsValidWriteField(uint32_t idxField);
     82#endif
     83static void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
     84
     85
     86static void hmR0VmxCheckError(PVM pVM, PVMCPU pVCpu, int rc)
    8687{
    8788    if (rc == VERR_VMX_GENERIC)
    … …  
    526527
    527528            /* Allow the guest to directly modify these MSRs; they are restored and saved automatically. */
    528             vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
    529             vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
    530             vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
    531             vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
    532             vmxR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
    533             vmxR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
    534             vmxR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
    535             vmxR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
    536             vmxR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
     529            hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
     530            hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
     531            hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
     532            hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
     533            hmR0VmxSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
     534            hmR0VmxSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
     535            hmR0VmxSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
     536            hmR0VmxSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
     537            hmR0VmxSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
    537538        }
    538539
    … …  
    630631    if (pVM->hwaccm.s.fNestedPaging)
    631632    {
    632         pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
     633        pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = hmR0VmxSetupTLBEPT;
    633634
    634635        /* Default values for flushing. */
    … …  
    650651    if (pVM->hwaccm.s.vmx.fVPID)
    651652    {
    652         pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
     653        pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = hmR0VmxSetupTLBVPID;
    653654
    654655        /* Default values for flushing. */
    … …  
    668669#endif /* HWACCM_VTX_WITH_VPID */
    669670    else
    670         pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
     671        pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = hmR0VmxSetupTLBDummy;
    671672
    672673vmx_end:
    673     VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
     674    hmR0VmxCheckError(pVM, &pVM->aCpus[0], rc);
    674675    return rc;
    675676}
    … …  
    683684 * @param   fWrite      Writing allowed/disallowed
    684685 */
    685 static void vmxR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
     686static void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
    686687{
    687688    unsigned ulBit;
    … …  
    739740 * @param   errCode     Error code (optional)
    740741 */
    741 static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
     742static int hmR0VmxInjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
    742743{
    743744    int         rc;
    … …  
    750751#ifdef VBOX_STRICT
    751752    if (iGate == 0xE)
    752         LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
     753        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
    753754    else
    754755    if (iGate < 0x20)
    755         LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
     756        LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
    756757    else
    757758    {
    … …  
    790791                intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    791792
    792                 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, 0, 0 /* no error code according to the Intel docs */);
     793                return hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, 0, 0 /* no error code according to the Intel docs */);
    793794            }
    794795            Log(("Triple fault -> reset the VM!\n"));
    … …  
    852853 * @param   pCtx        CPU Context
    853854 */
    854 static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
     855static int hmR0VmxCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
    855856{
    856857    int rc;
    … …  
    861862        Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
    862863        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
    863         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
     864        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
    864865        AssertRC(rc);
    865866
    … …  
    881882            intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    882883
    883             rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
     884            rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
    884885            AssertRC(rc);
    885886
    … …  
    985986
    986987        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
    987         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
     988        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
    988989        AssertRC(rc);
    989990    } /* if (interrupts can be dispatched) */
    … …  
    12421243 * @param   pCtx        Guest context
    12431244 */
    1244 static int vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
     1245static int hmR0VmxPrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
    12451246{
    12461247    if (CPUMIsGuestInPAEModeEx(pCtx))
    … …  
    12661267 * @param   pCtx        Guest context
    12671268 */
    1268 static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
     1269static void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
    12691270{
    12701271    uint32_t u32TrapMask;
    … …  
    17531754                val = pCtx->cr3;
    17541755                /* Prefetch the four PDPT entries in PAE mode. */
    1755                 rc = vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
     1756                rc = hmR0VmxPrefetchPAEPdptrs(pVM, pVCpu, pCtx);
    17561757                AssertRCReturn(rc, rc);
    17571758            }
    … …  
    18541855    }
    18551856
    1856     vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
     1857    hmR0VmxUpdateExceptionBitmap(pVM, pVCpu, pCtx);
    18571858
    18581859#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
    … …  
    20282029        }
    20292030        /* Prefetch the four PDPT entries in PAE mode. */
    2030         rc = vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
     2031        rc = hmR0VmxPrefetchPAEPdptrs(pVM, pVCpu, pCtx);
    20312032        AssertRCReturn(rc, rc);
    20322033    }
    … …  
    21262127 * @param   pVCpu       The VMCPU to operate on.
    21272128 */
    2128 static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
     2129static void hmR0VmxSetupTLBDummy(PVM pVM, PVMCPU pVCpu)
    21292130{
    21302131    NOREF(pVM);
    … …  
    21422143 * @param   pVCpu       The VMCPU to operate on.
    21432144 */
    2144 static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
     2145static void hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu)
    21452146{
    21462147    PHMGLOBLCPUINFO pCpu;
    … …  
    21742175    if (pVCpu->hwaccm.s.fForceTLBFlush)
    21752176    {
    2176         vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
     2177        hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
    21772178    }
    21782179    else
    … …  
    21852186        {
    21862187            /* aTlbShootdownPages contains physical addresses in this case. */
    2187             vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
     2188            hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
    21882189        }
    21892190    }
    … …  
    22072208 * @param   pVCpu       The VMCPU to operate on.
    22082209 */
    2209 static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
     2210static void hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu)
    22102211{
    22112212    PHMGLOBLCPUINFO pCpu;
    … …  
    22432244            pCpu->uCurrentASID               = 1;       /* start at 1; host uses 0 */
    22442245            pCpu->cTLBFlushes++;
    2245             vmxR0FlushVPID(pVM, pVCpu, VMX_FLUSH_ALL_CONTEXTS, 0);
     2246            hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_ALL_CONTEXTS, 0);
    22462247        }
    22472248        else
    … …  
    22622263            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
    22632264            for (unsigned i = 0; i < pVCpu->hwaccm.s.TlbShootdown.cPages; i++)
    2264                 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
     2265                hmR0VmxFlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
    22652266        }
    22662267    }
    … …  
    22762277
    22772278    if (pVCpu->hwaccm.s.fForceTLBFlush)
    2278         vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
     2279        hmR0VmxFlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
    22792280
    22802281# ifdef VBOX_WITH_STATISTICS
    … …  
    25162517     * Interrupts are disabled before the call to make sure we don't miss any interrupt
    25172518     * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
    2518      * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
     2519     * further down, but hmR0VmxCheckPendingInterrupt makes that impossible.)
    25192520     *
    25202521     * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
    … …  
    25332534    /* When external interrupts are pending, we should exit the VM when IF is set. */
    25342535    /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
    2535     rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
     2536    rc = hmR0VmxCheckPendingInterrupt(pVM, pVCpu, pCtx);
    25362537    if (RT_FAILURE(rc))
    25372538        goto end;
    … …  
    25732574            {
    25742575                /* A TPR change could activate a pending interrupt, so catch lstar writes. */
    2575                 vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
     2576                hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
    25762577            }
    25772578            else
    … …  
    25802581                 * There are enough world switches for detecting pending interrupts.
    25812582                 */
    2582                 vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
     2583                hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
    25832584            }
    25842585        }
    … …  
    27432744    if (RT_UNLIKELY(rc != VINF_SUCCESS))
    27442745    {
    2745         VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
     2746        hmR0VmxReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
    27462747        VMMR0LogFlushEnable(pVCpu);
    27472748        goto end;
    … …  
    28902891                Log(("Forward #NM fault to the guest\n"));
    28912892                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
    2892                 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
     2893                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
    28932894                AssertRC(rc2);
    28942895                STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
    … …  
    29112912                    /* Now we must update CR2. */
    29122913                    pCtx->cr2 = exitQualification;
    2913                     rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     2914                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    29142915                    AssertRC(rc2);
    29152916
    … …  
    30033004                    /* Now we must update CR2. */
    30043005                    pCtx->cr2 = exitQualification;
    3005                     rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3006                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    30063007                    AssertRC(rc2);
    30073008
    … …  
    30293030                }
    30303031                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
    3031                 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3032                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    30323033                AssertRC(rc2);
    30333034
    … …  
    30783079
    30793080                    Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip, exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7]));
    3080                     rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3081                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    30813082                    AssertRC(rc2);
    30823083
    … …  
    30953096                {
    30963097                    Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
    3097                     rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3098                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    30983099                    AssertRC(rc2);
    30993100                    STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
    … …  
    31213122                {
    31223123                    Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
    3123                     rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3124                    rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    31243125                    AssertRC(rc2);
    31253126                    STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
    … …  
    32903291                        intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    32913292
    3292                         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
     3293                        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    32933294                        AssertRC(VBOXSTRICTRC_VAL(rc));
    32943295                        fUpdateRIP = false;
    … …  
    33083309                            intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    33093310
    3310                             rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
     3311                            rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    33113312                            AssertRC(VBOXSTRICTRC_VAL(rc));
    33123313                            fUpdateRIP = false;
    … …  
    33253326                        intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    33263327
    3327                         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
     3328                        rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    33283329                        AssertRC(VBOXSTRICTRC_VAL(rc));
    33293330                        fUpdateRIP = false;
    … …  
    33813382
    33823383                Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
    3383                 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3384                rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    33843385                AssertRC(rc2);
    33853386
    … …  
    33933394                {
    33943395                    Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
    3395                     rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
     3396                    rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
    33963397                    AssertRC(VBOXSTRICTRC_VAL(rc)); /* Strict RC check below. */
    33973398
    … …  
    39563957
    39573958                            Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
    3958                             rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
     3959                            rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
    39593960                            AssertRC(rc2);
    39603961
    … …  
    43414342 * @param   GCPhys      Physical address of the page to flush
    43424343 */
    4343 static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
     4344static void hmR0VmxFlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
    43444345{
    43454346    uint64_t descriptor[2];
    43464347
    4347     LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
     4348    LogFlow(("hmR0VmxFlushEPT %d %RGv\n", enmFlush, GCPhys));
    43484349    Assert(pVM->hwaccm.s.fNestedPaging);
    43494350    descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
    … …  
    43634364 * @param   GCPtr       Virtual address of the page to flush
    43644365 */
    4365 static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
     4366static void hmR0VmxFlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
    43664367{
    43674368#if HC_ARCH_BITS == 32
    … …  
    44084409    if (   !fFlushPending
    44094410        && pVM->hwaccm.s.vmx.fVPID)
    4410         vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
     4411        hmR0VmxFlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
    44114412#endif /* HWACCM_VTX_WITH_VPID */
    44124413
    … …  
    44344435    /* Skip it if a TLB flush is already pending. */
    44354436    if (!fFlushPending)
    4436         vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
     4437        hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
    44374438
    44384439    return VINF_SUCCESS;
    … …  
    44474448 * @param   pCtx        Current CPU context (not updated)
    44484449 */
    4449 static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx)
     4450static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx)
    44504451{
    44514452    switch (VBOXSTRICTRC_VAL(rc))
    … …  
    46964697#ifdef VBOX_STRICT
    46974698    for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
    4698         Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
     4699        Assert(hmR0VmxIsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
    46994700
    47004701    for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
    4701         Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
     4702        Assert(hmR0VmxIsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
    47024703#endif
    47034704
    … …  
    48504851
    48514852#ifdef VBOX_STRICT
    4852 static bool vmxR0IsValidReadField(uint32_t idxField)
     4853static bool hmR0VmxIsValidReadField(uint32_t idxField)
    48534854{
    48544855    switch(idxField)
    … …  
    49184919}
    49194920
    4920 static bool vmxR0IsValidWriteField(uint32_t idxField)
     4921static bool hmR0VmxIsValidWriteField(uint32_t idxField)
    49214922{
    49224923    switch(idxField)
    … …  
    49464947
    49474948#endif
     4949
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