Changeset 38868 in vbox for trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp
- Timestamp:
- Sep 26, 2011 2:31:45 PM (13 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp
r37955 r38868 5 5 6 6 /* 7 * Copyright (C) 2006-20 07Oracle Corporation7 * Copyright (C) 2006-2011 Oracle Corporation 8 8 * 9 9 * This file is part of VirtualBox Open Source Edition (OSE), as … … 37 37 38 38 39 /******************************************************************************* 40 * Structures and Typedefs * 41 *******************************************************************************/ 39 42 #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI 40 /** Local APIC mappings */ 41 typedef struct 42 { 43 /** 44 * Local APIC mappings. 45 */ 46 typedef struct CPUMHOSTLAPIC 47 { 48 /** Indicates that the entry is in use and have valid data. */ 43 49 bool fEnabled; 44 uint64_t PhysBase; 50 /** Has APIC_REG_LVT_THMR. Not used. */ 51 uint32_t fHasThermal; 52 /** The physical address of the APIC registers. */ 53 RTHCPHYS PhysBase; 54 /** The memory object entering the physical address. */ 45 55 RTR0MEMOBJ hMemObj; 56 /** The mapping object for hMemObj. */ 46 57 RTR0MEMOBJ hMapObj; 58 /** The mapping address APIC registers. 59 * @remarks Different CPUs may use the same physical address to map their 60 * APICs, so this pointer is only valid when on the CPU owning the 61 * APIC. */ 47 62 void *pv; 48 uint32_t fHasThermal;49 63 } CPUMHOSTLAPIC; 50 64 #endif 65 66 67 /******************************************************************************* 68 * Global Variables * 69 *******************************************************************************/ 70 #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI 51 71 static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS]; 72 #endif 73 74 75 /******************************************************************************* 76 * Internal Functions * 77 *******************************************************************************/ 78 #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI 52 79 static int cpumR0MapLocalApics(void); 53 80 static void cpumR0UnmapLocalApics(void); … … 638 665 } 639 666 640 641 667 #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI 668 642 669 /** 643 670 * Worker for cpumR0MapLocalApics. Check each CPU for a present Local APIC. … … 669 696 uint32_t u32MaxExtIdx; 670 697 ASMCpuId(0x80000000, &u32MaxExtIdx, &u32EBX, &u32ECX, &u32EDX); 671 if ( u32MaxExtIdx >= 0x80000008672 && u32MaxExtIdx < 0x8000ffff)698 if ( u32MaxExtIdx >= UINT32_C(0x80000008) 699 && u32MaxExtIdx < UINT32_C(0x8000ffff)) 673 700 { 674 701 uint32_t u32PhysBits; … … 678 705 } 679 706 680 g_aLApics[iCpu].fEnabled = true; 681 g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask; 707 uint64_t const u64PhysBase = u64ApicBase & u64Mask; 708 g_aLApics[iCpu].PhysBase = (RTHCPHYS)u64PhysBase; 709 g_aLApics[iCpu].fEnabled = g_aLApics[iCpu].PhysBase == u64PhysBase; 682 710 } 683 711 } … … 725 753 * 0x2X..0xFF reserved 726 754 */ 755 /** @todo r=bird: The local APIC is usually at the same address for all CPUs, 756 * and therefore inaccessible by the other CPUs. */ 727 757 uint32_t ApicVersion = ApicRegRead(pvApicBase, APIC_REG_VERSION); 728 758 if ((APIC_REG_VERSION_GET_VER(ApicVersion) & 0xF0) == 0x10) … … 730 760 g_aLApics[iCpu].fHasThermal = APIC_REG_VERSION_GET_MAX_LVT(ApicVersion) >= 5; 731 761 g_aLApics[iCpu].pv = pvApicBase; 762 Log(("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#x, lint0=%#x lint1=%#x pc=%#x thmr=%#x\n", 763 iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, ApicVersion, 764 ApicRegRead(pvApicBase, APIC_REG_LVT_LINT0), 765 ApicRegRead(pvApicBase, APIC_REG_LVT_LINT1), 766 ApicRegRead(pvApicBase, APIC_REG_LVT_PC), 767 ApicRegRead(pvApicBase, APIC_REG_LVT_THMR) 768 )); 732 769 continue; 733 770 } … … 785 822 786 823 #endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */ 824
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