Changeset 39038 in vbox for trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

Timestamp:

Oct 19, 2011 2:36:27 PM (13 years ago)

Author:

vboxsync

Message:

VMM: -W4 warnings (MSC).

File:

• trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -964 +964 @@
     uint64_t    exitCode = (uint64_t)SVM_EXIT_INVALID;
     SVM_VMCB   *pVMCB;
-    bool        fSyncTPR = false;
     unsigned    cResume = 0;
-    uint8_t     u8LastTPR;
     PHMGLOBLCPUINFO pCpu = 0;
     RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
@@ -1092 +1090 @@
      * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
      *       shootdowns rely on this.
-     */                                               
+     */
     uOldEFlags = ASMIntDisableFlags();
     if (RTThreadPreemptIsPending(NIL_RTTHREAD))
@@ -1111 +1109 @@
     /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
     /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
-     * @todo query and update the TPR only when it could have been changed (mmio access)
      */
+    /** @todo query and update the TPR only when it could have been changed (mmio access)
+     */
+    bool    fSyncTPR  = false;
+    uint8_t u8LastTPR = 0; /* Initialized for potentially stupid compilers. */
     if (pVM->hwaccm.s.fHasIoApic)
     {
+        /* TPR caching in CR8 */
         bool fPending;
-
-        /* TPR caching in CR8 */
         rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
         AssertRC(rc2);
@@ -1587 +1587 @@
         else
         {
-            if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
+            if ((uint8_t)(u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
             {
                 rc2 = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4);   /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */