VirtualBox

Changeset 40447 in vbox


Ignore:
Timestamp:
Mar 13, 2012 3:30:35 PM (13 years ago)
Author:
vboxsync
Message:

EM: More refactoring.

Location:
trunk
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/em.h

    r40442 r40447  
    8181
    8282/**
    83  * EMInterpretInstructionCPUEx execution modes.
     83 * EMInterpretInstructionCPU execution modes.
    8484 */
    8585typedef enum
    … …  
    157157VMMDECL(int)            EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
    158158                                              PDISCPUSTATE pDISState, unsigned *pcbInstr);
    159 VMMDECL(VBOXSTRICTRC)   EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
     159VMMDECL(VBOXSTRICTRC)   EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     160VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
    160161VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
    161162VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionCpuUpdtPC(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, EMCODETYPE enmCodeType);

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r40446 r40447  
    488488 *          to worry about e.g. invalid modrm combinations (!)
    489489 */
    490 VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     490VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    491491{
    492492    LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    … …  
    513513        {
    514514            Assert(cbOp == pDis->opsize);
    515             rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbSize);
     515            uint32_t cbIgnored;
     516            rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
     517            if (RT_SUCCESS(rc))
     518                pRegFrame->rip += cbOp; /* Move on to the next instruction. */
     519
     520            return rc;
     521        }
     522    }
     523    return VERR_EM_INTERPRETER;
     524#endif
     525}
     526
     527
     528/**
     529 * Interprets the current instruction.
     530 *
     531 * @returns VBox status code.
     532 * @retval  VINF_*                  Scheduling instructions.
     533 * @retval  VERR_EM_INTERPRETER     Something we can't cope with.
     534 * @retval  VERR_*                  Fatal errors.
     535 *
     536 * @param   pVM         The VM handle.
     537 * @param   pVCpu       The VMCPU handle.
     538 * @param   pRegFrame   The register frame.
     539 *                      Updates the EIP if an instruction was executed successfully.
     540 * @param   pvFault     The fault address (CR2).
     541 * @param   pcbWritten  Size of the write (if applicable).
     542 *
     543 * @remark  Invalid opcode exceptions have a higher priority than GP (see Intel
     544 *          Architecture System Developers Manual, Vol 3, 5.5) so we don't need
     545 *          to worry about e.g. invalid modrm combinations (!)
     546 */
     547VMMDECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
     548{
     549    LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
     550#ifdef VBOX_WITH_IEM
     551    int rc = IEMExecOneEx(pVCpu, pRegFrame, IEM_EXEC_ONE_EX_FLAGS_, pcbWritten);
     552    if (RT_FAILURE(rc))
     553        switch (rc)
     554        {
     555            case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
     556            case VERR_IEM_INSTR_NOT_IMPLEMENTED:
     557                return VERR_EM_INTERPRETER;
     558        }
     559    return rc;
     560#else
     561    RTGCPTR pbCode;
     562    VBOXSTRICTRC rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
     563    if (RT_SUCCESS(rc))
     564    {
     565        uint32_t     cbOp;
     566        PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
     567        pDis->mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
     568        rc = emDisCoreOne(pVM, pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
     569        if (RT_SUCCESS(rc))
     570        {
     571            Assert(cbOp == pDis->opsize);
     572            rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
    516573            if (RT_SUCCESS(rc))
    517574                pRegFrame->rip += cbOp; /* Move on to the next instruction. */

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r40274 r40447  
    807807VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    808808{
    809     uint32_t cb;
    810     VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
     809    VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
    811810    if (rc == VERR_EM_INTERPRETER)
    812811        rc = VINF_EM_RAW_EMULATE_INSTR;

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r40356 r40447  
    20552055    case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
    20562056    {
    2057         uint32_t cbSize;
    2058 
    20592057        Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
    20602058        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
    2061         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2059        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    20622060
    20632061        switch (exitCode - SVM_EXIT_WRITE_CR0)
    … …  
    20962094    case SVM_EXIT_READ_CR12:  case SVM_EXIT_READ_CR13:  case SVM_EXIT_READ_CR14:  case SVM_EXIT_READ_CR15:
    20972095    {
    2098         uint32_t cbSize;
    2099 
    21002096        Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
    21012097        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
    2102         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2098        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    21032099        if (rc == VINF_SUCCESS)
    21042100        {
    … …  
    21172113    case SVM_EXIT_WRITE_DR12:  case SVM_EXIT_WRITE_DR13:  case SVM_EXIT_WRITE_DR14:  case SVM_EXIT_WRITE_DR15:
    21182114    {
    2119         uint32_t cbSize;
    2120 
    21212115        Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
    21222116        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
    … …  
    21372131        }
    21382132
    2139         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2133        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    21402134        if (rc == VINF_SUCCESS)
    21412135        {
    … …  
    21552149    case SVM_EXIT_READ_DR12:  case SVM_EXIT_READ_DR13:  case SVM_EXIT_READ_DR14:  case SVM_EXIT_READ_DR15:
    21562150    {
    2157         uint32_t cbSize;
    2158 
    21592151        Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
    21602152        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
    … …  
    21742166        }
    21752167
    2176         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2168        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    21772169        if (rc == VINF_SUCCESS)
    21782170        {
    … …  
    24342426    case SVM_EXIT_MSR:
    24352427    {
    2436         uint32_t cbSize;
    2437 
    24382428        /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
    24392429        if (    pVM->hwaccm.s.fTPRPatchingActive
    … …  
    24602450        STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
    24612451        Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
    2462         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2452        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    24632453        if (rc == VINF_SUCCESS)
    24642454        {

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r40442 r40447  
    36563656    case VMX_EXIT_RDMSR:                /* 31 RDMSR. Guest software attempted to execute RDMSR. */
    36573657    {
    3658         uint32_t cbSize;
    3659 
    36603658        STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
    36613659
    36623660        /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
    36633661        Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
    3664         rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     3662        rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0);
    36653663        if (rc == VINF_SUCCESS)
    36663664        {

  • trunk/src/VBox/VMM/VMMRC/PATMRC.cpp

    r40442 r40447  
    111111        {
    112112            /* This part of the page was not patched; try to emulate the instruction. */
    113             uint32_t cb;
    114 
    115113            LogFlow(("PATMHandleWriteToPatchPage: Interpret %x accessing %RRv\n", pRegFrame->eip, GCPtr));
    116             int rc = EMInterpretInstruction(pVM, VMMGetCpu0(pVM), pRegFrame, (RTGCPTR)(RTRCUINTPTR)GCPtr, &cb);
     114            int rc = EMInterpretInstruction(pVM, VMMGetCpu0(pVM), pRegFrame, (RTGCPTR)(RTRCUINTPTR)GCPtr);
    117115            if (rc == VINF_SUCCESS)
    118116            {

  • trunk/src/VBox/VMM/VMMRC/SELMRC.cpp

    r39078 r40447  
    194194        /** @todo should check if any affected selectors are loaded. */
    195195        uint32_t cb;
    196         rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
     196        rc = EMInterpretInstructionEx(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
    197197        if (RT_SUCCESS(rc) && cb)
    198198        {
    … …  
    305305     */
    306306    uint32_t cb;
    307     int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
     307    int rc = EMInterpretInstructionEx(pVM, pVCpu, pRegFrame, (RTGCPTR)(RTRCUINTPTR)pvFault, &cb);
    308308    if (RT_SUCCESS(rc) && cb)
    309309    {

  • trunk/src/VBox/VMM/VMMRC/TRPMRC.cpp

    r39078 r40447  
    125125    {
    126126        uint32_t cb;
    127         int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
     127        int rc = EMInterpretInstructionEx(pVM, pVCpu, pRegFrame, pvFault, &cb);
    128128        if (RT_SUCCESS(rc) && cb)
    129129        {
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