Changeset 41906 in vbox for trunk/src/VBox/VMM/VMMAll/EMAll.cpp

Timestamp:

Jun 24, 2012 3:44:03 PM (13 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

78759

Message:

CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.

File:

• trunk/src/VBox/VMM/VMMAll/EMAll.cpp (modified) (10 diffs)

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -384 +384 @@
 #else
 /** @todo Get the CPU mode as well while we're at it! */
-    int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss, pCtxCore->cs,
-                                          &pCtxCore->csHid, pCtxCore->rip, &GCPtrInstr);
+    int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel,
+                                          &pCtxCore->cs, pCtxCore->rip, &GCPtrInstr);
 #endif
     if (RT_FAILURE(rc))
     {
         Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
-             pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
+             pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
         return rc;
     }
@@ -415 +415 @@
                                    PDISCPUSTATE pDis, unsigned *pcbInstr)
 {
-    DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(pVCpu, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid);
+    DISCPUMODE enmCpuMode = SELMGetCpuModeFromSelector(pVCpu, pCtxCore->eflags, pCtxCore->cs.Sel, (PCPUMSELREGHID)&pCtxCore->cs);
     /** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
      *        \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
@@ -461 +461 @@
         uint32_t     cbOp;
         PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
-        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
+        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs);
         rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
         if (RT_SUCCESS(rc))
@@ -515 +515 @@
         uint32_t     cbOp;
         PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
-        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
+        pDis->uCpuMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs.Sel, &pRegFrame->cs);
         rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
         if (RT_SUCCESS(rc))
@@ -625 +625 @@
     AssertRCReturn(rc, VERR_EM_INTERPRETER);
 
-    pRegFrame->eip = eip & 0xffff;
-    pRegFrame->cs  = cs;
+    pRegFrame->eip    = eip & 0xffff;
+    pRegFrame->cs.Sel = cs;
 
     /* Mask away all reserved bits */
@@ -635 +635 @@
     Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
 
-    pRegFrame->esp = esp;
-    pRegFrame->ss  = ss;
-    pRegFrame->ds  = ds;
-    pRegFrame->es  = es;
-    pRegFrame->fs  = fs;
-    pRegFrame->gs  = gs;
+    pRegFrame->esp      = esp;
+    pRegFrame->ss.Sel   = ss;
+    pRegFrame->ds.Sel   = ds;
+    pRegFrame->es.Sel   = es;
+    pRegFrame->fs.Sel   = fs;
+    pRegFrame->gs.Sel   = gs;
 
     return VINF_SUCCESS;
@@ -926 +926 @@
             {
                 /* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
-                if (pRegFrame->csHid.Attr.n.u1Long)
+                if (pRegFrame->cs.Attr.n.u1Long)
                 {
                     AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
@@ -1535 +1535 @@
 
             /* Read stack value first */
-            if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == DISCPUMODE_16BIT)
+            if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, &pRegFrame->ss) == DISCPUMODE_16BIT)
                 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
 
@@ -2202 +2202 @@
     if (!(pDis->fPrefix & DISPREFIX_REP))
     {
-        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
+        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
 
         rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
@@ -2247 +2247 @@
         }
 
-        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
+        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
         /* Access verification first; we currently can't recover properly from traps inside this instruction */
         rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),