Changeset 43329 in vbox for trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
- Timestamp:
- Sep 14, 2012 3:55:26 PM (12 years ago)
- File:
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- 1 edited
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trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r40963 r43329 69 69 #define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1 70 70 71 /** The duration of software-initiated reset. Not documented, set to 500 us. */ 72 #define BUSLOGIC_RESET_DURATION_NS (500*1000) 73 71 74 /** 72 75 * State of a device attached to the buslogic host adapter. … … 121 124 enum BUSLOGICCOMMAND 122 125 { 123 BUSLOGICCOMMAND_TEST_C OMMAND_COMPLETE_INTERRUPT = 0x00,126 BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00, 124 127 BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01, 125 128 BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02, … … 249 252 #pragma pack() 250 253 251 #pragma pack(1)252 254 /** 253 255 * The local Ram. … … 267 269 } HostAdapterLocalRam, *PHostAdapterLocalRam; 268 270 AssertCompileSize(HostAdapterLocalRam, 256); 269 #pragma pack()270 271 271 272 /** Pointer to a task state structure. */ … … 304 305 /** Geometry register - Readonly. */ 305 306 volatile uint8_t regGeometry; 307 /** Pending (delayed) interrupt. */ 308 uint8_t uPendingIntr; 306 309 307 310 /** Local RAM for the fetch hostadapter local RAM request. … … 345 348 #endif 346 349 350 /** Time when HBA reset was last initiated. */ //@todo: does this need to be saved? 351 uint64_t u64ResetTime; 347 352 /** Physical base address of the outgoing mailboxes. */ 348 353 RTGCPHYS GCPhysAddrMailboxOutgoingBase; … … 442 447 /** Fields for the interrupt register. */ 443 448 # define BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED RT_BIT(0) 444 # define BUSLOGIC_REGISTER_INTERRUPT_OUT COMING_MAILBOX_AVAILABLERT_BIT(1)449 # define BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE RT_BIT(1) 445 450 # define BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE RT_BIT(2) 446 451 # define BUSLOGIC_REGISTER_INTERRUPT_EXTERNAL_BUS_RESET RT_BIT(3) … … 451 456 452 457 /* Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */ 453 #pragma pack(1)454 458 typedef struct ReplyInquirePCIHostAdapterInformation 455 459 { … … 467 471 } ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation; 468 472 AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4); 469 #pragma pack()470 473 471 474 /* Structure for the INQUIRE_CONFIGURATION reply. */ 472 #pragma pack(1)473 475 typedef struct ReplyInquireConfiguration 474 476 { … … 489 491 } ReplyInquireConfiguration, *PReplyInquireConfiguration; 490 492 AssertCompileSize(ReplyInquireConfiguration, 3); 491 #pragma pack()492 493 493 494 /* Structure for the INQUIRE_SETUP_INFORMATION reply. */ 494 #pragma pack(1)495 495 typedef struct ReplyInquireSetupInformationSynchronousValue 496 496 { … … 500 500 }ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue; 501 501 AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1); 502 #pragma pack() 503 504 #pragma pack(1) 502 505 503 typedef struct ReplyInquireSetupInformation 506 504 { … … 527 525 } ReplyInquireSetupInformation, *PReplyInquireSetupInformation; 528 526 AssertCompileSize(ReplyInquireSetupInformation, 34); 529 #pragma pack()530 527 531 528 /* Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */ … … 789 786 790 787 /** 788 * Assert IRQ line of the BusLogic adapter. 789 * 790 * @returns nothing. 791 * @param pBusLogic Pointer to the BusLogic device instance. 792 * @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled 793 * @param uFlag Type of interrupt being generated. 794 */ 795 static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType) 796 { 797 LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); 798 799 /* The CMDC interrupt has priority over IMBL and MBOR. */ 800 if (uIrqType & (BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED | BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE)) 801 { 802 if (!(pBusLogic->regInterrupt & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE)) 803 pBusLogic->regInterrupt |= uIrqType; /* Report now. */ 804 else 805 pBusLogic->uPendingIntr |= uIrqType; /* Report later. */ 806 } 807 else if (uIrqType & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE) 808 { 809 Assert(!pBusLogic->regInterrupt); 810 pBusLogic->regInterrupt |= uIrqType; 811 } 812 else 813 AssertMsgFailed(("Invalid interrupt state!\n")); 814 815 pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID; 816 if (pBusLogic->fIRQEnabled && !fSuppressIrq) 817 PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1); 818 } 819 820 /** 791 821 * Deasserts the interrupt line of the BusLogic adapter. 792 822 * … … 799 829 pBusLogic->regInterrupt = 0; 800 830 PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0); 801 } 802 803 /** 804 * Assert IRQ line of the BusLogic adapter. 805 * 806 * @returns nothing. 807 * @param pBusLogic Pointer to the BusLogic device instance. 808 * @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled 809 */ 810 static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq) 811 { 812 LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); 813 pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID; 814 if (pBusLogic->fIRQEnabled && !fSuppressIrq) 815 PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1); 831 /* If there's another pending interrupt, report it now. */ 832 if (pBusLogic->uPendingIntr) 833 { 834 buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr); 835 pBusLogic->uPendingIntr = 0; 836 } 816 837 } 817 838 … … 876 897 pBusLogic->regStatus = BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY | BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED; 877 898 pBusLogic->regInterrupt = 0; 899 pBusLogic->uPendingIntr = 0; 878 900 pBusLogic->regGeometry = BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED; 879 901 pBusLogic->uOperationCode = 0xff; /* No command executing. */ … … 912 934 /* Notify that the command is complete. */ 913 935 pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY; 914 pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE; 915 916 buslogicSetInterrupt(pBusLogic, fSuppressIrq); 936 buslogicSetInterrupt(pBusLogic, fSuppressIrq, BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE); 917 937 } 918 938 … … 931 951 { 932 952 LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); 953 954 /* Remember when the guest initiated a reset. */ 955 pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns)); 933 956 934 957 buslogicHwReset(pBusLogic); … … 987 1010 #endif 988 1011 989 pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED; 990 buslogicSetInterrupt(pBusLogic, false); 1012 buslogicSetInterrupt(pBusLogic, false, BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED); 991 1013 992 1014 PDMCritSectLeave(&pBusLogic->CritSectIntr); … … 1318 1340 switch (pBusLogic->uOperationCode) 1319 1341 { 1342 case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT: 1343 /* Valid command, no reply. */ 1344 pBusLogic->cbReplyParametersLeft = 0; 1345 break; 1320 1346 case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION: 1321 1347 { … … 1326 1352 pReply->InformationIsValid = 0; 1327 1353 pReply->IsaIOPort = 0xff; /* Make it invalid. */ 1354 pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev); 1328 1355 pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation); 1329 1356 break; … … 1367 1394 break; 1368 1395 } 1396 case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS: 1397 /* The parameter list length is determined by the first byte of the command buffer. */ 1398 if (pBusLogic->iParameter == 1) 1399 { 1400 /* First pass - set the number of following parameter bytes. */ 1401 pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0]; 1402 Log(("Set HA options: %u bytes follow\n", pBusLogic->aCommandBuffer[0])); 1403 } 1404 else 1405 { 1406 /* Second pass - process received data. */ 1407 Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0])); 1408 /* We ignore the data - it only concerns the SCSI hardware protocol. */ 1409 } 1410 pBusLogic->cbReplyParametersLeft = 0; 1411 break; 1412 1369 1413 case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER: 1370 1414 { … … 1384 1428 case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION: 1385 1429 { 1430 uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev); 1431 1386 1432 pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration); 1387 1433 PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer; … … 1389 1435 1390 1436 pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */ 1391 /* 1392 * The rest of this reply only applies for ISA adapters. 1393 * This is a PCI adapter so they are not important and are skipped. 1394 */ 1437 //@todo: What should the DMA channel be? 1438 pReply->fDmaChannel6 = 1; 1439 /* The IRQ is not necessarily representable in this structure. */ 1440 switch (uPciIrq) { 1441 case 9: pReply->fIrqChannel9 = 1; break; 1442 case 10: pReply->fIrqChannel10 = 1; break; 1443 case 11: pReply->fIrqChannel11 = 1; break; 1444 case 12: pReply->fIrqChannel12 = 1; break; 1445 case 14: pReply->fIrqChannel14 = 1; break; 1446 case 15: pReply->fIrqChannel15 = 1; break; 1447 default: 1448 Log(("Inquire configuration: PCI IRQ %d cannot be represented\n", uPciIrq)); 1449 break; 1450 } 1395 1451 break; 1396 1452 } … … 1405 1461 pReply->uBusType = 'E'; /* EISA style */ 1406 1462 pReply->u16ScatterGatherLimit = 8192; 1463 pReply->cMailbox = pBusLogic->cMailbox; 1464 pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase; 1407 1465 pReply->fLevelSensitiveInterrupt = true; 1408 1466 pReply->fHostWideSCSI = true; … … 1444 1502 Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase)); 1445 1503 Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase)); 1446 Log(("cMailboxes=%u\n", pBusLogic->cMailbox)); 1504 Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox)); 1505 LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress)); 1447 1506 1448 1507 pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED; … … 1474 1533 break; 1475 1534 } 1535 case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7: 1536 /* This is supposed to send TEST UNIT READY to each target/LUN. 1537 * We cheat and skip that, since we already know what's attached 1538 */ 1539 memset(pBusLogic->aReplyBuffer, 0, 8); 1540 for (int i = 0; i < 8; ++i) 1541 { 1542 if (pBusLogic->aDeviceStates[i].fPresent) 1543 pBusLogic->aReplyBuffer[i] = 1; 1544 } 1545 pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */ 1546 pBusLogic->cbReplyParametersLeft = 8; 1547 break; 1476 1548 case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES: 1477 1549 { … … 1528 1600 break; 1529 1601 } 1602 default: 1603 AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode)); 1530 1604 case BUSLOGICCOMMAND_EXT_BIOS_INFO: 1531 1605 case BUSLOGICCOMMAND_UNLOCK_MAILBOX: … … 1538 1612 break; 1539 1613 case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */ 1540 default: 1541 AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode)); 1614 AssertMsgFailed(("Invalid mailbox execute state!\n")); 1542 1615 } 1543 1616 … … 1547 1620 if (pBusLogic->cbReplyParametersLeft) 1548 1621 pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY; 1549 else 1622 else if (!pBusLogic->cbCommandParametersLeft) 1550 1623 buslogicCommandComplete(pBusLogic, fSuppressIrq); 1551 1624 … … 1570 1643 { 1571 1644 *pu32 = pBusLogic->regStatus; 1572 /* 1573 * If the diagnostic active bit is set we are in a hard reset initiated from the guest. 1574 * The guest reads the status register and waits that the host adapter ready bit is set. 1645 1646 /* If the diagnostic active bit is set, we are in a guest-initiated 1647 * hard or soft reset. If the guest reads the status register and 1648 * waits for the host adapter ready bit to be set, we terminate the 1649 * reset right away. However, guests may also expect the reset 1650 * condition to clear automatically after a period of time. 1575 1651 */ 1576 1652 if (pBusLogic->regStatus & BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE) 1577 1653 { 1654 uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns)); 1655 1578 1656 pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE; 1579 1657 pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY; 1658 if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS) 1659 { 1660 /* Let the guest see the ready condition right away. */ 1661 *pu32 &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE; 1662 *pu32 |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY; 1663 pBusLogic->u64ResetTime = 0; 1664 } 1580 1665 } 1581 1666 break; … … 1588 1673 *pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply]; 1589 1674 1590 pBusLogic->iReply++; 1591 pBusLogic->cbReplyParametersLeft--; 1592 1593 LogFlowFunc(("cbReplyParametersLeft=%u\n", pBusLogic->cbReplyParametersLeft)); 1594 if (!pBusLogic->cbReplyParametersLeft) 1675 /* Careful about underflow - guest can read data register even if 1676 * no data is available. 1677 */ 1678 if (pBusLogic->cbReplyParametersLeft) 1595 1679 { 1596 /* 1597 * Reply finished, set command complete bit, unset data in ready bit and 1598 * interrupt the guest if enabled. 1599 */ 1600 buslogicCommandComplete(pBusLogic, false); 1680 pBusLogic->iReply++; 1681 pBusLogic->cbReplyParametersLeft--; 1682 if (!pBusLogic->cbReplyParametersLeft) 1683 { 1684 /* 1685 * Reply finished, set command complete bit, unset data-in ready bit and 1686 * interrupt the guest if enabled. 1687 */ 1688 buslogicCommandComplete(pBusLogic, false); 1689 } 1601 1690 } 1691 LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32, 1692 pBusLogic->iReply, pBusLogic->cbReplyParametersLeft)); 1602 1693 break; 1603 1694 } … … 1644 1735 #ifdef LOG_ENABLED 1645 1736 uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0); 1646 Log(("%u incoming mailboxes are ready when this interrupt was cleared\n", cMailboxesReady));1737 Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady)); 1647 1738 #endif 1648 1739 … … 1695 1786 switch (pBusLogic->uOperationCode) 1696 1787 { 1788 case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT: 1697 1789 case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER: 1698 1790 case BUSLOGICCOMMAND_INQUIRE_BOARD_ID: … … 1700 1792 case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION: 1701 1793 case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION: 1794 case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7: 1702 1795 case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES: 1703 1796 pBusLogic->cbCommandParametersLeft = 0; … … 1721 1814 case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX: 1722 1815 pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox); 1816 break; 1817 case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS: 1818 /* There must be at least one byte following this command. */ 1819 pBusLogic->cbCommandParametersLeft = 1; 1723 1820 break; 1724 1821 case BUSLOGICCOMMAND_EXT_BIOS_INFO: … … 1826 1923 { 1827 1924 PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);; 1828 unsigned iRegister = Port - pBusLogic->IOPortBase;1925 unsigned iRegister = Port % 4; 1829 1926 1830 1927 Assert(cb == 1); … … 1849 1946 PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); 1850 1947 int rc = VINF_SUCCESS; 1851 unsigned iRegister = Port - pBusLogic->IOPortBase;1948 unsigned iRegister = Port % 4; 1852 1949 uint8_t uVal = (uint8_t)u32; 1853 1950 … … 1874 1971 * @param cb Number of bytes read. 1875 1972 */ 1876 static int buslogic IsaIOPortRead (PPDMDEVINS pDevIns, void *pvUser,1973 static int buslogicBIOSIOPortRead (PPDMDEVINS pDevIns, void *pvUser, 1877 1974 RTIOPORT Port, uint32_t *pu32, unsigned cb) 1878 1975 { … … 2008 2105 * @param cb The value size in bytes. 2009 2106 */ 2010 static int buslogic IsaIOPortWrite (PPDMDEVINS pDevIns, void *pvUser,2107 static int buslogicBIOSIOPortWrite (PPDMDEVINS pDevIns, void *pvUser, 2011 2108 RTIOPORT Port, uint32_t u32, unsigned cb) 2012 2109 { … … 2038 2135 * @see FNIOMIOPORTOUTSTRING for details. 2039 2136 */ 2040 static DECLCALLBACK(int) buslogic IsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)2137 static DECLCALLBACK(int) buslogicBIOSIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb) 2041 2138 { 2042 2139 PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); … … 2063 2160 * @see FNIOMIOPORTINSTRING for details. 2064 2161 */ 2065 static DECLCALLBACK(int) buslogic IsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)2162 static DECLCALLBACK(int) buslogicBIOSIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb) 2066 2163 { 2067 2164 PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); … … 2091 2188 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/, 2092 2189 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU, 2093 buslogicMMIOWrite, buslogicMMIORead, "BusLogic ");2190 buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO"); 2094 2191 if (RT_FAILURE(rc)) 2095 2192 return rc; … … 2116 2213 { 2117 2214 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32, 2118 NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic ");2215 NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI"); 2119 2216 if (RT_FAILURE(rc)) 2120 2217 return rc; … … 2123 2220 { 2124 2221 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32, 2125 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic ");2222 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI"); 2126 2223 if (RT_FAILURE(rc)) 2127 2224 return rc; … … 2131 2228 { 2132 2229 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32, 2133 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic ");2230 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI"); 2134 2231 if (RT_FAILURE(rc)) 2135 2232 return rc; … … 2203 2300 AssertMsgFailed(("invalid completion status %d\n", rcCompletion)); 2204 2301 } 2205 2206 /* Add task to the cache. */ 2302 /* Remove task from the cache. */ 2207 2303 RTMemCacheFree(pBusLogic->hTaskCache, pTaskState); 2208 2304 } … … 2235 2331 int rc = VINF_SUCCESS; 2236 2332 2237 /* Fetch CCB. */2333 /* Fetch the CCB from guest memory. */ 2238 2334 RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB; 2239 2335 PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB, … … 2371 2467 } 2372 2468 2373 LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, pTaskState->MailboxGuest.u32PhysAddrCCB));2469 LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB)); 2374 2470 #ifdef DEBUG 2375 2471 buslogicDumpMailboxInfo(&pTaskState->MailboxGuest, true); … … 3128 3224 /* Register I/O port space in ISA region for BIOS access. */ 3129 3225 rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 3, NULL, 3130 buslogic IsaIOPortWrite, buslogicIsaIOPortRead,3131 buslogic IsaIOPortWriteStr, buslogicIsaIOPortReadStr,3226 buslogicBIOSIOPortWrite, buslogicBIOSIOPortRead, 3227 buslogicBIOSIOPortWriteStr, buslogicBIOSIOPortReadStr, 3132 3228 "BusLogic BIOS"); 3133 3229 if (RT_FAILURE(rc))
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