VirtualBox

Changeset 43657 in vbox


Ignore:
Timestamp:
Oct 16, 2012 3:34:05 PM (12 years ago)
Author:
vboxsync
Message:

VMM: APIC refactor. Moved APIC base MSR to the VCPU (where it belongs) for lockless accesses.

Location:
trunk
Files:
15 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.mac

    r41906 r43657  
    44
    55;
    6 ; Copyright (C) 2006-2010 Oracle Corporation
     6; Copyright (C) 2006-2012 Oracle Corporation
    77;
    88; This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    194194    .msrSFMASK          resb    8
    195195    .msrKERNELGSBASE    resb    8
    196     .au32SizePadding    resb    32
     196    .msrApicBase        resb    8
     197    .au32SizePadding    resb    24
    197198endstruc
    198199
    … …  
    206207
    207208%endif
     209

  • trunk/include/VBox/vmm/cpumctx.h

    r42427 r43657  
    400400    uint64_t        msrSFMASK;          /**< syscall flag mask. */
    401401    uint64_t        msrKERNELGSBASE;    /**< swapgs exchange value. */
     402    uint64_t        msrApicBase;        /**< The local APIC base (IA32_APIC_BASE MSR). */
    402403    /** @} */
    403404
    404405    /** Size padding. */
    405     uint32_t        au32SizePadding[8];
     406    uint32_t        au32SizePadding[6];
    406407} CPUMCTX;
    407408#pragma pack()

  • trunk/include/VBox/vmm/hm_vmx.h

    r43390 r43657  
    429429    struct
    430430    {
     431        /** Bits set here -must- be set in the correpsonding VM-execution controls. */
    431432        uint32_t        disallowed0;
     433        /** Bits cleared here -must- be cleared in the corresponding VM-execution
     434         *  controls. */
    432435        uint32_t        allowed1;
    433436    } n;

  • trunk/include/VBox/vmm/pdmapi.h

    r40907 r43657  
    4747VMMDECL(bool)       PDMHasIoApic(PVM pVM);
    4848VMMDECL(int)        PDMApicHasPendingIrq(PVM pVM, bool *pfPending);
    49 VMMDECL(int)        PDMApicSetBase(PVM pVM, uint64_t u64Base);
    50 VMMDECL(int)        PDMApicGetBase(PVM pVM, uint64_t *pu64Base);
     49VMMDECL(int)        PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base);
     50VMMDECL(int)        PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base);
     51VMMDECL(int)        PDMApicGetBaseFromApic(PVMCPU pVCpu, uint64_t *pu64Base);
    5152VMMDECL(int)        PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR);
    5253VMMDECL(int)        PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending);

  • trunk/include/VBox/vmm/pdmdev.h

    r43472 r43657  
    10781078     * @returns Pending interrupt number.
    10791079     * @param   pDevIns         Device instance of the APIC.
     1080     * @param   idCpu           The VCPU Id.
    10801081     * @param   puTagSrc        Where to return the tag source.
    10811082     */
    1082     DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
     1083    DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
    10831084
    10841085    /**
    … …  
    10871088     * @returns Pending interrupt yes/no
    10881089     * @param   pDevIns         Device instance of the APIC.
    1089      */
    1090     DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns));
     1090     * @param   idCpu           The VCPU Id.
     1091     */
     1092    DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    10911093
    10921094    /**
    … …  
    10941096     *
    10951097     * @param   pDevIns         Device instance of the APIC.
     1098     * @param   idCpu           The VCPU Id.
    10961099     * @param   u64Base         The new base.
    10971100     */
    1098     DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, uint64_t u64Base));
     1101    DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
    10991102
    11001103    /**
    … …  
    11031106     * @returns Current base.
    11041107     * @param   pDevIns         Device instance of the APIC.
    1105      */
    1106     DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns));
     1108     * @param   idCpu           The VCPU Id.
     1109     */
     1110    DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    11071111
    11081112    /**
    … …  
    11101114     *
    11111115     * @param   pDevIns         Device instance of the APIC.
    1112      * @param   idCpu           VCPU id
     1116     * @param   idCpu           The VCPU id.
    11131117     * @param   u8TPR           The new TPR.
    11141118     */

  • trunk/src/VBox/Devices/PC/DevAPIC.cpp

    r42574 r43657  
    461461{
    462462    /* for now we assume LAPIC physical id == CPU id */
    463     return VMCPUID(s->phys_id);
     463    return (VMCPUID)s->phys_id;
    464464}
    465465
    … …  
    596596
    597597
    598 PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
     598PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t val)
    599599{
    600600    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    601601    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    602     APICState *s = getLapic(pDev); /** @todo fix interface */
     602    APICState *s = getLapicById(pDev, idCpu);
    603603    Log(("apicSetBase: %016RX64\n", val));
    604604
    … …  
    640640}
    641641
    642 PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
     642PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns, VMCPUID idCpu)
    643643{
    644644    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    645645    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    646     APICState *s = getLapic(pDev); /** @todo fix interface */
     646    APICState *s = getLapicById(pDev, idCpu);
    647647    LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
    648648    return s->apicbase;
    … …  
    12291229
    12301230/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
    1231 PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
     1231PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns, VMCPUID idCpu)
    12321232{
    12331233    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    … …  
    12371237    /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
    12381238
    1239     APICState *s = getLapic(pDev); /** @todo fix interface */
     1239    APICState *s = getLapicById(pDev, idCpu);
    12401240
    12411241    /*
    … …  
    14371437
    14381438
    1439 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
     1439PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)
    14401440{
    14411441    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    … …  
    14501450    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    14511451
    1452     APICState *s = getLapic(pDev);  /** @todo fix interface */
     1452    APICState *s = getLapicById(pDev, idCpu);
    14531453
    14541454    if (!(s->spurious_vec & APIC_SV_ENABLE))

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r43387 r43657  
    862862
    863863        case MSR_IA32_APICBASE:
    864             rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
    865             if (RT_SUCCESS(rc))
    866                 rc = VINF_SUCCESS;
     864        {
     865            PVM pVM = pVCpu->CTX_SUFF(pVM);
     866            if (   (    pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1
     867                    && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
     868                || (   pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
     869                    && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
     870                    && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC)))
     871            {
     872                *puValue = pVCpu->cpum.s.Guest.msrApicBase;
     873            }
    867874            else
    868875            {
    … …  
    871878            }
    872879            break;
     880        }
    873881
    874882        case MSR_IA32_CR_PAT:
    … …  
    11221130
    11231131        case MSR_IA32_APICBASE:
    1124             rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
     1132            rc = PDMApicSetBase(pVCpu, uValue);
    11251133            if (rc != VINF_SUCCESS)
    11261134                rc = VERR_CPUM_RAISE_GP_0;

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r41965 r43657  
    5858        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
    5959        uint32_t uTagSrc;
    60         int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), &uTagSrc);
     60        int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, &uTagSrc);
    6161        AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
    6262        if (i >= 0)
    … …  
    215215 *
    216216 * @returns VBox status code.
    217  * @param   pVM             Pointer to the VM.
     217 * @param   pVM             Pointer to the VMCPU.
    218218 * @param   u64Base         The new base.
    219219 */
    220 VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base)
    221 {
     220VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base)
     221{
     222    PVM pVM = pVCpu->CTX_SUFF(pVM);
    222223    if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    223224    {
    224225        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
    225226        pdmLock(pVM);
    226         pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base);
    227         pdmUnlock(pVM);
    228         return VINF_SUCCESS;
    229     }
    230     return VERR_PDM_NO_APIC_INSTANCE;
    231 }
    232 
    233 
    234 /**
    235  * Get the APIC base.
    236  *
    237  * @returns VBox status code.
    238  * @param   pVM             Pointer to the VM.
     227        pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u64Base);
     228
     229        /* Update CPUM's copy of the APIC base. */
     230        PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
     231        Assert(pCtx);
     232        pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
     233
     234        pdmUnlock(pVM);
     235        return VINF_SUCCESS;
     236    }
     237    return VERR_PDM_NO_APIC_INSTANCE;
     238}
     239
     240
     241/**
     242 * Get the APIC base from the APIC device. This is slow and involves
     243 * taking the PDM lock, this is currently only used by CPUM to cache the APIC
     244 * base once (during init./load state), all other callers should use
     245 * PDMApicGetBase() and not this function.
     246 *
     247 * @returns VBox status code.
     248 * @param   pVM             Pointer to the VMCPU.
    239249 * @param   pu64Base        Where to store the APIC base.
    240250 */
    241 VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base)
    242 {
     251VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base)
     252{
     253    PVM pVM = pVCpu->CTX_SUFF(pVM);
    243254    if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    244255    {
    245256        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
    246257        pdmLock(pVM);
    247         *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
     258        *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
    248259        pdmUnlock(pVM);
    249260        return VINF_SUCCESS;
    … …  
    258269 *
    259270 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
    260  * @param   pDevIns         Device instance of the APIC.
     271 * @param   pVCpu           Pointer to the VMCPU.
    261272 * @param   pfPending       Pending state (out).
    262273 */
    263 VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending)
    264 {
     274VMMDECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending)
     275{
     276    PVM pVM = pVCpu->CTX_SUFF(pVM);
    265277    if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
    266278    {
    267279        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
    268280        pdmLock(pVM);
    269         *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
     281        *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
    270282        pdmUnlock(pVM);
    271283        return VINF_SUCCESS;
    … …  
    316328        *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
    317329        if (pfPending)
    318             *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
     330            *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
    319331        return VINF_SUCCESS;
    320332    }

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r43509 r43657  
    19521952            {
    19531953                RTGCPHYS GCPhysApicBase, GCPhys;
    1954                 PDMApicGetBase(pVM, &GCPhysApicBase);   /** @todo cache this */
     1954                GCPhysApicBase = pCtx->msrApicBase;
    19551955                GCPhysApicBase &= PAGE_BASE_GC_MASK;
    19561956
    … …  
    21172117            &&  pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
    21182118        {
    2119             RTGCPHYS GCPhysApicBase;
    2120             PDMApicGetBase(pVM, &GCPhysApicBase);   /** @todo cache this */
     2119            RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
    21212120            GCPhysApicBase &= PAGE_BASE_GC_MASK;
    21222121

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r43566 r43657  
    11661166        Assert((TRPMQueryTrap(pVCpu, NULL, NULL) == VERR_TRPM_NO_ACTIVE_TRAP));
    11671167
    1168         /* 
     1168        /*
    11691169         * Clear the pending event and move it over to TRPM for the rest
    11701170         * of the world to see.
    … …  
    35053505                {
    35063506                    RTGCPHYS GCPhysApicBase, GCPhys;
    3507                     PDMApicGetBase(pVM, &GCPhysApicBase);   /** @todo cache this */
     3507                    GCPhysApicBase = pCtx->msrApicBase;
    35083508                    GCPhysApicBase &= PAGE_BASE_GC_MASK;
    35093509
    … …  
    35363536                {
    35373537                    RTGCPHYS GCPhysApicBase, GCPhys;
    3538                     PDMApicGetBase(pVM, &GCPhysApicBase);   /* @todo cache this */
     3538                    GCPhysApicBase = pCtx->msrApicBase;
    35393539                    GCPhysApicBase &= PAGE_BASE_GC_MASK;
    35403540
    … …  
    40484048            {
    40494049                RTGCPHYS GCPhysApicBase;
    4050                 PDMApicGetBase(pVM, &GCPhysApicBase);   /* @todo cache this */
     4050                GCPhysApicBase = pCtx->msrApicBase;
    40514051                GCPhysApicBase &= PAGE_BASE_GC_MASK;
    40524052                if (GCPhys == GCPhysApicBase + 0x80)
    … …  
    41084108            &&  (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
    41094109        {
    4110             RTGCPHYS GCPhysApicBase;
    4111             PDMApicGetBase(pVM, &GCPhysApicBase);   /* @todo cache this */
     4110            RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
    41124111            GCPhysApicBase &= PAGE_BASE_GC_MASK;
    41134112            if (GCPhys == GCPhysApicBase + 0x80)
    … …  
    46484647            case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
    46494648            {
    4650                 RTGCPHYS GCPhys;
    4651                 PDMApicGetBase(pVM, &GCPhys);
     4649                RTGCPHYS GCPhys = pCtx->msrApicBase;
    46524650                GCPhys &= PAGE_BASE_GC_MASK;
    46534651                GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r43387 r43657  
    4040#include <VBox/vmm/cpumctx-v1_6.h>
    4141#include <VBox/vmm/pgm.h>
     42#include <VBox/vmm/pdmapi.h>
    4243#include <VBox/vmm/mm.h>
    4344#include <VBox/vmm/selm.h>
    … …  
    14901491{
    14911492    /** @todo anything different for VCPU > 0? */
    1492     PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
     1493    PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
    14931494
    14941495    /*
    … …  
    15751576    */
    15761577    pCtx->msrEFER                   = 0;
     1578
     1579    /*
     1580     * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
     1581     * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
     1582     */
     1583    PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
    15771584}
    15781585
    … …  
    15911598
    15921599#ifdef VBOX_WITH_CRASHDUMP_MAGIC
    1593         PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
     1600        PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
    15941601
    15951602        /* Magic marker for searching in crash dumps. */
    … …  
    27022709    }
    27032710
    2704     /* Notify PGM of the NXE states in case they've changed. */
    27052711    for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
     2712    {
     2713        /* Notify PGM of the NXE states in case they've changed. */
    27062714        PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
     2715
     2716        /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
     2717        PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
     2718    }
    27072719    return VINF_SUCCESS;
    27082720}
    … …  
    30643076    pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
    30653077
    3066     PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
     3078    PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
    30673079    cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
    30683080}

  • trunk/src/VBox/VMM/VMMR3/VM.cpp

    r43387 r43657  
    28582858        CPUMR3Reset(pVM);
    28592859    }
    2860     CPUMR3ResetCpu(pVCpu);
    28612860    if (pVCpu->idCpu == 0)
    28622861    {

  • trunk/src/VBox/VMM/include/CPUMInternal.mac

    r41932 r43657  
    196196    .Hyper.msrSFMASK          resb    8
    197197    .Hyper.msrKERNELGSBASE    resb    8
     198    .Hyper.msrApicBase        resb    8
    198199
    199200    ;
    … …  
    416417    .Guest.msrSFMASK          resb    8
    417418    .Guest.msrKERNELGSBASE    resb    8
     419    .Guest.msrApicBase        resb    8
    418420
    419421

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r40920 r43657  
    488488    PPDMDEVINSR3                    pDevInsR3;
    489489    /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    490     DECLR3CALLBACKMEMBER(int,       pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
     490    DECLR3CALLBACKMEMBER(int,       pfnGetInterruptR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
    491491    /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
    492     DECLR3CALLBACKMEMBER(bool,      pfnHasPendingIrqR3,(PPDMDEVINS pDevIns));
     492    DECLR3CALLBACKMEMBER(bool,      pfnHasPendingIrqR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    493493    /** @copydoc PDMAPICREG::pfnSetBaseR3 */
    494     DECLR3CALLBACKMEMBER(void,      pfnSetBaseR3,(PPDMDEVINS pDevIns, uint64_t u64Base));
     494    DECLR3CALLBACKMEMBER(void,      pfnSetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
    495495    /** @copydoc PDMAPICREG::pfnGetBaseR3 */
    496     DECLR3CALLBACKMEMBER(uint64_t,  pfnGetBaseR3,(PPDMDEVINS pDevIns));
     496    DECLR3CALLBACKMEMBER(uint64_t,  pfnGetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    497497    /** @copydoc PDMAPICREG::pfnSetTPRR3 */
    498498    DECLR3CALLBACKMEMBER(void,      pfnSetTPRR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));
    … …  
    512512    PPDMDEVINSR0                    pDevInsR0;
    513513    /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    514     DECLR0CALLBACKMEMBER(int,       pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
     514    DECLR0CALLBACKMEMBER(int,       pfnGetInterruptR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
    515515    /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
    516     DECLR0CALLBACKMEMBER(bool,      pfnHasPendingIrqR0,(PPDMDEVINS pDevIns));
     516    DECLR0CALLBACKMEMBER(bool,      pfnHasPendingIrqR0,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    517517    /** @copydoc PDMAPICREG::pfnSetBaseR3 */
    518     DECLR0CALLBACKMEMBER(void,      pfnSetBaseR0,(PPDMDEVINS pDevIns, uint64_t u64Base));
     518    DECLR0CALLBACKMEMBER(void,      pfnSetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
    519519    /** @copydoc PDMAPICREG::pfnGetBaseR3 */
    520     DECLR0CALLBACKMEMBER(uint64_t,  pfnGetBaseR0,(PPDMDEVINS pDevIns));
     520    DECLR0CALLBACKMEMBER(uint64_t,  pfnGetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    521521    /** @copydoc PDMAPICREG::pfnSetTPRR3 */
    522522    DECLR0CALLBACKMEMBER(void,      pfnSetTPRR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));
    … …  
    536536    PPDMDEVINSRC                    pDevInsRC;
    537537    /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
    538     DECLRCCALLBACKMEMBER(int,       pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
     538    DECLRCCALLBACKMEMBER(int,       pfnGetInterruptRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
    539539    /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
    540     DECLRCCALLBACKMEMBER(bool,      pfnHasPendingIrqRC,(PPDMDEVINS pDevIns));
     540    DECLRCCALLBACKMEMBER(bool,      pfnHasPendingIrqRC,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    541541    /** @copydoc PDMAPICREG::pfnSetBaseR3 */
    542     DECLRCCALLBACKMEMBER(void,      pfnSetBaseRC,(PPDMDEVINS pDevIns, uint64_t u64Base));
     542    DECLRCCALLBACKMEMBER(void,      pfnSetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
    543543    /** @copydoc PDMAPICREG::pfnGetBaseR3 */
    544     DECLRCCALLBACKMEMBER(uint64_t,  pfnGetBaseRC,(PPDMDEVINS pDevIns));
     544    DECLRCCALLBACKMEMBER(uint64_t,  pfnGetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu));
    545545    /** @copydoc PDMAPICREG::pfnSetTPRR3 */
    546546    DECLRCCALLBACKMEMBER(void,      pfnSetTPRRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));

  • trunk/src/recompiler/VBoxRecompiler.c

    r43394 r43657  
    44644464{
    44654465    uint64_t u64;
    4466     int rc = PDMApicGetBase(env->pVM, &u64);
     4466    int rc = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64);
    44674467    if (RT_SUCCESS(rc))
    44684468    {
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