Changeset 44373 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Jan 25, 2013 12:19:29 PM (12 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/HMAll.cpp
r44195 r44373 67 67 * @param GCVirt Page to invalidate 68 68 */ 69 VMM DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)69 VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt) 70 70 { 71 71 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual); … … 90 90 * @param pVCpu Pointer to the VMCPU. 91 91 */ 92 VMM DECL(int) HMFlushTLB(PVMCPU pVCpu)92 VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu) 93 93 { 94 94 LogFlow(("HMFlushTLB\n")); … … 193 193 * @param GCVirt Page to invalidate 194 194 */ 195 VMM DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCPtr)195 VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCPtr) 196 196 { 197 197 VMCPUID idCurCpu = VMMGetCpuId(pVM); … … 226 226 * @param pVM Pointer to the VM. 227 227 */ 228 VMM DECL(int) HMFlushTLBOnAllVCpus(PVM pVM)228 VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM) 229 229 { 230 230 if (pVM->cCpus == 1) … … 260 260 * @param pVM Pointer to the VM. 261 261 */ 262 VMM DECL(bool) HMIsNestedPagingActive(PVM pVM)262 VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM) 263 263 { 264 264 return HMIsEnabled(pVM) && pVM->hm.s.fNestedPaging; … … 271 271 * @param pVM Pointer to the VM. 272 272 */ 273 VMM DECL(PGMMODE) HMGetShwPagingMode(PVM pVM)273 VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM) 274 274 { 275 275 Assert(HMIsNestedPagingActive(pVM)); … … 290 290 * @param GCPhys Page to invalidate 291 291 */ 292 VMM DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)292 VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys) 293 293 { 294 294 if (!HMIsNestedPagingActive(pVM)) … … 336 336 * @param pVM Pointer to the VM. 337 337 */ 338 VMM DECL(bool) HMHasPendingIrq(PVM pVM)338 VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM) 339 339 { 340 340 PVMCPU pVCpu = VMMGetCpu(pVM); … … 349 349 * @param pVCpu Pointer to the VMCPU. 350 350 */ 351 VMM DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)351 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu) 352 352 { 353 353 return &pVCpu->hm.s.aPdpes[0]; -
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r44171 r44373 608 608 * @returns VBox status code. 609 609 */ 610 VMMR0 DECL(int) HMR0Init(void)610 VMMR0_INT_DECL(int) HMR0Init(void) 611 611 { 612 612 /* … … 709 709 * @returns VBox status code. 710 710 */ 711 VMMR0 DECL(int) HMR0Term(void)711 VMMR0_INT_DECL(int) HMR0Term(void) 712 712 { 713 713 int rc; … … 1003 1003 * @param pVM Pointer to the VM. 1004 1004 */ 1005 VMMR0 DECL(int) HMR0EnableAllCpus(PVM pVM)1005 VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM) 1006 1006 { 1007 1007 /* Make sure we don't touch hm after we've disabled hm in … … 1182 1182 * @param pVM Pointer to the VM. 1183 1183 */ 1184 VMMR0 DECL(int) HMR0InitVM(PVM pVM)1184 VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM) 1185 1185 { 1186 1186 AssertReturn(pVM, VERR_INVALID_PARAMETER); … … 1279 1279 * @param pVM Pointer to the VM. 1280 1280 */ 1281 VMMR0 DECL(int) HMR0TermVM(PVM pVM)1281 VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM) 1282 1282 { 1283 1283 Log(("HMR0TermVM: %p\n", pVM)); … … 1317 1317 * @param pVM Pointer to the VM. 1318 1318 */ 1319 VMMR0 DECL(int) HMR0SetupVM(PVM pVM)1319 VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM) 1320 1320 { 1321 1321 Log(("HMR0SetupVM: %p\n", pVM)); … … 1374 1374 * @remarks This is called with preemption disabled. 1375 1375 */ 1376 VMMR0 DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)1376 VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu) 1377 1377 { 1378 1378 RTCPUID idCpu = RTMpCpuId(); … … 1449 1449 * counterpart. 1450 1450 */ 1451 VMMR0 DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)1451 VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu) 1452 1452 { 1453 1453 int rc; … … 1522 1522 * HMR0Enter. 1523 1523 */ 1524 VMMR0 DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)1524 VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu) 1525 1525 { 1526 1526 #ifdef VBOX_STRICT … … 1554 1554 * @param pCtx Pointer to the guest CPU context. 1555 1555 */ 1556 VMMR0 DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)1556 VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 1557 1557 { 1558 1558 STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack); … … 1571 1571 * @param pCtx Pointer to the guest CPU context. 1572 1572 */ 1573 VMMR0 DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)1573 VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 1574 1574 { 1575 1575 STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack); … … 1586 1586 * @param pVM Pointer to the VM. 1587 1587 */ 1588 VMMR0 DECL(int) HMR0TestSwitcher3264(PVM pVM)1588 VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM) 1589 1589 { 1590 1590 PVMCPU pVCpu = &pVM->aCpus[0]; … … 1610 1610 * @returns Suspend pending or not. 1611 1611 */ 1612 VMMR0 DECL(bool) HMR0SuspendPending(void)1612 VMMR0_INT_DECL(bool) HMR0SuspendPending(void) 1613 1613 { 1614 1614 return ASMAtomicReadBool(&g_HvmR0.fSuspended); … … 1654 1654 * @param cbSize Read size. 1655 1655 */ 1656 VMMR0DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize) 1656 VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, 1657 unsigned uPort, unsigned uAndVal, unsigned cbSize) 1657 1658 { 1658 1659 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ; … … 1675 1676 * @param cbSize Read size. 1676 1677 */ 1677 VMMR0DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize) 1678 VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, 1679 unsigned uPort, unsigned uAndVal, unsigned cbSize) 1678 1680 { 1679 1681 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE; … … 1696 1698 * @param pfVTxDisabled Where to store whether VT-x was disabled or not. 1697 1699 */ 1698 VMMR0 DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)1700 VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled) 1699 1701 { 1700 1702 Assert(!(ASMGetFlags() & X86_EFL_IF) || !RTThreadPreemptIsEnabled(NIL_RTTHREAD)); … … 1760 1762 * @param fVTxDisabled Whether VT-x was disabled or not. 1761 1763 */ 1762 VMMR0 DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)1764 VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled) 1763 1765 { 1764 1766 Assert(!(ASMGetFlags() & X86_EFL_IF)); -
trunk/src/VBox/VMM/VMMR3/CSAM.cpp
r44362 r44373 36 36 #include <VBox/vmm/trpm.h> 37 37 #include <VBox/vmm/cfgm.h> 38 #include <VBox/vmm/ssm.h> 38 39 #include <VBox/param.h> 39 40 #include <iprt/avl.h> … … 42 43 #include "CSAMInternal.h" 43 44 #include <VBox/vmm/vm.h> 45 #include <VBox/vmm/uvm.h> 44 46 #include <VBox/dbg.h> 45 47 #include <VBox/err.h> 46 #include <VBox/vmm/ssm.h>47 48 #include <VBox/log.h> 48 49 #include <iprt/assert.h> … … 2685 2686 * Query CSAM state (enabled/disabled) 2686 2687 * 2687 * @returns 0 - disabled, 1 - enabled 2688 * @param pVM Pointer to the VM. 2689 */ 2690 VMMR3DECL(int) CSAMR3IsEnabled(PVM pVM) 2691 { 2692 return pVM->fCSAMEnabled; 2688 * @returns true if enabled, false otherwise. 2689 * @param pUVM The user mode VM handle. 2690 */ 2691 VMMR3DECL(bool) CSAMR3IsEnabled(PUVM pUVM) 2692 { 2693 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 2694 PVM pVM = pUVM->pVM; 2695 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 2696 return CSAMIsEnabled(pVM); 2693 2697 } 2694 2698 -
trunk/src/VBox/VMM/VMMR3/DBGF.cpp
r43387 r44373 80 80 #include "DBGFInternal.h" 81 81 #include <VBox/vmm/vm.h> 82 #include <VBox/vmm/uvm.h> 82 83 #include <VBox/err.h> 83 84 … … 1116 1117 } 1117 1118 1119 1120 /** 1121 * Inject an NMI into a running VM (only VCPU 0!) 1122 * 1123 * @returns VBox status code. 1124 * @param pVM Pointer to the VM. 1125 */ 1126 VMMR3DECL(int) DBGFR3InjectNMI(PUVM pUVM, VMCPUID idCpu) 1127 { 1128 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE); 1129 PVM pVM = pUVM->pVM; 1130 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE); 1131 AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID); 1132 1133 /** @todo Implement generic NMI injection. */ 1134 if (!HMIsEnabled(pVM)) 1135 return VERR_NOT_SUP_IN_RAW_MODE; 1136 1137 VMCPU_FF_SET(&pVM->aCpus[idCpu], VMCPU_FF_INTERRUPT_NMI); 1138 return VINF_SUCCESS; 1139 } 1140 -
trunk/src/VBox/VMM/VMMR3/EM.cpp
r44362 r44373 63 63 #include "EMInternal.h" 64 64 #include <VBox/vmm/vm.h> 65 #include <VBox/vmm/uvm.h> 65 66 #include <VBox/vmm/cpumdis.h> 66 67 #include <VBox/dis.h> … … 666 667 667 668 /** 669 * Checks if raw ring-3 execute mode is enabled. 670 * 671 * @returns true if enabled, false if disabled. 672 * @param pUVM The user mode VM handle. 673 */ 674 VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM) 675 { 676 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 677 PVM pVM = pUVM->pVM; 678 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 679 return EMIsRawRing3Enabled(pVM); 680 } 681 682 683 /** 684 * Checks if raw ring-0 execute mode is enabled. 685 * 686 * @returns true if enabled, false if disabled. 687 * @param pUVM The user mode VM handle. 688 */ 689 VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM) 690 { 691 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 692 PVM pVM = pUVM->pVM; 693 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 694 return EMIsRawRing0Enabled(pVM); 695 } 696 697 698 /** 668 699 * Raise a fatal error. 669 700 * -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r44362 r44373 39 39 #include "HMInternal.h" 40 40 #include <VBox/vmm/vm.h> 41 #include <VBox/vmm/uvm.h> 41 42 #include <VBox/err.h> 42 43 #include <VBox/param.h> … … 284 285 * @param pVM Pointer to the VM. 285 286 */ 286 VMMR3 DECL(int) HMR3Init(PVM pVM)287 VMMR3_INT_DECL(int) HMR3Init(PVM pVM) 287 288 { 288 289 LogFlow(("HMR3Init\n")); … … 1484 1485 * @param pVM The VM. 1485 1486 */ 1486 VMMR3 DECL(void) HMR3Relocate(PVM pVM)1487 VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM) 1487 1488 { 1488 1489 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0))); … … 1547 1548 * @param pVM Pointer to the VM. 1548 1549 */ 1549 VMMR3 DECL(bool) HMR3IsAllowed(PVM pVM)1550 VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM) 1550 1551 { 1551 1552 return pVM->hm.s.fAllowed; … … 1564 1565 * @param enmGuestMode New guest paging mode. 1565 1566 */ 1566 VMMR3 DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)1567 VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode) 1567 1568 { 1568 1569 /* Ignore page mode changes during state loading. */ … … 1619 1620 * @param pVM Pointer to the VM. 1620 1621 */ 1621 VMMR3 DECL(int) HMR3Term(PVM pVM)1622 VMMR3_INT_DECL(int) HMR3Term(PVM pVM) 1622 1623 { 1623 1624 if (pVM->hm.s.vmx.pRealModeTSS) … … 1675 1676 * @param pVCpu The CPU to reset. 1676 1677 */ 1677 VMMR3 DECL(void) HMR3ResetCpu(PVMCPU pVCpu)1678 VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu) 1678 1679 { 1679 1680 /* On first entry we'll sync everything. */ … … 1712 1713 * @param pVM Pointer to the VM. 1713 1714 */ 1714 VMMR3 DECL(void) HMR3Reset(PVM pVM)1715 VMMR3_INT_DECL(void) HMR3Reset(PVM pVM) 1715 1716 { 1716 1717 LogFlow(("HMR3Reset:\n")); … … 1831 1832 * @param cbPatchMem Size of the memory range. 1832 1833 */ 1833 VMMR3 DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)1834 VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem) 1834 1835 { 1835 1836 VM_ASSERT_EMT(pVM); … … 1855 1856 * @param cbPatchMem Size of the memory range. 1856 1857 */ 1857 VMMR3 DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)1858 VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem) 1858 1859 { 1859 1860 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem)); … … 2289 2290 * @param pCtx Pointer to the guest CPU context. 2290 2291 */ 2291 VMMR3 DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)2292 VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 2292 2293 { 2293 2294 NOREF(pCtx); … … 2307 2308 * @param pCtx Partial VM execution context. 2308 2309 */ 2309 VMMR3 DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)2310 VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx) 2310 2311 { 2311 2312 PVMCPU pVCpu = VMMGetCpu(pVM); … … 2523 2524 * @param pCtx VM execution context. 2524 2525 */ 2525 VMMR3 DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)2526 VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx) 2526 2527 { 2527 2528 /* … … 2546 2547 * @param pVCpu Pointer to the current VMCPU. 2547 2548 */ 2548 VMMR3 DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)2549 VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu) 2549 2550 { 2550 2551 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST; … … 2557 2558 * @param pVCpu Pointer to the VMCPU. 2558 2559 */ 2559 VMMR3 DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)2560 VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu) 2560 2561 { 2561 2562 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST; … … 2569 2570 * @param pVCpu Pointer to the VMCPU. 2570 2571 */ 2571 VMMR3 DECL(bool) HMR3IsActive(PVMCPU pVCpu)2572 VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu) 2572 2573 { 2573 2574 return pVCpu->hm.s.fActive; … … 2579 2580 * 2580 2581 * @returns true if nested paging is being used, otherwise false. 2581 * @param pVM Pointer to the VM. 2582 */ 2583 VMMR3DECL(bool) HMR3IsNestedPagingActive(PVM pVM) 2584 { 2582 * @param pUVM The user mode VM handle. 2583 */ 2584 VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM) 2585 { 2586 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 2587 PVM pVM = pUVM->pVM; 2588 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 2589 return HMIsEnabled(pVM); 2590 } 2591 2592 2593 /** 2594 * Checks if we are currently using nested paging. 2595 * 2596 * @returns true if nested paging is being used, otherwise false. 2597 * @param pUVM The user mode VM handle. 2598 */ 2599 VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM) 2600 { 2601 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 2602 PVM pVM = pUVM->pVM; 2603 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 2585 2604 return pVM->hm.s.fNestedPaging; 2586 2605 } … … 2591 2610 * 2592 2611 * @returns true if VPID is being used, otherwise false. 2593 * @param pVM Pointer to the VM. 2594 */ 2595 VMMR3DECL(bool) HMR3IsVPIDActive(PVM pVM) 2596 { 2612 * @param pUVM The user mode VM handle. 2613 */ 2614 VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM) 2615 { 2616 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false); 2617 PVM pVM = pUVM->pVM; 2618 VM_ASSERT_VALID_EXT_RETURN(pVM, false); 2597 2619 return pVM->hm.s.vmx.fVpid; 2598 2620 } … … 2605 2627 * @param pVM Pointer to the VM. 2606 2628 */ 2607 VMMR3 DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)2629 VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu) 2608 2630 { 2609 2631 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending; … … 2617 2639 * @param pVM Pointer to the VM. 2618 2640 */ 2619 VMMR3 DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)2641 VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM) 2620 2642 { 2621 2643 return HMIsEnabled(pVM) … … 2639 2661 * @param pCtx Pointer to the guest CPU context. 2640 2662 */ 2641 VMMR3 DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)2663 VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 2642 2664 { 2643 2665 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType; … … 2686 2708 2687 2709 /** 2688 * Inject an NMI into a running VM (only VCPU 0!)2689 *2690 * @returns VBox status code.2691 * @param pVM Pointer to the VM.2692 */2693 VMMR3DECL(int) HMR3InjectNMI(PVM pVM)2694 {2695 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);2696 return VINF_SUCCESS;2697 }2698 2699 2700 /**2701 2710 * Check fatal VT-x/AMD-V error and produce some meaningful 2702 2711 * log release message. … … 2705 2714 * @param iStatusCode VBox status code. 2706 2715 */ 2707 VMMR3 DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)2716 VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode) 2708 2717 { 2709 2718 for (VMCPUID i = 0; i < pVM->cCpus; i++)
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