VirtualBox

Changeset 44375 in vbox for trunk


Ignore:
Timestamp:
Jan 25, 2013 12:41:24 PM (12 years ago)
Author:
vboxsync
Message:

EM: pVM -> pUVM for main, mark as many as possible interfaces module internal.

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/em.h

    r44373 r44375  
    9595} EMCODETYPE;
    9696
    97 VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
    98 VMMDECL(void)    EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
     97VMM_INT_DECL(EMSTATE)          EMGetState(PVMCPU pVCpu);
     98VMM_INT_DECL(void)              EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
    9999
    100100/** @name Callback handlers for instruction emulation functions.
    … …  
    152152#define EMIsSupervisorCodeRecompiled(pVM) ((pVM)->fRecompileSupervisor)
    153153
    154 VMMDECL(void)           EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
    155 VMMDECL(RTGCUINTPTR)    EMGetInhibitInterruptsPC(PVMCPU pVCpu);
    156 VMMDECL(int)            EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
    157 VMMDECL(int)            EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
    158                                               PDISCPUSTATE pDISState, unsigned *pcbInstr);
    159 VMMDECL(VBOXSTRICTRC)   EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
    160 VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
    161 VMMDECL(VBOXSTRICTRC)   EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault, EMCODETYPE enmCodeType);
     154VMMDECL(void)                   EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
     155VMMDECL(RTGCUINTPTR)            EMGetInhibitInterruptsPC(PVMCPU pVCpu);
     156VMM_INT_DECL(int)               EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
     157VMM_INT_DECL(int)               EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
     158                                                      PDISCPUSTATE pDISState, unsigned *pcbInstr);
     159VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
     160VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
     161VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
     162                                                                 RTGCPTR pvFault, EMCODETYPE enmCodeType);
    162163
    163164#ifdef IN_RC
    164 VMMDECL(int)            EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     165VMM_INT_DECL(int)               EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    165166#endif
    166167
    167 VMMDECL(int)            EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    168 VMMDECL(int)            EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    169 VMMDECL(int)            EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    170 VMMDECL(int)            EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    171 VMMDECL(VBOXSTRICTRC)   EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
    172 VMMDECL(VBOXSTRICTRC)   EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    173 VMMDECL(int)            EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    174 VMMDECL(int)            EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
    175 VMMDECL(int)            EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
    176 VMMDECL(int)            EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
    177 VMMDECL(int)            EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
    178 VMMDECL(int)            EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
    179 VMMDECL(int)            EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
     168VMM_INT_DECL(int)               EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     169VMM_INT_DECL(int)               EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     170VMM_INT_DECL(int)               EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     171VMM_INT_DECL(int)               EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
     172VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
     173VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     174VMM_INT_DECL(int)               EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     175VMM_INT_DECL(int)               EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
     176VMM_INT_DECL(int)               EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
     177VMM_INT_DECL(int)               EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
     178VMM_INT_DECL(int)               EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
     179VMM_INT_DECL(int)               EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
     180VMM_INT_DECL(int)               EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
    180181#ifndef VBOX_WITH_IEM
    181 VMMDECL(int)            EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    182 VMMDECL(int)            EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     182VMM_INT_DECL(int)               EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
     183VMM_INT_DECL(int)               EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
    183184#endif /* !VBOX_WITH_IEM */
    184 VMM_INT_DECL(bool)      EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
    185 VMM_INT_DECL(int)       EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx);
    186 VMM_INT_DECL(int)       EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
     185VMM_INT_DECL(bool)              EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
     186VMM_INT_DECL(int)               EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx);
     187VMM_INT_DECL(int)               EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
    187188
    188189/** @name Assembly routines
    … …  
    214215/** @name REM locking routines
    215216 * @{ */
    216 VMMDECL(void)       EMRemUnlock(PVM pVM);
    217 VMMDECL(void)       EMRemLock(PVM pVM);
    218 VMMDECL(bool)       EMRemIsLockOwner(PVM pVM);
    219 VMMDECL(int)        EMRemTryLock(PVM pVM);
     217VMMDECL(void)                   EMRemUnlock(PVM pVM);
     218VMMDECL(void)                   EMRemLock(PVM pVM);
     219VMMDECL(bool)                   EMRemIsLockOwner(PVM pVM);
     220VMM_INT_DECL(int)               EMRemTryLock(PVM pVM);
    220221/** @} */
    221222
    … …  
    225226 * @{
    226227 */
    227 
    228 VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM);
    229 VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM);
    230 
    231 VMMR3DECL(int)          EMR3Init(PVM pVM);
    232 VMMR3DECL(void)         EMR3Relocate(PVM pVM);
    233 VMMR3DECL(void)         EMR3ResetCpu(PVMCPU pVCpu);
    234 VMMR3DECL(void)         EMR3Reset(PVM pVM);
    235 VMMR3DECL(int)          EMR3Term(PVM pVM);
    236 VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
    237 VMMR3DECL(int)          EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
    238 VMMR3DECL(int)          EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
    239 VMMR3DECL(int)          EMR3Interpret(PVM pVM);
    240 VMMR3_INT_DECL(int)     EMR3NotifyResume(PVM pVM);
    241 VMMR3_INT_DECL(int)     EMR3NotifySuspend(PVM pVM);
    242 VMMR3_INT_DECL(bool)    EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu);
    243228
    244229/**
    … …  
    261246    EMEXECPOLICY_32BIT_HACK = 0x7fffffff
    262247} EMEXECPOLICY;
    263 
    264 VMMR3DECL(int)      EMR3SetExecutionPolicy(PVM pVM, EMEXECPOLICY enmPolicy, bool fEnforce);
     248VMMR3DECL(int)                  EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce);
     249VMMR3DECL(bool)                 EMR3IsRawRing3Enabled(PUVM pUVM);
     250VMMR3DECL(bool)                 EMR3IsRawRing0Enabled(PUVM pUVM);
     251
     252VMMR3_INT_DECL(int)             EMR3Init(PVM pVM);
     253VMMR3_INT_DECL(void)            EMR3Relocate(PVM pVM);
     254VMMR3_INT_DECL(void)            EMR3ResetCpu(PVMCPU pVCpu);
     255VMMR3_INT_DECL(void)            EMR3Reset(PVM pVM);
     256VMMR3_INT_DECL(int)             EMR3Term(PVM pVM);
     257VMMR3DECL(DECLNORETURN(void))   EMR3FatalError(PVMCPU pVCpu, int rc);
     258VMMR3_INT_DECL(int)             EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
     259VMMR3_INT_DECL(int)             EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
     260VMMR3_INT_DECL(int)             EMR3NotifyResume(PVM pVM);
     261VMMR3_INT_DECL(int)             EMR3NotifySuspend(PVM pVM);
     262VMMR3_INT_DECL(bool)            EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu);
    265263/** @} */
    266264#endif /* IN_RING3 */
    267265
    268 
    269 #ifdef IN_RC
    270 /** @defgroup grp_em_gc     The EM Guest Context API
    271  * @ingroup grp_em
    272  * @{
    273  */
    274 VMMRCDECL(int)      EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
    275 /** @} */
    276 #endif /* IN_RC */
    277 
    278266/** @} */
    279267

  • trunk/src/VBox/Main/src-client/MachineDebuggerImpl.cpp

    r44373 r44375  
    215215            if (SUCCEEDED(hrc))
    216216            {
    217                 int vrc = EMR3SetExecutionPolicy(ptrVM.raw(), EMEXECPOLICY_RECOMPILE_RING3, RT_BOOL(aEnable));
     217                int vrc = EMR3SetExecutionPolicy(ptrVM.rawUVM(), EMEXECPOLICY_RECOMPILE_RING3, RT_BOOL(aEnable));
    218218                if (RT_FAILURE(vrc))
    219219                    hrc = setError(VBOX_E_VM_ERROR, tr("EMR3SetExecutionPolicy failed with %Rrc"), vrc);
    … …  
    272272            if (SUCCEEDED(hrc))
    273273            {
    274                 int vrc = EMR3SetExecutionPolicy(ptrVM.raw(), EMEXECPOLICY_RECOMPILE_RING0, RT_BOOL(aEnable));
     274                int vrc = EMR3SetExecutionPolicy(ptrVM.rawUVM(), EMEXECPOLICY_RECOMPILE_RING0, RT_BOOL(aEnable));
    275275                if (RT_FAILURE(vrc))
    276276                    hrc = setError(VBOX_E_VM_ERROR, tr("EMR3SetExecutionPolicy failed with %Rrc"), vrc);

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r44266 r44375  
    118118 * @param   pVCpu         Pointer to the VMCPU.
    119119 */
    120 VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu)
     120VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
    121121{
    122122    return pVCpu->em.s.enmState;
    … …  
    128128 * @param   pVCpu         Pointer to the VMCPU.
    129129 */
    130 VMMDECL(void)    EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
     130VMM_INT_DECL(void)    EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
    131131{
    132132    /* Only allowed combination: */
    … …  
    295295 * @param   pVM         Pointer to the VM.
    296296 */
    297 VMMDECL(int) EMRemTryLock(PVM pVM)
     297VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
    298298{
    299299#ifdef VBOX_WITH_REM
    … …  
    411411 * @param   pcbInstr        Where to return the instruction size. (optional)
    412412 */
    413 VMMDECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
     413VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
    414414{
    415415    PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
    … …  
    447447 * @param   pcbInstr        Where to return the instruction size. (optional)
    448448 */
    449 VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
    450                                    PDISCPUSTATE pDis, unsigned *pcbInstr)
     449VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
     450                                        PDISCPUSTATE pDis, unsigned *pcbInstr)
    451451{
    452452    Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
    … …  
    680680 *          to worry about e.g. invalid modrm combinations (!)
    681681 */
    682 VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
     682VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    683683{
    684684    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    809809 *          to worry about e.g. invalid modrm combinations (!)
    810810 */
    811 VMMDECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
     811VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
    812812{
    813813    LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    … …  
    951951 *          Make sure this can't happen!! (will add some assertions/checks later)
    952952 */
    953 VMMDECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
    954                                                        RTGCPTR pvFault, EMCODETYPE enmCodeType)
     953VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
     954                                                            RTGCPTR pvFault, EMCODETYPE enmCodeType)
    955955{
    956956    LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    … …  
    10491049 *
    10501050 */
    1051 VMMDECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1051VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    10521052{
    10531053    RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
    … …  
    11191119 *
    11201120 */
    1121 VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1121VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    11221122{
    11231123    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    11471147 *
    11481148 */
    1149 VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1149VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    11501150{
    11511151    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    11771177 *
    11781178 */
    1179 VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
     1179VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
    11801180{
    11811181    Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
    … …  
    12151215 *
    12161216 */
    1217 VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1217VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    12181218{
    12191219    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    12421242 * MWAIT Emulation.
    12431243 */
    1244 VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1244VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    12451245{
    12461246    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    12811281 * MONITOR Emulation.
    12821282 */
    1283 VMMDECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     1283VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    12841284{
    12851285    uint32_t u32Dummy, u32ExtFeatures, cpl;
    … …  
    13191319 *
    13201320 */
    1321 VMMDECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
     1321VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
    13221322{
    13231323    /** @todo is addr always a flat linear address or ds based
    … …  
    14961496 *
    14971497 */
    1498 VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
     1498VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
    14991499{
    15001500    uint64_t val;
    … …  
    15271527 *
    15281528 */
    1529 VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
     1529VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
    15301530{
    15311531    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    15481548 *
    15491549 */
    1550 VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
     1550VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
    15511551{
    15521552    NOREF(pVM);
    … …  
    15701570 *
    15711571 */
    1572 VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
     1572VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
    15731573{
    15741574    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    16031603 *
    16041604 */
    1605 VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
     1605VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
    16061606{
    16071607    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    … …  
    16421642 *
    16431643 */
    1644 VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
     1644VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
    16451645{
    16461646    uint64_t val64;
    … …  
    34953495 * @param   pRegFrame   The register frame.
    34963496 */
    3497 VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     3497VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    34983498{
    34993499    NOREF(pVM);
    … …  
    35423542 * @param   pRegFrame   The register frame.
    35433543 */
    3544 VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     3544VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
    35453545{
    35463546    Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));

  • trunk/src/VBox/VMM/VMMR3/EM.cpp

    r44373 r44375  
    104104 * @param   pVM         Pointer to the VM.
    105105 */
    106 VMMR3DECL(int) EMR3Init(PVM pVM)
     106VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
    107107{
    108108    LogFlow(("EMR3Init\n"));
    … …  
    422422 * @param   pVM     Pointer to the VM.
    423423 */
    424 VMMR3DECL(void) EMR3Relocate(PVM pVM)
     424VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
    425425{
    426426    LogFlow(("EMR3Relocate\n"));
    … …  
    441441 * @param   pVCpu   Pointer to the VMCPU.
    442442 */
    443 VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
     443VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
    444444{
    445445    pVCpu->em.s.fForceRAW = false;
    … …  
    461461 * @param   pVM         Pointer to the VM.
    462462 */
    463 VMMR3DECL(void) EMR3Reset(PVM pVM)
     463VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
    464464{
    465465    Log(("EMR3Reset: \n"));
    … …  
    478478 * @param   pVM         Pointer to the VM.
    479479 */
    480 VMMR3DECL(int) EMR3Term(PVM pVM)
     480VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
    481481{
    482482    AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
    … …  
    652652 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
    653653 *
    654  * @param   pVM             Pointer to the VM.
     654 * @param   pUVM            The user mode VM handle.
    655655 * @param   enmPolicy       The scheduling policy to change.
    656656 * @param   fEnforce        Whether to enforce the policy or not.
    657657 */
    658 VMMR3DECL(int) EMR3SetExecutionPolicy(PVM pVM, EMEXECPOLICY enmPolicy, bool fEnforce)
    659 {
    660     VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
     658VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
     659{
     660    UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
     661    VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
    661662    AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
    662663
    663664    struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
    664     return VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
     665    return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
    665666}
    666667
    … …  
    19331934 * @param   pVCpu       Pointer to the VMCPU.
    19341935 */
    1935 VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
     1936VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
    19361937{
    19371938    Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s)  enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",

  • trunk/src/VBox/VMM/VMMR3/EMRaw.cpp

    r44362 r44375  
    11931193 * @param   pVCpu       Pointer to the VMCPU.
    11941194 */
    1195 VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
     1195VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
    11961196{
    11971197    int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);

  • trunk/src/VBox/VMM/testcase/tstAnimate.cpp

    r44346 r44375  
    879879                    if (RT_SUCCESS(rc))
    880880                    {
    881                         rc = EMR3SetExecutionPolicy(pVM, EMEXECPOLICY_RECOMPILE_RING0, true); AssertReleaseRC(rc);
    882                         rc = EMR3SetExecutionPolicy(pVM, EMEXECPOLICY_RECOMPILE_RING3, true); AssertReleaseRC(rc);
     881                        rc = EMR3SetExecutionPolicy(pUVM, EMEXECPOLICY_RECOMPILE_RING0, true); AssertReleaseRC(rc);
     882                        rc = EMR3SetExecutionPolicy(pUVM, EMEXECPOLICY_RECOMPILE_RING3, true); AssertReleaseRC(rc);
    883883                        DBGFR3Info(pVM, "cpumguest", "verbose", NULL);
    884884                        if (fPowerOn)
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette