VirtualBox

Changeset 44646 in vbox for trunk/src/VBox/Devices/Audio


Ignore:
Timestamp:
Feb 11, 2013 8:07:44 PM (12 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
83734
Message:

DevIchIntelHDA.cpp: Last batch of cleanups.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp

    r44645 r44646  
    435435} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
    436436
    437 typedef struct INTELHDLinkState
     437/**
     438 * ICH Intel HD Audio Controller state.
     439 */
     440typedef struct HDASTATE
    438441{
    439442    /** The PCI device structure. */
     
    471474    uint8_t                 u8Counter;
    472475    uint64_t                u64BaseTS;
    473 } INTELHDLinkState, *PINTELHDLinkState;
    474 /** ICH Intel HD Audio Controller state. */
    475 typedef INTELHDLinkState HDASTATE;
     476} HDASTATE;
    476477/** Pointer to the ICH Intel HD Audio Controller state. */
    477478typedef HDASTATE *PHDASTATE;
    478 
    479 #define ICH6_HDASTATE_2_DEVINS(pINTELHD)   ((pINTELHD)->pDevIns)
    480 #define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PHDASTATE)(pPciDev))
    481479
    482480#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
     
    720718{
    721719    if (pThis->u64DPBase & DPBASE_ENABLED)
    722         PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis),
     720        PDMDevHlpPhysWrite(pThis->pDevIns,
    723721                           (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
    724722                           pStreamDesc->pu32Lpib, sizeof(uint32_t));
     
    758756    {
    759757        Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
    760         PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pThis), 0 , fIrq);
     758        PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);
    761759    }
    762760    return VINF_SUCCESS;
     
    820818    {
    821819        Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
    822         rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
     820        rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
    823821        if (RT_FAILURE(rc))
    824822            AssertRCReturn(rc, rc);
     
    849847    {
    850848        Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
    851         rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
     849        rc = PDMDevHlpPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
    852850        if (RT_FAILURE(rc))
    853851            AssertRCReturn(rc, rc);
     
    10531051                HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
    10541052        }
    1055         hdaReset(ICH6_HDASTATE_2_DEVINS(pThis));
     1053        hdaReset(pThis->pDevIns);
    10561054        GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
    10571055        pThis->fInReset = true;
     
    11031101{
    11041102    /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
    1105     *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pThis))
     1103    *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)
    11061104                                                   - pThis->u64BaseTS, 24, 1000);
    11071105    return VINF_SUCCESS;
     
    15301528    for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
    15311529    {
    1532         PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), u64BaseDMA + i*16, bdle, 16);
     1530        PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);
    15331531        addr = *(uint64_t *)bdle;
    15341532        len = *(uint32_t *)&bdle[8];
     
    15401538    for (i = 0; i < 8; ++i)
    15411539    {
    1542         PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
     1540        PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
    15431541        Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": "   ",
    15441542             i , counter));
     
    15541552            && pBdle
    15551553            && pBdle->u32BdleMaxCvi));
    1556     PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
     1554    PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
    15571555    pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
    15581556    pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
     
    17451743     * write the HDA DMA buffer
    17461744     */
    1747     PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
     1745    PDMDevHlpPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
    17481746
    17491747    /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
     
    17841782    }
    17851783
    1786     PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
     1784    PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
    17871785    /*
    17881786     * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
     
    18141812DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
    18151813{
    1816     PHDASTATE pThis = (INTELHDLinkState *)pCodecState->pvHDAState;
     1814    PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
    18171815    return VINF_SUCCESS;
    18181816}
     
    18511849static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
    18521850{
    1853     PHDASTATE pThis = (INTELHDLinkState *)pCodecState->pvHDAState;
     1851    PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState;
    18541852    uint8_t                 u8Strm = 0;
    18551853    PHDABDLEDESC            pBdle = NULL;
     
    19951993                                           PCIADDRESSSPACE enmType)
    19961994{
     1995    PPDMDEVINS  pDevIns = pPciDev->pDevIns;
     1996    PHDASTATE   pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
     1997    RTIOPORT    Port = (RTIOPORT)GCPhysAddress;
    19971998    int         rc;
    1998     PPDMDEVINS  pDevIns = pPciDev->pDevIns;
    1999     RTIOPORT    Port = (RTIOPORT)GCPhysAddress;
    2000     PHDASTATE pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
    20011999
    20022000    /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
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