Changeset 44646 in vbox for trunk/src/VBox/Devices/Audio
- Timestamp:
- Feb 11, 2013 8:07:44 PM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 83734
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
r44645 r44646 435 435 } HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC; 436 436 437 typedef struct INTELHDLinkState 437 /** 438 * ICH Intel HD Audio Controller state. 439 */ 440 typedef struct HDASTATE 438 441 { 439 442 /** The PCI device structure. */ … … 471 474 uint8_t u8Counter; 472 475 uint64_t u64BaseTS; 473 } INTELHDLinkState, *PINTELHDLinkState; 474 /** ICH Intel HD Audio Controller state. */ 475 typedef INTELHDLinkState HDASTATE; 476 } HDASTATE; 476 477 /** Pointer to the ICH Intel HD Audio Controller state. */ 477 478 typedef HDASTATE *PHDASTATE; 478 479 #define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)480 #define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PHDASTATE)(pPciDev))481 479 482 480 #define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \ … … 720 718 { 721 719 if (pThis->u64DPBase & DPBASE_ENABLED) 722 PDMDevHlpPhysWrite( ICH6_HDASTATE_2_DEVINS(pThis),720 PDMDevHlpPhysWrite(pThis->pDevIns, 723 721 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8, 724 722 pStreamDesc->pu32Lpib, sizeof(uint32_t)); … … 758 756 { 759 757 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted")); 760 PDMDevHlpPCISetIrq( ICH6_HDASTATE_2_DEVINS(pThis), 0 , fIrq);758 PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq); 761 759 } 762 760 return VINF_SUCCESS; … … 820 818 { 821 819 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))); 822 rc = PDMDevHlpPhysRead( ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);820 rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf); 823 821 if (RT_FAILURE(rc)) 824 822 AssertRCReturn(rc, rc); … … 849 847 { 850 848 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))); 851 rc = PDMDevHlpPhysWrite( ICH6_HDASTATE_2_DEVINS(pThis), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);849 rc = PDMDevHlpPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf); 852 850 if (RT_FAILURE(rc)) 853 851 AssertRCReturn(rc, rc); … … 1053 1051 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off")); 1054 1052 } 1055 hdaReset( ICH6_HDASTATE_2_DEVINS(pThis));1053 hdaReset(pThis->pDevIns); 1056 1054 GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST); 1057 1055 pThis->fInReset = true; … … 1103 1101 { 1104 1102 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */ 1105 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano( ICH6_HDASTATE_2_DEVINS(pThis))1103 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns) 1106 1104 - pThis->u64BaseTS, 24, 1000); 1107 1105 return VINF_SUCCESS; … … 1530 1528 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i) 1531 1529 { 1532 PDMDevHlpPhysRead( ICH6_HDASTATE_2_DEVINS(pThis), u64BaseDMA + i*16, bdle, 16);1530 PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16); 1533 1531 addr = *(uint64_t *)bdle; 1534 1532 len = *(uint32_t *)&bdle[8]; … … 1540 1538 for (i = 0; i < 8; ++i) 1541 1539 { 1542 PDMDevHlpPhysRead( ICH6_HDASTATE_2_DEVINS(pThis), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));1540 PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter)); 1543 1541 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ", 1544 1542 i , counter)); … … 1554 1552 && pBdle 1555 1553 && pBdle->u32BdleMaxCvi)); 1556 PDMDevHlpPhysRead( ICH6_HDASTATE_2_DEVINS(pThis), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);1554 PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16); 1557 1555 pBdle->u64BdleCviAddr = *(uint64_t *)bdle; 1558 1556 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8]; … … 1745 1743 * write the HDA DMA buffer 1746 1744 */ 1747 PDMDevHlpPhysWrite( ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);1745 PDMDevHlpPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy); 1748 1746 1749 1747 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */ … … 1784 1782 } 1785 1783 1786 PDMDevHlpPhysRead( ICH6_HDASTATE_2_DEVINS(pThis), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);1784 PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy); 1787 1785 /* 1788 1786 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend. … … 1814 1812 DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState) 1815 1813 { 1816 PHDASTATE pThis = ( INTELHDLinkState *)pCodecState->pvHDAState;1814 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState; 1817 1815 return VINF_SUCCESS; 1818 1816 } … … 1851 1849 static DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail) 1852 1850 { 1853 PHDASTATE pThis = ( INTELHDLinkState *)pCodecState->pvHDAState;1851 PHDASTATE pThis = (PHDASTATE)pCodecState->pvHDAState; 1854 1852 uint8_t u8Strm = 0; 1855 1853 PHDABDLEDESC pBdle = NULL; … … 1995 1993 PCIADDRESSSPACE enmType) 1996 1994 { 1995 PPDMDEVINS pDevIns = pPciDev->pDevIns; 1996 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev); 1997 RTIOPORT Port = (RTIOPORT)GCPhysAddress; 1997 1998 int rc; 1998 PPDMDEVINS pDevIns = pPciDev->pDevIns;1999 RTIOPORT Port = (RTIOPORT)GCPhysAddress;2000 PHDASTATE pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);2001 1999 2002 2000 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
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