Changeset 46310 in vbox for trunk/src/VBox/VMM

Timestamp:

May 29, 2013 12:52:37 PM (12 years ago)

Author:

vboxsync

Message:

VMM/HM: AMD-V bits. Bring VMCB layout up to latest spec.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (6 diffs)
• HWSVMR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -20 +20 @@
 *******************************************************************************/
 
+#ifdef DEBUG_ramshankar
+# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
+# define HMSVM_ALWAYS_TRAP_PF
+#endif
 
 /*******************************************************************************
@@ -211 +215 @@
 VMMR0DECL(int) SVMR0InitVM(PVM pVM)
 {
-    int rc;
+    int rc = VERR_INTERNAL_ERROR_5;
 
     /* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
@@ -241 +245 @@
 
         pVCpu->hm.s.svm.pvVmcbHost     = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
-        pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0);
+        pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
         Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
         ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
@@ -251 +255 @@
 
         pVCpu->hm.s.svm.pvVmcb     = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
-        pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0);
+        pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
         Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
         ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
@@ -261 +265 @@
 
         pVCpu->hm.s.svm.pvMsrBitmap     = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
-        pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0);
+        pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
         /* Set all bits to intercept all MSR accesses. */
         ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
@@ -287 +291 @@
 
 
-
+/**
+ * Sets up AMD-V for the specified VM.
+ * This function is only called once per-VM during initalization.
+ *
+ * @returns VBox status code.
+ * @param   pVM         Pointer to the VM.
+ */
+VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
+{
+    int rc = VINF_SUCCESS;
+
+    AssertReturn(pVM, VERR_INVALID_PARAMETER);
+    Assert(pVM->hm.s.svm.fSupported);
+
+    for (uint32_t i = 0; i < pVM->cCpus; i++)
+    {
+        PVMCPU   pVCpu = &pVM->aCpus[i];
+        PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
+
+        AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
+
+        /* Intercept traps. */
+#ifdef HMSVM_ALWAYS_TRAP_PF
+        pVmcb->ctrl.u32InterceptException |=   RT_BIT(X86_XCPT_PF);
+#endif
+#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
+        pVmcb->ctrl.u32InterceptException |=   RT_BIT(X86_XCPT_BP)
+                                             | RT_BIT(X86_XCPT_DB)
+                                             | RT_BIT(X86_XCPT_DE)
+                                             | RT_BIT(X86_XCPT_UD)
+                                             | RT_BIT(X86_XCPT_NP)
+                                             | RT_BIT(X86_XCPT_SS)
+                                             | RT_BIT(X86_XCPT_GP)
+                                             | RT_BIT(X86_XCPT_MF)
+                                             | RT_BIT(X86_XCPT_PF);
+#endif
+
+        /* -XXX- todo. */
+    }
+
+    return rc;
+}
+

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -1584 +1584 @@
         Log(("ctrl.IntCtrl.u3Reserved           %x\n",      pVmcb->ctrl.IntCtrl.n.u3Reserved));
         Log(("ctrl.IntCtrl.u1VIrqMasking        %x\n",      pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
-        Log(("ctrl.IntCtrl.u7Reserved2          %x\n",      pVmcb->ctrl.IntCtrl.n.u7Reserved2));
+        Log(("ctrl.IntCtrl.u6Reserved           %x\n",      pVmcb->ctrl.IntCtrl.n.u6Reserved));
         Log(("ctrl.IntCtrl.u8VIrqVector         %x\n",      pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
         Log(("ctrl.IntCtrl.u24Reserved          %x\n",      pVmcb->ctrl.IntCtrl.n.u24Reserved));