Changeset 46731 in vbox for trunk/src/VBox/VMM/testcase/Instructions
- Timestamp:
- Jun 22, 2013 12:34:46 AM (12 years ago)
- svn:sync-xref-src-repo-rev:
- 86654
- Location:
- trunk/src/VBox/VMM/testcase/Instructions
- Files:
-
- 2 edited
-
InstructionTestGen.py (modified) (14 diffs)
-
env-common.mac (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py
r46728 r46731 45 45 """ 64-bit one bit mask. """ 46 46 return 1 << iBit; 47 ## @} 48 49 50 ## @name Misc 51 ## @{ 52 53 def convU32ToSigned(u32): 54 """ Converts a 32-bit unsigned value to 32-bit signed. """ 55 if u32 < 0x80000000: 56 return u32; 57 return u32 - UINT32_MAX - 1; 58 47 59 ## @} 48 60 … … 134 146 135 147 148 136 149 ## @name Instruction Emitter Helpers 137 150 ## @{ … … 226 239 return self.getMaxOpBits() / 8; 227 240 241 def getDefAddrBits(self): 242 """ Get the default address size as a bit count. """ 243 if self.sInstrSet == self.ksInstrSet_16: 244 return 16; 245 if self.sInstrSet == self.ksInstrSet_32: 246 return 32; 247 return 64; 248 249 def getDefAddrBytes(self): 250 """ Get the default address size as a byte count. """ 251 return self.getDefAddrBits() / 8; 252 228 253 def getGRegCount(self): 229 254 """ Get the number of general registers. """ … … 240 265 """ Gets a list of addressing mode (16, 32, or/and 64). """ 241 266 if self.sInstrSet == self.ksInstrSet_16: 242 return [16, ];267 return [16, 32]; 243 268 if self.sInstrSet == self.ksInstrSet_32: 244 269 return [32, 16]; … … 253 278 254 279 255 class InstrTestBase(object): # pylint: disable=R0903280 class InstrTestBase(object): 256 281 """ 257 282 Base class for testing one instruction. … … 346 371 elif cbEffOp == 2: 347 372 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs16[iOp1], g_asGRegs16[iOp2])); 373 elif cbEffOp == 1: 374 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs8[iOp1], g_asGRegs8[iOp2])); 348 375 else: 349 376 assert False; … … 358 385 elif cbEffOp == 2: 359 386 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs16[iOp1],)); 387 elif cbEffOp == 1: 388 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs8[iOp1],)); 360 389 else: 361 390 assert False; … … 405 434 else: 406 435 ## @todo generate REX.B=1 variant. 407 oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp /2,));436 oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,)); 408 437 oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); 409 438 return True; … … 441 470 442 471 443 def generateStandardTests(self, oGen): # pylint: disable=R0914472 def generateStandardTests(self, oGen): 444 473 """ Generate standard tests. """ 445 474 … … 512 541 513 542 543 544 class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg): 545 """ 546 Tests MOV Gv,Ev. 547 """ 548 def __init__(self): 549 InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov); 550 551 @staticmethod 552 def calc_mov(cbEffOp, uInput, uCur, oGen): 553 """ Calculates the result of a mov instruction.""" 554 if cbEffOp == 8: 555 return uInput & UINT64_MAX; 556 if cbEffOp == 4: 557 return uInput & UINT32_MAX; 558 if cbEffOp == 2: 559 return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX); 560 assert cbEffOp == 1; 561 return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX); 562 563 514 564 class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg): 515 565 """ … … 554 604 ## Instruction Tests. 555 605 g_aoInstructionTests = [ 556 InstrTest_MovSxD_Gv_Ev(), 606 InstrTest_Mov_Gv_Ev(), 607 #InstrTest_MovSxD_Gv_Ev(), 557 608 ]; 558 609 … … 646 697 sName = '%ubit_U%u_%s' % (cAddrBits, cbEffOp * 8, self.oTarget.asGRegs[iReg1]); 647 698 if offDisp is not None: 648 sName += '_ 0x%016x' % (offDisp & UINT64_MAX, );699 sName += '_%#010x' % (offDisp & UINT32_MAX, ); 649 700 if sName in self.dCheckFns: 650 701 self.dMemSetupFns[sName] += 1; … … 780 831 return True; 781 832 833 def _generateMemSetupFunctions(self): 834 """ 835 Generates the memory setup functions. 836 """ 837 cDefAddrBits = self.oTarget.getDefAddrBits(); 838 for sName in self.dMemSetupFns: 839 # Unpack it. 840 asParams = sName.split('_'); 841 cAddrBits = int(asParams[0][:-3]); 842 cEffOpBits = int(asParams[1][1:]); 843 sBaseReg = asParams[2]; 844 845 if cAddrBits == 64: asAddrGRegs = g_asGRegs64; 846 elif cAddrBits == 32: asAddrGRegs = g_asGRegs32; 847 else: asAddrGRegs = g_asGRegs16; 848 iBaseReg = asAddrGRegs.index(sBaseReg); 849 850 i = 3; 851 offDisp = None; 852 if i < len(asParams) and len(asParams[i]) == 10: 853 u32Disp = long(asParams[i], 16); 854 i += 1; 855 856 sIndexReg = None; 857 iIndexReg = None; 858 if i < len(asParams): 859 sIndexReg = asParams[i]; 860 iBaseReg = asAddrGRegs.index(sBaseReg); 861 i += 1; 862 863 iScale = 1; 864 if i < len(asParams): 865 iScale = int(asParams[i]); assert iScale in [2, 4, 8]; 866 i += 1; 867 868 # Prologue. 869 iTmpReg1 = 0 if iBaseReg != 0 else 1; 870 self.write('\n\n' 871 'VBINSTST_BEGINPROC Common_MemSetup_%s\n' 872 ' MY_PUSH_FLAGS\n' 873 ' push %s\n' 874 % (sName, self.oTarget.asGRegs[iTmpReg1], )); 875 876 # Figure out what to use. 877 if cEffOpBits == 64: 878 sTmpReg1 = g_asGRegs64[iTmpReg1]; 879 sDataVar = 'VBINSTST_NAME(g_u64Data)'; 880 elif cEffOpBits == 32: 881 sTmpReg1 = g_asGRegs32[iTmpReg1]; 882 sDataVar = 'VBINSTST_NAME(g_u32Data)'; 883 elif cEffOpBits == 16: 884 sTmpReg1 = g_asGRegs16[iTmpReg1]; 885 sDataVar = 'VBINSTST_NAME(g_u16Data)'; 886 else: 887 assert cEffOpBits == 8; 888 sTmpReg1 = g_asGRegs8[iTmpReg1]; 889 sDataVar = 'VBINSTST_NAME(g_u8Data)'; 890 891 # Load the value and mem address, sorting the value there. 892 self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,)); 893 if cAddrBits >= cDefAddrBits: 894 self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,)); 895 self.write(' lea %s, [%s xWrtRIP]\n' % (sBaseReg, sDataVar,)); 896 else: 897 898 if cAddrBits == 16: 899 self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sBaseReg,)); 900 else: 901 self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sBaseReg,)); 902 self.write(' add %s, %s\n' % (sBaseReg, (randU16() << cEffOpBits) & 0xfff, )); 903 self.write(' mov [%s], %s\n' % (sBaseReg, sTmpReg1, )); 904 905 # Adjust for disposition and scaling. 906 if offDisp is not None: 907 self.write(' sub %s, %d\n' % ( sBaseReg, convU32ToSigned(u32Disp), )); 908 if iIndexReg is not None: 909 uIdxRegVal = randUxx(cAddrBits); 910 self.write(' mov %s, %u\n' % ( sIndexReg, uIdxRegVal,)); 911 if cAddrBits == 64: 912 self.write(' sub %s, %#06x\n' % ( sBaseReg, uIdxRegVal * iScale, )); 913 elif cAddrBits == 16: 914 self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, )); 915 else: 916 assert cAddrBits == 16; 917 self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT16_MAX, )); 918 919 # Set upper bits that's supposed to be unused. 920 if cDefAddrBits > cAddrBits or cAddrBits == 16: 921 if cDefAddrBits == 64: 922 assert cAddrBits == 32; 923 self.write(' mov %s, %#018x\n' 924 ' or %s, %s\n' 925 % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, 926 g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],)); 927 if iIndexReg is not None: 928 self.write(' mov %s, %#018x\n' 929 ' or %s, %s\n' 930 % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, 931 g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],)); 932 else: 933 assert cDefAddrBits == 32; assert cAddrBits == 16; 934 self.write(' or %s, %#010x\n' 935 % ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, )); 936 if iIndexReg is not None: 937 self.write(' or %s, %#010x\n' 938 % ( g_asGRegs32[iIndexReg], randU32() & 0xffff0000, )); 939 940 # Epilogue. 941 self.write(' pop %s\n' 942 ' MY_POP_FLAGS\n' 943 ' ret\n' 944 'VBINSTST_ENDPROC Common_MemSetup_%s\n' 945 % ( self.oTarget.asGRegs[iTmpReg1], sName,)); 946 947 782 948 def _generateFileFooter(self): 783 949 """ … … 841 1007 % (sReg1, sReg2,)); 842 1008 1009 # memory setup functions 1010 self._generateMemSetupFunctions(); 843 1011 844 1012 # 64-bit constants. -
trunk/src/VBox/VMM/testcase/Instructions/env-common.mac
r46728 r46731 179 179 push sAX 180 180 mov ax, [xSP + sCB + xCB] 181 mov [VBINSTST_NAME(g_u8Data) xWrtR ip], ax181 mov [VBINSTST_NAME(g_u8Data) xWrtRIP], ax 182 182 pop sAX 183 183 ret sCB … … 190 190 push sAX 191 191 mov ax, [xSP + sCB + xCB] 192 mov [VBINSTST_NAME(g_u16Data) xWrtR ip], ax192 mov [VBINSTST_NAME(g_u16Data) xWrtRIP], ax 193 193 pop sAX 194 194 ret sCB … … 201 201 push sAX 202 202 mov eax, [xSP + sCB + xCB] 203 mov [VBINSTST_NAME(g_u32Data) xWrtR ip], eax203 mov [VBINSTST_NAME(g_u32Data) xWrtRIP], eax 204 204 pop sAX 205 205 ret sCB … … 213 213 %ifdef RT_ARCH_AMD64 214 214 mov rax, [xSP + sCB + xCB] 215 mov [VBINSTST_NAME(g_u64Data) xWrtR ip], rax215 mov [VBINSTST_NAME(g_u64Data) xWrtRIP], rax 216 216 %else 217 217 mov eax, [xSP + sCB + xCB] 218 mov [VBINSTST_NAME(g_u64Data) xWrtR ip], eax218 mov [VBINSTST_NAME(g_u64Data) xWrtRIP], eax 219 219 mov eax, [xSP + sCB + xCB + 4] 220 mov [VBINSTST_NAME(g_u64Data) + 4 xWrtR ip], eax220 mov [VBINSTST_NAME(g_u64Data) + 4 xWrtRIP], eax 221 221 %endif 222 222 pop sAX
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