Changeset 47135 in vbox for trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

Timestamp:

Jul 14, 2013 4:43:54 PM (11 years ago)

Author:

vboxsync

Message:

32bit fixes

File:

• trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py (modified) (9 diffs)

trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

@@ -384 +384 @@
         return False;
 
+    def gregNameBits(self, iReg, cBits):
+        """ Gets the name of the given register for the specified width (bits). """
+        return gregName(iReg, cBits, self.is64Bit());
+
+    def gregNameBytes(self, iReg, cbWidth):
+        """ Gets the name of the given register for the specified with (in bytes). """
+        return gregName(iReg, cbWidth * 8, self.is64Bit());
+
+
 
 
@@ -392 +401 @@
     'bs2-r0-64':        TargetEnv('bs2-r0-64',      TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long,    0),
     'bs2-r0-64-big':    TargetEnv('bs2-r0-64-big',  TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long,    0),
+    'bs2-r0-32-big':    TargetEnv('bs2-r0-32-big',  TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 0),
 };
 
@@ -1238 +1248 @@
         oGen.write('        push    %s\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX],));
         oGen.write('        VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s    %s\n'
-                   % (self.sInstr, gregName(iOp2, cbEffOp * 8),));
+                   % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),));
         oGen.write('        call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),));
         return True;
@@ -1244 +1254 @@
     def generateOneDivideErrorTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor):
         """ Generate code of one '[I]DIV AX,<GREG>' test that causes #DE (8-bit). """
+        if not oGen.oTarget.is64Bit() and iOp2 == 4: # Avoid AH.
+            iOp2 = 5;
+
         cbMaxOp   = oGen.oTarget.getMaxOpBytes();
         fMaxOp    = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4];
@@ -1264 +1277 @@
         oGen.write('        push    sAX\n');
         oGen.write('        VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s    %s\n'
-                   % (self.sInstr, gregName(iOp2, cbEffOp * 8),));
+                   % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),));
         oGen.write('        call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),));
         return;
@@ -1279 +1292 @@
                 iOp2 = oGen.oTarget.randGRegNoSp();
 
-            for cbEffOp in ( 8, 4, 2, 1 ):
+            for cbEffOp in [1]:#( 8, 4, 2, 1 ):
                 if cbEffOp > oGen.oTarget.getMaxOpBytes():
                     continue;
@@ -1299 +1312 @@
         #oGen.write('        int3\n');
 
-        self.generateStandardTests(oGen);
+        #self.generateStandardTests(oGen);
         self.generateDivideErrorTests(oGen);
 
@@ -1314 +1327 @@
 #
 g_aoInstructionTests = [
-    InstrTest_Mov_Gv_Ev(),
-    #InstrTest_MovSxD_Gv_Ev(),
+    #InstrTest_Mov_Gv_Ev(),
+    ##InstrTest_MovSxD_Gv_Ev(),
     InstrTest_DivIDiv(fIsIDiv = False),
-    InstrTest_DivIDiv(fIsIDiv = True),
+    #InstrTest_DivIDiv(fIsIDiv = True),
 ];
 
@@ -1525 +1538 @@
         """ Checks if we're in tiny mode."""
         return self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny;
+
+
+    #
+    # Forwarding calls for oTarget to shorted typing and lessen the attacks
+    # on the right margin.
+    #
+
+    def gregNameBits(self, iReg, cBitsWide):
+        """ Target: Get the name of a general register for the given size (in bits). """
+        return self.oTarget.gregNameBits(iReg, cBitsWide);
+
+    def gregNameBytes(self, iReg, cbWide):
+        """ Target: Get the name of a general register for the given size (in bytes). """
+        return self.oTarget.gregNameBytes(iReg, cbWide);
+
+    def is64Bit(self):
+        """ Target: Is the target 64-bit? """
+        return self.oTarget.is64Bit();