Changeset 47677 in vbox for trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

Timestamp:

Aug 12, 2013 4:09:41 PM (11 years ago)

Author:

vboxsync

Message:

HMSVMXR0.cpp: DR6.Bx values are cleared on #DB it seems, while the others aren't.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (5 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -8992 +8992 @@
     AssertRCReturn(rc, rc);
 
-    Log4(("CS:RIP=%04x:%#RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
-
     /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
     uint32_t uIOPort   = VMX_EXIT_QUALIFICATION_IO_PORT(pVmxTransient->uExitQualification);
@@ -9018 +9016 @@
          * interpreting the instruction.
          */
+        Log4(("CS:RIP=%04x:%#RX64 %#06x/%u %c str\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
 #if 0 /* Not quite ready, seem iSegReg assertion trigger once... Do we perhaps need to always read that in longjmp / preempt scenario? */
         AssertReturn(pMixedCtx->dx == uIOPort, VERR_HMVMX_IPE_2);
@@ -9091 +9090 @@
          * IN/OUT - I/O instruction.
          */
+        Log4(("CS:RIP=%04x:%#RX64 %#06x/%u %c\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
         const uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
         Assert(!VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification));
@@ -9165 +9165 @@
                         uint64_t uDrXFirst  = pMixedCtx->dr[iBp] & ~(uint64_t)cbInvAlign;
                         uint64_t uDrXLast   = uDrXFirst + cbInvAlign;
+
                         if (uDrXFirst <= uIOPortLast && uDrXLast >= uIOPort)
                         {
@@ -9670 +9671 @@
          * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
          */
+        pMixedCtx->dr[6] &= ~X86_DR6_B_MASK;
         pMixedCtx->dr[6] |= uDR6;
         if (CPUMIsGuestDebugStateActive(pVCpu))