VirtualBox

Changeset 48212 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Aug 30, 2013 11:02:22 PM (11 years ago)
Author:
vboxsync
Message:

VMM/HM: Naming fixes.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r48210 r48212  
    896896    {
    897897        LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
    898         LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
     898        LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
    899899        switch (pVM->hm.s.lLastError)
    900900        {
    … …  
    969969
    970970    Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
    971     AssertLogRelReturn(pVM->hm.s.vmx.msr.feature_ctrl != 0, VERR_HM_IPE_4);
     971    AssertLogRelReturn(pVM->hm.s.vmx.msr.u64FeatureCtrl != 0, VERR_HM_IPE_4);
    972972
    973973    uint64_t    val;
    … …  
    977977    LogRel(("HM: Using VT-x implementation 2.0!\n"));
    978978    LogRel(("HM: Host CR4                        = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
    979     LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
    980     LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
    981     LogRel(("HM: VMCS id                         = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
    982     LogRel(("HM: VMCS size                       = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    983     LogRel(("HM: VMCS physical address limit     = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
    984     LogRel(("HM: VMCS memory type                = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
    985     LogRel(("HM: Dual-monitor treatment support  = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
    986     LogRel(("HM: OUTS & INS instruction-info     = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
     979    LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
     980    LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.msr.u64BasicInfo));
     981    LogRel(("HM:    VMCS id                                  = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo)));
     982    LogRel(("HM:    VMCS size                                = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo)));
     983    LogRel(("HM:    VMCS physical address limit              = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None"));
     984    LogRel(("HM:    VMCS memory type                         = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo)));
     985    LogRel(("HM:    Dual-monitor treatment support           = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo)));
     986    LogRel(("HM:    OUTS & INS instruction-info              = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo)));
    987987    LogRel(("HM: Max resume loops                = %u\n", pVM->hm.s.cMaxResumeLoops));
    988988
    989     LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS      = %#RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
    990     val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    991     zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
     989    LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS      = %#RX64\n", pVM->hm.s.vmx.msr.VmxPinCtls.u));
     990    val = pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1;
     991    zap = pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0;
    992992    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
    993993    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
    … …  
    995995    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
    996996
    997     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
    998     val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
    999     zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
     997    LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls.u));
     998    val = pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1;
     999    zap = pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0;
    10001000    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
    10011001    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
    … …  
    10191019    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
    10201020    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
    1021     if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    1022     {
    1023         LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2    = %#RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
    1024         val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
    1025         zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
     1021    if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
     1022    {
     1023        LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2    = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls2.u));
     1024        val = pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1;
     1025        zap = pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0;
    10261026        HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
    10271027        HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
    … …  
    10381038    }
    10391039
    1040     LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
    1041     val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
    1042     zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
     1040    LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS         = %#RX64\n", pVM->hm.s.vmx.msr.VmxEntry.u));
     1041    val = pVM->hm.s.vmx.msr.VmxEntry.n.allowed1;
     1042    zap = pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0;
    10431043    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
    10441044    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
    … …  
    10491049    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
    10501050
    1051     LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
    1052     val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
    1053     zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
     1051    LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.msr.VmxExit.u));
     1052    val = pVM->hm.s.vmx.msr.VmxExit.n.allowed1;
     1053    zap = pVM->hm.s.vmx.msr.VmxExit.n.disallowed0;
    10541054    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
    10551055    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
    … …  
    10621062    HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
    10631063
    1064     if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
    1065     {
    1066         val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
     1064    if (pVM->hm.s.vmx.msr.u64EptVpidCaps)
     1065    {
     1066        val = pVM->hm.s.vmx.msr.u64EptVpidCaps;
    10671067        LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP       = %#RX64\n", val));
    10681068        HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
    … …  
    10931093    }
    10941094
    1095     LogRel(("HM: MSR_IA32_VMX_MISC               = %#RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
    1096     if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
     1095    LogRel(("HM: MSR_IA32_VMX_MISC               = %#RX64\n", pVM->hm.s.vmx.msr.u64Misc));
     1096    if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc) == pVM->hm.s.vmx.cPreemptTimerShift)
    10971097    {
    10981098        LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %#x\n",
    1099                 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
     1099                MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc)));
    11001100    }
    11011101    else
    11021102    {
    11031103        LogRel(("HM:    MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT        = %#x - erratum detected, using %#x instead\n",
    1104                 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
    1105     }
    1106 
    1107     LogRel(("HM:    MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT   = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
    1108     LogRel(("HM:    MSR_IA32_VMX_MISC_ACTIVITY_STATES        = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
    1109     LogRel(("HM:    MSR_IA32_VMX_MISC_CR3_TARGET             = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
    1110     LogRel(("HM:    MSR_IA32_VMX_MISC_MAX_MSR                = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
    1111     LogRel(("HM:    MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM   = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
    1112     LogRel(("HM:    MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2     = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
    1113     LogRel(("HM:    MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO    = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
    1114     LogRel(("HM:    MSR_IA32_VMX_MISC_MSEG_ID                = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
     1104                MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc), pVM->hm.s.vmx.cPreemptTimerShift));
     1105    }
     1106
     1107    val = pVM->hm.s.vmx.msr.u64Misc;
     1108    LogRel(("HM:    MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT   = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val)));
     1109    LogRel(("HM:    MSR_IA32_VMX_MISC_ACTIVITY_STATES        = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
     1110    LogRel(("HM:    MSR_IA32_VMX_MISC_CR3_TARGET             = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
     1111    LogRel(("HM:    MSR_IA32_VMX_MISC_MAX_MSR                = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
     1112    LogRel(("HM:    MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM   = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val)));
     1113    LogRel(("HM:    MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2     = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val)));
     1114    LogRel(("HM:    MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO    = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val)));
     1115    LogRel(("HM:    MSR_IA32_VMX_MISC_MSEG_ID                = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
    11151116
    11161117    /* Paranoia */
    1117     AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
    1118 
    1119     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
    1120     LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
    1121     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
    1122     LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
    1123     LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM          = %#RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
    1124     LogRel(("HM:    MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX     = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
    1125 
    1126     val = pVM->hm.s.vmx.msr.vmx_vmfunc;
     1118    AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc) >= 512);
     1119
     1120    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed0));
     1121    LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed1));
     1122    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed0));
     1123    LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1         = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed1));
     1124
     1125    val = pVM->hm.s.vmx.msr.u64VmcsEnum;
     1126    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM          = %#RX64\n", val));
     1127    LogRel(("HM:    MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX     = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
     1128
     1129    val = pVM->hm.s.vmx.msr.u64Vmfunc;
    11271130    if (val)
    11281131    {
    … …  
    11391142    }
    11401143
    1141     if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
     1144    if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
    11421145        pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
    11431146
    1144     if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
     1147    if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
    11451148        pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
    11461149
    … …  
    11501153     * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
    11511154     */
    1152     if (   !(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
     1155    if (   !(pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    11531156        && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
    11541157    {
    … …  
    11601163    if (    pVM->hm.s.vmx.fAllowUnrestricted
    11611164        &&  pVM->hm.s.fNestedPaging
    1162         &&  (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
     1165        &&  (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
    11631166    {
    11641167        pVM->hm.s.vmx.fUnrestrictedGuest = true;
    … …  
    25642567
    25652568        /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
    2566         mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
     2569        mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr0Fixed0;
    25672570        /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
    25682571        mask &= ~X86_CR0_NE;
    … …  
    25822585
    25832586        /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
    2584         mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
     2587        mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr0Fixed1;
    25852588        if ((pCtx->cr0 & mask) != 0)
    25862589            return false;
    25872590
    25882591        /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
    2589         mask  = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
     2592        mask  = (uint32_t)pVM->hm.s.vmx.msr.u64Cr4Fixed0;
    25902593        mask &= ~X86_CR4_VMXE;
    25912594        if ((pCtx->cr4 & mask) != mask)
    … …  
    25932596
    25942597        /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
    2595         mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
     2598        mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr4Fixed1;
    25962599        if ((pCtx->cr4 & mask) != 0)
    25972600            return false;
    … …  
    29452948    if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
    29462949    {
    2947         LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed    %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
    2948         LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
     2950        LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed    %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.allowed1));
     2951        LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0));
    29492952    }
    29502953}
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