Changeset 49927 in vbox for trunk/src/VBox
- Timestamp:
- Dec 16, 2013 12:17:39 PM (11 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 1 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r49899 r49927 2365 2365 { 2366 2366 /** @todo uncore msrs. */ 2367 return VINF_SUCCESS; 2368 } 2369 2370 2371 /** @callback_method_impl{FNCPUMRDMSR} */ 2372 static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2373 { 2374 /** @todo implement enhanced multi thread termal monitoring? */ 2375 *puValue = pRange->uInitOrReadValue; 2376 return VINF_SUCCESS; 2377 } 2378 2379 2380 /** @callback_method_impl{FNCPUMWRMSR} */ 2381 static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2382 { 2383 /** @todo implement enhanced multi thread termal monitoring? */ 2384 return VINF_SUCCESS; 2385 } 2386 2387 2388 /** @callback_method_impl{FNCPUMRDMSR} */ 2389 static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2390 { 2391 /** @todo SMM & C-states? */ 2392 *puValue = 0; 2393 return VINF_SUCCESS; 2394 } 2395 2396 2397 /** @callback_method_impl{FNCPUMWRMSR} */ 2398 static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2399 { 2400 /** @todo SMM & C-states? */ 2401 return VINF_SUCCESS; 2402 } 2403 2404 2405 /** @callback_method_impl{FNCPUMRDMSR} */ 2406 static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2407 { 2408 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */ 2409 *puValue = 0; 2410 return VINF_SUCCESS; 2411 } 2412 2413 2414 /** @callback_method_impl{FNCPUMWRMSR} */ 2415 static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2416 { 2417 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */ 2418 return VINF_SUCCESS; 2419 } 2420 2421 2422 /** @callback_method_impl{FNCPUMRDMSR} */ 2423 static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2424 { 2425 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */ 2426 *puValue = 0; 2427 return VINF_SUCCESS; 2428 } 2429 2430 2431 /** @callback_method_impl{FNCPUMWRMSR} */ 2432 static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2433 { 2434 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */ 2435 return VINF_SUCCESS; 2436 } 2437 2438 2439 /** @callback_method_impl{FNCPUMRDMSR} */ 2440 static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2441 { 2442 /** @todo Core2+ platform environment control interface control register? */ 2443 *puValue = 0; 2444 return VINF_SUCCESS; 2445 } 2446 2447 2448 /** @callback_method_impl{FNCPUMWRMSR} */ 2449 static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2450 { 2451 /** @todo Core2+ platform environment control interface control register? */ 2367 2452 return VINF_SUCCESS; 2368 2453 } … … 4192 4277 cpumMsrRd_IntelI7UncArbPerfCtrN, 4193 4278 cpumMsrRd_IntelI7UncArbPerfEvtSelN, 4279 cpumMsrRd_IntelCore2EmttmCrTablesN, 4280 cpumMsrRd_IntelCore2SmmCStMiscInfo, 4281 cpumMsrRd_IntelCore1ExtConfig, 4282 cpumMsrRd_IntelCore1DtsCalControl, 4283 cpumMsrRd_IntelCore2PeciControl, 4194 4284 4195 4285 cpumMsrRd_P6LastBranchFromIp, … … 4396 4486 cpumMsrWr_IntelI7UncArbPerfCtrN, 4397 4487 cpumMsrWr_IntelI7UncArbPerfEvtSelN, 4488 cpumMsrWr_IntelCore2EmttmCrTablesN, 4489 cpumMsrWr_IntelCore2SmmCStMiscInfo, 4490 cpumMsrWr_IntelCore1ExtConfig, 4491 cpumMsrWr_IntelCore1DtsCalControl, 4492 cpumMsrWr_IntelCore2PeciControl, 4398 4493 4399 4494 cpumMsrWr_P6LastIntFromIp, … … 4822 4917 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN); 4823 4918 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN); 4919 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN); 4920 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo); 4921 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig); 4922 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl); 4923 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl); 4824 4924 4825 4925 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp); … … 5015 5115 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN); 5016 5116 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN); 5117 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN); 5118 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo); 5119 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig); 5120 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl); 5121 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl); 5017 5122 5018 5123 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp); -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r49915 r49927 3818 3818 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29"); 3819 3819 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30"); 3820 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");3820 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP"); 3821 3821 pHlp->pfnPrintf(pHlp, "\n"); 3822 3822 } -
trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp
r49899 r49927 176 176 #include "cpus/Intel_Core_i7_3960X.h" 177 177 #include "cpus/Intel_Core_i5_3570.h" 178 #include "cpus/Intel_Xeon_X5482_3_20GHz.h" 178 179 179 180 #include "cpus/AMD_FX_8150_Eight_Core.h" … … 198 199 #ifdef Intel_Pentium_M_processor_2_00GHz 199 200 &g_Entry_Intel_Pentium_M_processor_2_00GHz, 201 #endif 202 #ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz 203 &g_Entry_Intel_Xeon_X5482_3_20GHz, 200 204 #endif 201 205 #ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core -
trunk/src/VBox/VMM/include/CPUMInternal.h
r49899 r49927 265 265 kCpumMsrRdFn_IntelI7UncArbPerfCtrN, 266 266 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN, 267 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */ 268 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo, 269 kCpumMsrRdFn_IntelCore1ExtConfig, 270 kCpumMsrRdFn_IntelCore1DtsCalControl, 271 kCpumMsrRdFn_IntelCore2PeciControl, 267 272 268 273 kCpumMsrRdFn_P6LastBranchFromIp, … … 477 482 kCpumMsrWrFn_IntelI7UncArbPerfCtrN, 478 483 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN, 484 kCpumMsrWrFn_IntelCore2EmttmCrTablesN, 485 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo, 486 kCpumMsrWrFn_IntelCore1ExtConfig, 487 kCpumMsrWrFn_IntelCore1DtsCalControl, 488 kCpumMsrWrFn_IntelCore2PeciControl, 479 489 480 490 kCpumMsrWrFn_P6LastIntFromIp, -
trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp
r49899 r49927 575 575 case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */ 576 576 case 0x0000001b: return "IA32_APIC_BASE"; 577 case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */ 577 578 case 0x0000002a: return "EBL_CR_POWERON"; 578 579 case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */ … … 583 584 case 0x00000035: return "P6_UNK_0000_0035"; /* P6_M_Dothan. */ 584 585 case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */ 586 case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */ 585 587 case 0x0000003a: return "IA32_FEATURE_CONTROL"; 586 588 case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */ 587 589 case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */ 588 590 case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */ 589 case 0x00000040: return "MSR_LASTBRANCH_0";590 case 0x00000041: return "MSR_LASTBRANCH_1";591 case 0x00000042: return "MSR_LASTBRANCH_2";592 case 0x00000043: return "MSR_LASTBRANCH_3";593 case 0x00000044: return "MSR_LASTBRANCH_4";594 case 0x00000045: return "MSR_LASTBRANCH_5";595 case 0x00000046: return "MSR_LASTBRANCH_6";596 case 0x00000047: return "MSR_LASTBRANCH_7";597 case 0x00000048: return "MSR_LASTBRANCH_8"; 598 case 0x00000049: return "MSR_LASTBRANCH_9"; 591 case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0"; 592 case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1"; 593 case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2"; 594 case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3"; 595 case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4"; 596 case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5"; 597 case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6"; 598 case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7"; 599 case 0x00000048: return "MSR_LASTBRANCH_8"; /*??*/ 600 case 0x00000049: return "MSR_LASTBRANCH_9"; /*??*/ 599 601 case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */ 600 602 case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */ … … 608 610 case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */ 609 611 case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */ 612 case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */ 613 case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */ 614 case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */ 615 case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */ 616 case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */ 617 case 0x00000065: return "MSR_LASTBRANCH_5_TO_IP"; 618 case 0x00000066: return "MSR_LASTBRANCH_6_TO_IP"; 619 case 0x00000067: return "MSR_LASTBRANCH_7_TO_IP"; 610 620 case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */ 611 621 case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */ … … 623 633 case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */ 624 634 case 0x0000009b: return "IA32_SMM_MONITOR_CTL"; 635 case 0x000000a8: return "C2_EMTTM_CR_TABLES_0"; 636 case 0x000000a9: return "C2_EMTTM_CR_TABLES_1"; 637 case 0x000000aa: return "C2_EMTTM_CR_TABLES_2"; 638 case 0x000000ab: return "C2_EMTTM_CR_TABLES_3"; 639 case 0x000000ac: return "C2_EMTTM_CR_TABLES_4"; 640 case 0x000000ad: return "C2_EMTTM_CR_TABLES_5"; 625 641 case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */ 626 642 case 0x000000c1: return "IA32_PMC0"; … … 636 652 case 0x000000cd: return "P6_UNK_0000_00cd"; /* P6_M_Dothan. */ 637 653 case 0x000000ce: return "P6_UNK_0000_00ce"; /* P6_M_Dothan. */ 654 case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */ 655 case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */ 656 case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */ 638 657 case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL"; 658 case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */ 639 659 case 0x000000e4: return "MSR_PMG_IO_CAPTURE_BASE"; 660 case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */ 640 661 case 0x000000e7: return "IA32_MPERF"; 641 662 case 0x000000e8: return "IA32_APERF"; 663 case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */ 642 664 case 0x000000fe: return "IA32_MTRRCAP"; 643 665 case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */ … … 649 671 case 0x0000011a: return "BBL_CR_TRIG"; 650 672 case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */ 673 case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */ 651 674 case 0x0000011e: return "BBL_CR_CTL3"; 652 675 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere … … 671 694 case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */ 672 695 case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */ 696 case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */ 697 case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */ 673 698 case 0x00000174: return "IA32_SYSENTER_CS"; 674 699 case 0x00000175: return "IA32_SYSENTER_ESP"; … … 697 722 case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL; 698 723 case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL; 699 case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : NULL;724 case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193"; 700 725 case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX"; 701 726 case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL; … … 724 749 case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS"; 725 750 case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT"; 751 case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */ 726 752 case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/ 727 753 case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL; … … 870 896 case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY"; 871 897 case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY"; 872 case 0x00000478: g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;898 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL; 873 899 case 0x00000480: return "IA32_VMX_BASIC"; 874 900 case 0x00000481: return "IA32_VMX_PINBASED_CTLS"; … … 896 922 case 0x000004c7: return "IA32_A_PMC6"; 897 923 case 0x000004c8: return "IA32_A_PMC7"; 924 case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */ 925 case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */ 926 case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */ 927 case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */ 928 case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */ 929 case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */ 930 case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */ 931 case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */ 898 932 case 0x00000502: return "I7_SB_UNK_0000_0502"; 933 case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */ 934 case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */ 935 case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */ 936 case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */ 899 937 case 0x00000600: return "IA32_DS_AREA"; 900 938 case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */ … … 1402 1440 switch (uMsr) 1403 1441 { 1442 case 0x00000040: 1443 return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n"; 1444 case 0x00000060: 1445 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah) 1446 return "MSR_LASTBRANCH_n_TO_IP"; 1447 break; 1448 1404 1449 case 0x000003f8: 1405 1450 case 0x000003f9: … … 1496 1541 case 0x0000009b: return "Ia32SmmMonitorCtl"; 1497 1542 1543 case 0x000000a8: 1544 case 0x000000a9: 1545 case 0x000000aa: 1546 case 0x000000ab: 1547 case 0x000000ac: 1548 case 0x000000ad: 1549 *pfTakesValue = true; 1550 return "IntelCore2EmttmCrTablesN"; 1551 1498 1552 case 0x000000c1: 1499 1553 case 0x000000c2: … … 1510 1564 1511 1565 case 0x000000e2: return "IntelPkgCStConfigControl"; 1566 case 0x000000e3: return "IntelCore2SmmCStMiscInfo"; 1512 1567 case 0x000000e4: return "IntelPmgIoCaptureBase"; 1513 1568 case 0x000000e7: return "Ia32MPerf"; 1514 1569 case 0x000000e8: return "Ia32APerf"; 1570 case 0x000000ee: return "IntelCore1ExtConfig"; 1515 1571 case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap"; 1516 1572 case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl"; … … 1530 1586 ? "IntelCpuId80000001FeatureMaskEcdx" : NULL; 1531 1587 case 0x0000013c: return "IntelI7SandyAesNiCtl"; 1588 case 0x0000015f: return "IntelCore1DtsCalControl"; 1532 1589 case 0x00000174: return "Ia32SysEnterCs"; 1533 1590 case 0x00000175: return "Ia32SysEnterEsp"; … … 1539 1596 case 0x00000186: return "Ia32PerfEvtSelN"; 1540 1597 case 0x00000187: return "Ia32PerfEvtSelN"; 1598 case 0x00000193: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL : NULL /* Core2_Penryn. */; 1541 1599 case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus"; 1542 1600 case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl"; … … 1630 1688 case 0x000003fe: return "IntelI7CoreCnResidencyN"; 1631 1689 1632 case 0x00000478: g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;1690 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL; 1633 1691 case 0x00000480: *pfTakesValue = true; return "Ia32VmxBase"; 1634 1692 case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls"; … … 1658 1716 case 0x000004c8: 1659 1717 return "Ia32PmcN"; 1718 1719 case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */ 1660 1720 1661 1721 case 0x00000600: return "Ia32DsArea"; … … 1706 1766 //case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db: 1707 1767 //case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df: 1708 return "IntelLastBranch FromN";1768 return "IntelLastBranchToN"; 1709 1769 case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */ 1710 1770 … … 1958 2018 return UINT64_C(0xffff800000000000); 1959 2019 2020 case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063: 2021 case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067: 2022 case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043: 2023 case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047: 2024 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First) 2025 return UINT64_C(0xffff800000000000); 2026 break; 2027 1960 2028 /* Time counters - fudge them to avoid incorrect ignore masks. */ 1961 2029 case 0x00000010: … … 2491 2559 2492 2560 static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName, 2493 uint32_t uMsrBase, bool fEarlyEndOk, uint64_t fSkipMask, uint32_t *pidxLoop)2561 uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop) 2494 2562 { 2495 2563 uint32_t uMsr = paMsrs[0].uMsr; … … 2531 2599 return rc; 2532 2600 if ( fReadOnlyN != fReadOnly0 2533 || fIgnMaskN != fIgnMask02601 || (fIgnMaskN != fIgnMask0 && !fNoIgnMask) 2534 2602 || fGpMaskN != fGpMask0) 2535 2603 { … … 2551 2619 *pidxLoop += cRegs - 1; 2552 2620 2553 bool fSimple = fIgnMask0 == 0 2554 && (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0)) 2555 && iRange == 0; 2621 if (fNoIgnMask) 2622 fIgnMask0 = 0; 2623 bool fSimple = fIgnMask0 == 0 2624 && (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0)) 2625 && iRange == 0; 2556 2626 if (cRegs == 1) 2557 2627 return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, … … 2570 2640 uint32_t *pidxLoop) 2571 2641 { 2572 return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, 2642 return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 2573 2643 getGenericSkipMask(paMsrs[0].uMsr), pidxLoop); 2574 2644 } … … 3419 3489 else if (uMsr == 0x0000001b) 3420 3490 rc = reportMsr_Ia32ApicBase(uMsr, uValue); 3491 else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan) 3492 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i); 3421 3493 else if (uMsr == 0x00000040) 3422 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i); 3494 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false, 3495 true, getGenericSkipMask(uMsr), &i); 3496 else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah) 3497 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false, 3498 true, getGenericSkipMask(uMsr), &i); 3423 3499 else if (uMsr == 0x000000c1) 3424 3500 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, … … 3436 3512 rc = reportMsr_Ia32MtrrFixedOrPat(uMsr); 3437 3513 else if (uMsr >= 0x00000280 && uMsr <= 0x00000295) 3438 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, 0, &i);3514 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i); 3439 3515 else if (uMsr == 0x000002ff) 3440 3516 rc = reportMsr_Ia32MtrrDefType(uMsr); 3441 3517 else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b) 3442 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, 0, &i);3518 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i); 3443 3519 else if (uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a) 3444 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, 0, &i);3520 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i); 3445 3521 else if (uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b) 3446 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, 0, &i);3522 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i); 3447 3523 else if (uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c) 3448 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, 0, &i);3449 else if (uMsr >= 0x00000400 && uMsr <= 0x0000047 f)3524 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i); 3525 else if (uMsr >= 0x00000400 && uMsr <= 0x00000477) 3450 3526 rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i); 3451 3527 else if (uMsr == 0x000004c1) 3452 3528 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i); 3453 3529 else if (uMsr == 0x00000680 || uMsr == 0x000006c0) 3454 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, UINT64_C(0xffff800000000000), &i);3530 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false, UINT64_C(0xffff800000000000), &i); 3455 3531 else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff) 3456 3532 rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i); … … 3494 3570 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i); 3495 3571 else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a) 3496 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, 0, &i);3572 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i); 3497 3573 else if (uMsr == 0xc0010050) 3498 3574 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i); … … 3511 3587 else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) 3512 3588 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1, 3513 false /*fEarlyEndOk*/, 0, &i);3589 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i); 3514 3590 else if (uMsr == 0xc0011021) 3515 3591 rc = reportMsr_AmdK7InstrCacheCfg(uMsr, uValue); … … 3518 3594 else if (uMsr == 0xc0011027) 3519 3595 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027, 3520 false /*fEarlyEndOk*/, 0, &i);3596 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i); 3521 3597 else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch)) 3522 3598 rc = reportMsr_AmdFam15hExecUnitCfg(uMsr, uValue);
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