Changeset 49966 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Dec 17, 2013 8:43:23 PM (11 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r49927 r49966 221 221 222 222 223 /** @callback_method_impl{FNCPUMRDMSR} */ 224 static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 225 { 226 /** @todo fake microcode update. */ 227 *puValue = pRange->uInitOrReadValue; 228 return VINF_SUCCESS; 229 } 230 231 232 /** @callback_method_impl{FNCPUMWRMSR} */ 233 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 234 { 235 return VERR_CPUM_RAISE_GP_0; 236 } 237 238 223 239 /** @callback_method_impl{FNCPUMWRMSR} */ 224 240 static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) … … 695 711 /** @todo implement IA32_PERFSTATUS. */ 696 712 *puValue = pRange->uInitOrReadValue; 713 return VINF_SUCCESS; 714 } 715 716 717 /** @callback_method_impl{FNCPUMWRMSR} */ 718 static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 719 { 720 /* Pentium4 allows writing, but all bits are ignored. */ 697 721 return VINF_SUCCESS; 698 722 } … … 1465 1489 1466 1490 /** @callback_method_impl{FNCPUMRDMSR} */ 1491 static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1492 { 1493 /** @todo P4 hard power on config */ 1494 *puValue = pRange->uInitOrReadValue; 1495 return VINF_SUCCESS; 1496 } 1497 1498 1499 /** @callback_method_impl{FNCPUMWRMSR} */ 1500 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 1501 { 1502 /** @todo P4 hard power on config */ 1503 return VINF_SUCCESS; 1504 } 1505 1506 1507 /** @callback_method_impl{FNCPUMRDMSR} */ 1508 static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1509 { 1510 /** @todo P4 soft power on config */ 1511 *puValue = pRange->uInitOrReadValue; 1512 return VINF_SUCCESS; 1513 } 1514 1515 1516 /** @callback_method_impl{FNCPUMWRMSR} */ 1517 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 1518 { 1519 /** @todo P4 soft power on config */ 1520 return VINF_SUCCESS; 1521 } 1522 1523 1524 /** @callback_method_impl{FNCPUMRDMSR} */ 1525 static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1526 { 1527 /** @todo P4 bus frequency config */ 1528 *puValue = pRange->uInitOrReadValue; 1529 return VINF_SUCCESS; 1530 } 1531 1532 1533 /** @callback_method_impl{FNCPUMWRMSR} */ 1534 static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 1535 { 1536 /** @todo P4 bus frequency config */ 1537 return VINF_SUCCESS; 1538 } 1539 1540 1541 /** @callback_method_impl{FNCPUMRDMSR} */ 1467 1542 static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1468 1543 { … … 2813 2888 2814 2889 /** @callback_method_impl{FNCPUMRDMSR} */ 2890 static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2891 { 2892 /** @todo AMD FIDVID_CTL. */ 2893 *puValue = pRange->uInitOrReadValue; 2894 return VINF_SUCCESS; 2895 } 2896 2897 2898 /** @callback_method_impl{FNCPUMWRMSR} */ 2899 static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 2900 { 2901 /** @todo AMD FIDVID_CTL. */ 2902 return VINF_SUCCESS; 2903 } 2904 2905 2906 /** @callback_method_impl{FNCPUMRDMSR} */ 2907 static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2908 { 2909 /** @todo AMD FIDVID_STATUS. */ 2910 *puValue = pRange->uInitOrReadValue; 2911 return VINF_SUCCESS; 2912 } 2913 2914 2915 /** @callback_method_impl{FNCPUMRDMSR} */ 2815 2916 static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2816 2917 { … … 3453 3554 { 3454 3555 /** @todo Changing CPUID leaf 0x80000001. */ 3556 return VINF_SUCCESS; 3557 } 3558 3559 3560 /** @callback_method_impl{FNCPUMRDMSR} */ 3561 static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 3562 { 3563 /** @todo Fake AMD microcode patching. */ 3564 *puValue = pRange->uInitOrReadValue; 3565 return VINF_SUCCESS; 3566 } 3567 3568 3569 /** @callback_method_impl{FNCPUMWRMSR} */ 3570 static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue) 3571 { 3572 /** @todo Fake AMD microcode patching. */ 3455 3573 return VINF_SUCCESS; 3456 3574 } … … 4144 4262 cpumMsrRd_Ia32ApicBase, 4145 4263 cpumMsrRd_Ia32FeatureControl, 4264 cpumMsrRd_Ia32BiosSignId, 4146 4265 cpumMsrRd_Ia32SmmMonitorCtl, 4147 4266 cpumMsrRd_Ia32PmcN, … … 4217 4336 4218 4337 cpumMsrRd_IntelEblCrPowerOn, 4338 cpumMsrRd_IntelP4EbcHardPowerOn, 4339 cpumMsrRd_IntelP4EbcSoftPowerOn, 4340 cpumMsrRd_IntelP4EbcFrequencyId, 4219 4341 cpumMsrRd_IntelPlatformInfo100MHz, 4220 4342 cpumMsrRd_IntelPlatformInfo133MHz, … … 4304 4426 cpumMsrRd_AmdK8HwThermalCtrl, 4305 4427 cpumMsrRd_AmdK8SwThermalCtrl, 4428 cpumMsrRd_AmdK8FidVidControl, 4429 cpumMsrRd_AmdK8FidVidStatus, 4306 4430 cpumMsrRd_AmdK8McCtlMaskN, 4307 4431 cpumMsrRd_AmdK8SmiOnIoTrapN, … … 4341 4465 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx, 4342 4466 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx, 4467 cpumMsrRd_AmdK8PatchLevel, 4343 4468 cpumMsrRd_AmdK7DebugStatusMaybe, 4344 4469 cpumMsrRd_AmdK7BHTraceBaseMaybe, … … 4393 4518 cpumMsrWr_Ia32ApicBase, 4394 4519 cpumMsrWr_Ia32FeatureControl, 4520 cpumMsrWr_Ia32BiosSignId, 4395 4521 cpumMsrWr_Ia32BiosUpdateTrigger, 4396 4522 cpumMsrWr_Ia32SmmMonitorCtl, … … 4415 4541 cpumMsrWr_Ia32Dca0Cap, 4416 4542 cpumMsrWr_Ia32PerfEvtSelN, 4543 cpumMsrWr_Ia32PerfStatus, 4417 4544 cpumMsrWr_Ia32PerfCtl, 4418 4545 cpumMsrWr_Ia32FixedCtrN, … … 4446 4573 4447 4574 cpumMsrWr_IntelEblCrPowerOn, 4575 cpumMsrWr_IntelP4EbcHardPowerOn, 4576 cpumMsrWr_IntelP4EbcSoftPowerOn, 4577 cpumMsrWr_IntelP4EbcFrequencyId, 4448 4578 cpumMsrWr_IntelPkgCStConfigControl, 4449 4579 cpumMsrWr_IntelPmgIoCaptureBase, … … 4511 4641 cpumMsrWr_AmdK8HwThermalCtrl, 4512 4642 cpumMsrWr_AmdK8SwThermalCtrl, 4643 cpumMsrWr_AmdK8FidVidControl, 4513 4644 cpumMsrWr_AmdK8McCtlMaskN, 4514 4645 cpumMsrWr_AmdK8SmiOnIoTrapN, … … 4547 4678 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx, 4548 4679 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx, 4680 cpumMsrWr_AmdK8PatchLoader, 4549 4681 cpumMsrWr_AmdK7DebugStatusMaybe, 4550 4682 cpumMsrWr_AmdK7BHTraceBaseMaybe, … … 4785 4917 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase); 4786 4918 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl); 4919 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId); 4787 4920 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl); 4788 4921 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN); … … 4857 4990 4858 4991 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn); 4992 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn); 4993 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn); 4994 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId); 4859 4995 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo100MHz); 4860 4996 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo133MHz); … … 4944 5080 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl); 4945 5081 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl); 5082 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl); 5083 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus); 4946 5084 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN); 4947 5085 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN); … … 4981 5119 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx); 4982 5120 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx); 5121 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel); 4983 5122 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe); 4984 5123 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe); … … 5023 5162 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase); 5024 5163 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl); 5164 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId); 5025 5165 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger); 5026 5166 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl); … … 5045 5185 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap); 5046 5186 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN); 5187 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus); 5047 5188 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl); 5048 5189 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN); … … 5075 5216 5076 5217 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn); 5218 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn); 5219 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn); 5220 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId); 5077 5221 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl); 5078 5222 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase); … … 5140 5284 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl); 5141 5285 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl); 5286 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl); 5142 5287 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN); 5143 5288 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN); … … 5176 5321 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx); 5177 5322 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx); 5323 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader); 5178 5324 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe); 5179 5325 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
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