Changeset 49977 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Dec 18, 2013 5:51:13 PM (11 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

91407

Message:

CPUM: Make sure a minimum of commonly used MSRs are present by default.

Location:

trunk/src/VBox/VMM/VMMR3

Files:

• CPUM.cpp (modified) (2 diffs)
• CPUMR3Db.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/CPUM.cpp

@@ -1677 +1677 @@
     }
 
+    /*
+     * MSR fudging.
+     */
+    /** @cfgm{CPUM/FudgeMSRs, boolean, true}
+     * Fudges some common MSRs if not present in the selected CPU database entry.
+     * This is for trying to keep VMs running when moved between different hosts
+     * and different CPU vendors. */
+    bool fEnable;
+    rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true);       AssertRCReturn(rc, rc);
+    if (fEnable)
+    {
+        rc = cpumR3MsrApplyFudge(pVM);
+        AssertLogRelRCReturn(rc, rc);
+    }
 
     /*
@@ -1704 +1718 @@
 
     /* Check if PAE was explicitely enabled by the user. */
-    bool fEnable;
     rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);      AssertRCReturn(rc, rc);
     if (fEnable)

trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

@@ -439 +439 @@
 
 
+/**
+ * Fudges the MSRs that guest are known to access in some odd cases.
+ *
+ * A typical example is a VM that has been moved between different hosts where
+ * for instance the cpu vendor differs.
+ *
+ * @returns VBox status code.
+ * @param   pVM                 Pointer to the cross context VM structure.
+ */
+int cpumR3MsrApplyFudge(PVM pVM)
+{
+    static CPUMMSRRANGE const s_aFudgeMsrs[] =
+    {
+        MFO(0x00000099, "IA32_P5_MC_ADDR",          Ia32P5McAddr),
+        MFX(0x00000001, "IA32_P5_MC_TYPE",          Ia32P5McType,   Ia32P5McType,   0, 0, UINT64_MAX),
+        MVO(0x00000017, "IA32_PLATFORM_ID",         0),
+        MFN(0x0000001b, "IA32_APIC_BASE",           Ia32ApicBase,   Ia32ApicBase),
+        MVI(0x0000008b, "BIOS_SIGN",                0),
+        MFX(0x000000fe, "IA32_MTRRCAP",             Ia32MtrrCap,    ReadOnly,       0x508, 0, 0),
+        MFX(0x00000179, "IA32_MCG_CAP",             Ia32McgCap,     ReadOnly,       0x005, 0, 0),
+        MFX(0x0000017a, "IA32_MCG_STATUS",          Ia32McgStatus,  Ia32McgStatus,  0, ~(uint64_t)UINT32_MAX, 0),
+        MFN(0x000001a0, "IA32_MISC_ENABLE",         Ia32MiscEnable, Ia32MiscEnable),
+        MFN(0x000001d9, "IA32_DEBUGCTL",            Ia32DebugCtl,   Ia32DebugCtl),
+        MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP",   P6LastBranchFromIp),
+        MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP",     P6LastBranchToIp),
+        MFO(0x000001dd, "P6_LAST_INT_FROM_IP",      P6LastIntFromIp),
+        MFO(0x000001de, "P6_LAST_INT_TO_IP",        P6LastIntToIp),
+        MFS(0x00000277, "IA32_PAT",                 Ia32Pat, Ia32Pat, Guest.msrPAT),
+        MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE",       Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
+        MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
+    };
+
+    for (uint32_t i = 0; i < RT_ELEMENTS(s_aFudgeMsrs); i++)
+        if (!cpumLookupMsrRange(pVM, s_aFudgeMsrs[i].uFirst))
+        {
+            LogRel(("CPUM: MSR fudge: %#010x %s\n", s_aFudgeMsrs[i].uFirst, s_aFudgeMsrs[i].szName));
+            int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
+                                           &s_aFudgeMsrs[i]);
+            if (RT_FAILURE(rc))
+                return rc;
+        }
+
+    return VINF_SUCCESS;
+}
+
+
 int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
 {