Changeset 51643 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jun 18, 2014 11:06:06 AM (11 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

94404

Message:

VMM/GIM: More bits for Hyper-V implementation.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• GIMR0.cpp (modified) (2 diffs)
• GIMR0Hv.cpp (modified) (4 diffs)
• HMSVMR0.cpp (modified) (3 diffs)
• HMVMXR0.cpp (modified) (20 diffs)
• VMMR0.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMR0/GIMR0.cpp

@@ -23 +23 @@
 #include "GIMHvInternal.h"
 
-#include <iprt/err.h>
+#include <VBox/err.h>
 #include <VBox/vmm/vm.h>
 
@@ -72 +72 @@
 }
 
+/**
+ * Updates the paravirtualized TSC supported by the GIM provider.
+ *
+ * @returns VBox status code.
+ * @retval VINF_SUCCESS if the paravirt. TSC is setup and in use.
+ * @retval VERR_GIM_NOT_ENABLED if no GIM provider is configured for this VM.
+ * @retval VERR_GIM_PVTSC_NOT_AVAILABLE if the GIM provider does not support any
+ *         paravirt. TSC.
+ * @retval VERR_GIM_PVTSC_NOT_IN_USE if the GIM provider supports paravirt. TSC
+ *         but the guest isn't currently using it.
+ *
+ * @param   pVM         Pointer to the VM.
+ * @param   u64Offset   The computed TSC offset.
+ *
+ * @thread EMT(pVCpu)
+ */
+VMMR0_INT_DECL(int) GIMR0UpdateParavirtTsc(PVM pVM, uint64_t u64Offset)
+{
+    if (!pVM->gim.s.fEnabled)
+        return VERR_GIM_NOT_ENABLED;
+
+    switch (pVM->gim.s.enmProviderId)
+    {
+        case GIMPROVIDERID_HYPERV:
+            return GIMR0HvUpdateParavirtTsc(pVM, u64Offset);
+
+        default:
+            break;
+    }
+    return VERR_GIM_PVTSC_NOT_AVAILABLE;
+}
+

trunk/src/VBox/VMM/VMMR0/GIMR0Hv.cpp

@@ -23 +23 @@
 #include "GIMHvInternal.h"
 
-#include <iprt/err.h>
-#include <iprt/asm.h>
-#include <iprt/memobj.h>
+#include <VBox/err.h>
 #include <VBox/vmm/gim.h>
 #include <VBox/vmm/vm.h>
 
+#include <iprt/spinlock.h>
 
+
+#if 0
 /**
  * Allocates and maps one physically contiguous page. The allocated page is
@@ -80 +81 @@
     }
 }
+#endif
+
+/**
+ * Updates Hyper-V's reference TSC page.
+ *
+ * @returns VBox status code.
+ * @param   pVM         Pointer to the VM.
+ * @param   u64Offset   The computed TSC offset.
+ * @thread  EMT.
+ */
+VMM_INT_DECL(int) GIMR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset)
+{
+    Assert(GIMIsEnabled(pVM));
+    bool fHvTscEnabled = MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
+    if (RT_UNLIKELY(!fHvTscEnabled))
+        return VERR_GIM_PVTSC_NOT_ENABLED;
+
+    PCGIMHV          pcHv     = &pVM->gim.s.u.Hv;
+    PCGIMMMIO2REGION pcRegion = &pcHv->aMmio2Regions[GIM_HV_HYPERCALL_PAGE_REGION_IDX];
+    PGIMHVREFTSC     pRefTsc  = (PGIMHVREFTSC)pcRegion->CTX_SUFF(pvPage);
+    Assert(pRefTsc);
+
+    RTSpinlockAcquire(pcHv->hSpinlockR0);
+    pRefTsc->i64TscOffset = u64Offset;
+    if (pRefTsc->u32TscSequence < UINT32_C(0xfffffffe))
+        ASMAtomicIncU32(&pRefTsc->u32TscSequence);
+    else
+        ASMAtomicWriteU32(&pRefTsc->u32TscSequence, 1);
+    RTSpinlockRelease(pcHv->hSpinlockR0);
+
+    Assert(pRefTsc->u32TscSequence != 0);
+    Assert(pRefTsc->u32TscSequence != UINT32_C(0xffffffff));
+    return VINF_SUCCESS;
+}
 
 
@@ -90 +125 @@
 VMMR0_INT_DECL(int) GIMR0HvInitVM(PVM pVM)
 {
-#if 0
     AssertPtr(pVM);
     Assert(GIMIsEnabled(pVM));
 
     PGIMHV pHv = &pVM->gim.s.u.Hv;
-    Assert(pHv->hMemObjTscPage == NIL_RTR0MEMOBJ);
+    Assert(pHv->hSpinlockR0 == NIL_RTSPINLOCK);
 
-    /*
-     * Allocate the TSC page.
-     */
-    int rc = gimR0HvPageAllocZ(&pHv->hMemObjTscPage, &pHv->pvTscPageR0, &pHv->HCPhysTscPage);
-    if (RT_FAILURE(rc))
-        goto cleanup;
-#endif
-
-    return VINF_SUCCESS;
-
-#if 0
-cleanup:
-    gimR0HvPageFree(&pHv->hMemObjTscPage, &pHv->pvTscPageR0, &pHv->HCPhysTscPage);
+    int rc = RTSpinlockCreate(&pHv->hSpinlockR0, RTSPINLOCK_FLAGS_INTERRUPT_UNSAFE, "Hyper-V");
     return rc;
-#endif
 }
 
@@ -125 +146 @@
     AssertPtr(pVM);
     Assert(GIMIsEnabled(pVM));
-#if 0
+
     PGIMHV pHv = &pVM->gim.s.u.Hv;
-    gimR0HvPageFree(&pHv->hMemObjTscPage, &pHv->pvTscPageR0, &pHv->HCPhysTscPage);
-#endif
+    RTSpinlockDestroy(pHv->hSpinlockR0);
+    pHv->hSpinlockR0 = NIL_RTSPINLOCK;
+
     return VINF_SUCCESS;
 }

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -30 +30 @@
 #include <VBox/vmm/iom.h>
 #include <VBox/vmm/tm.h>
+#include <VBox/vmm/gim.h>
 
 #ifdef DEBUG_ramshankar
@@ -2234 +2235 @@
 static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
 {
+    bool     fParavirtTsc = false;
     PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
-    if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
-    {
-        uint64_t u64CurTSC = ASMReadTSC();
-        if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
+    if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc))
+    {
+        uint64_t u64CurTSC   = ASMReadTSC();
+        uint64_t u64LastTick = TMCpuTickGetLastSeen(pVCpu);
+        if (fParavirtTsc)
+        {
+            if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > u64LastTick)
+            {
+                pVmcb->ctrl.u64TSCOffset = u64LastTick - u64CurTSC;
+                STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffsetAdjusted);
+            }
+            int rc = GIMR0UpdateParavirtTsc(pVCpu->CTX_SUFF(pVM), pVmcb->ctrl.u64TSCOffset);
+            AssertRC(rc);
+            STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
+        }
+
+        if (u64CurTSC + pVmcb->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
         {
             pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
@@ -2253 +2268 @@
     else
     {
+        Assert(!fParavirtTsc);
         pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
         pVmcb->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -34 +34 @@
 #include <VBox/vmm/selm.h>
 #include <VBox/vmm/tm.h>
+#include <VBox/vmm/gim.h>
 #ifdef VBOX_WITH_REM
 # include <VBox/vmm/rem.h>
@@ -336 +337 @@
 *   Internal Functions                                                         *
 *******************************************************************************/
-static void               hmR0VmxFlushEpt(PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush);
-static void               hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr);
+static void               hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush);
+static void               hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
 static int                hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
                                                  uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, uint32_t *puIntState);
@@ -1067 +1068 @@
     if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
     {
-        hmR0VmxFlushEpt(NULL /* pVCpu */, VMX_FLUSH_EPT_ALL_CONTEXTS);
+        hmR0VmxFlushEpt(NULL /* pVCpu */, VMXFLUSHEPT_ALL_CONTEXTS);
         pCpu->fFlushAsidBeforeUse = false;
     }
@@ -1698 +1699 @@
  * @remarks Can be called with interrupts disabled.
  */
-static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush)
+static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush)
 {
     uint64_t au64Descriptor[2];
-    if (enmFlush == VMX_FLUSH_EPT_ALL_CONTEXTS)
+    if (enmFlush == VMXFLUSHEPT_ALL_CONTEXTS)
         au64Descriptor[0] = 0;
     else
@@ -1734 +1735 @@
  * @remarks Can be called with interrupts disabled.
  */
-static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr)
+static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
 {
     NOREF(pVM);
@@ -1741 +1742 @@
 
     uint64_t au64Descriptor[2];
-    if (enmFlush == VMX_FLUSH_VPID_ALL_CONTEXTS)
+    if (enmFlush == VMXFLUSHVPID_ALL_CONTEXTS)
     {
         au64Descriptor[0] = 0;
@@ -1795 +1796 @@
             if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
             {
-                hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, GCVirt);
+                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
             }
@@ -1961 +1962 @@
         {
             for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
-                hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
+                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
         }
         else
@@ -2120 +2121 @@
         if (pCpu->fFlushAsidBeforeUse)
         {
-            if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
-                hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_SINGLE_CONTEXT, 0 /* GCPtr */);
-            else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
+            if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
+                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
+            else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
             {
-                hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_ALL_CONTEXTS, 0 /* GCPtr */);
+                hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
                 pCpu->fFlushAsidBeforeUse = false;
             }
@@ -2151 +2152 @@
             {
                 for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
-                    hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
+                    hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
             }
             else
@@ -2226 +2227 @@
         {
             if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
-                pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT;
+                pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_SINGLE_CONTEXT;
             else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
-                pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS;
+                pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_ALL_CONTEXTS;
             else
             {
                 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
-                pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
+                pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
                 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
             }
@@ -2240 +2241 @@
             {
                 LogRel(("hmR0VmxSetupTaggedTlb: Unsupported EPTP memory type %#x.\n", pVM->hm.s.vmx.Msrs.u64EptVpidCaps));
-                pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
+                pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
                 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
             }
@@ -2247 +2248 @@
         {
             /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
-            pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
+            pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
             return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
         }
@@ -2260 +2261 @@
         {
             if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
-                pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT;
+                pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_SINGLE_CONTEXT;
             else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
-                pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS;
+                pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_ALL_CONTEXTS;
             else
             {
@@ -2270 +2271 @@
                 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
                     LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
-                pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
+                pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
                 pVM->hm.s.vmx.fVpid = false;
             }
@@ -2278 +2279 @@
             /*  Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
             Log4(("hmR0VmxSetupTaggedTlb: VPID supported without INVEPT support. Ignoring VPID.\n"));
-            pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
+            pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
             pVM->hm.s.vmx.fVpid = false;
         }
@@ -2728 +2729 @@
 
     /* Initialize these always, see hmR3InitFinalizeR0().*/
-    pVM->hm.s.vmx.enmFlushEpt  = VMX_FLUSH_EPT_NONE;
-    pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NONE;
+    pVM->hm.s.vmx.enmFlushEpt  = VMXFLUSHEPT_NONE;
+    pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NONE;
 
     /* Setup the tagged-TLB flush handlers. */
@@ -5565 +5566 @@
     int  rc            = VERR_INTERNAL_ERROR_5;
     bool fOffsettedTsc = false;
+    bool fParavirtTsc  = false;
     PVM pVM            = pVCpu->CTX_SUFF(pVM);
     if (pVM->hm.s.vmx.fUsePreemptTimer)
     {
-        uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVCpu, &fOffsettedTsc, &pVCpu->hm.s.vmx.u64TSCOffset);
+        uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVCpu, &fOffsettedTsc, &fParavirtTsc,
+                                                                     &pVCpu->hm.s.vmx.u64TSCOffset);
 
         /* Make sure the returned values have sane upper and lower boundaries. */
@@ -5580 +5583 @@
     }
     else
-        fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset);
+        fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset, &fParavirtTsc);
+
+    if (fParavirtTsc)
+    {
+        uint64_t const u64CurTsc   = ASMReadTSC();
+        uint64_t const u64LastTick = TMCpuTickGetLastSeen(pVCpu);
+        if (u64CurTsc + pVCpu->hm.s.vmx.u64TSCOffset < u64LastTick)
+        {
+            pVCpu->hm.s.vmx.u64TSCOffset = (u64LastTick - u64CurTsc);
+            STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffsetAdjusted);
+        }
+
+        Assert(u64CurTsc + pVCpu->hm.s.vmx.u64TSCOffset >= u64LastTick);
+        rc = GIMR0UpdateParavirtTsc(pVM, pVCpu->hm.s.vmx.u64TSCOffset);
+        if (RT_SUCCESS(rc))
+        {
+            /* Note: VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
+            rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);                                  AssertRC(rc);
+
+            pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
+            rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);              AssertRC(rc);
+            STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
+            return;
+        }
+        /* else: Shouldn't really fail. If it does, fallback to offsetted TSC mode. */
+    }
 
     if (fOffsettedTsc)
@@ -10358 +10386 @@
               ("hmR0VmxExitRdmsr: failed, invalid error code %Rrc\n", rc));
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
-
     if (RT_LIKELY(rc == VINF_SUCCESS))
     {

trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

@@ -36 +36 @@
 #include <VBox/vmm/gvmm.h>
 #include <VBox/vmm/gmm.h>
+#include <VBox/vmm/gim.h>
 #include <VBox/intnet.h>
 #include <VBox/vmm/hm.h>
@@ -379 +380 @@
                     if (RT_SUCCESS(rc))
                     {
-                        GVMMR0DoneInitVM(pVM);
-                        return rc;
+                        rc = GIMR0InitVM(pVM);
+                        if (RT_SUCCESS(rc))
+                        {
+                            GVMMR0DoneInitVM(pVM);
+                            return rc;
+                        }
+
+                        /* bail out*/
+#ifdef VBOX_WITH_PCI_PASSTHROUGH
+                        PciRawR0TermVM(pVM);
+#endif
                     }
                 }
-
-                /* bail out */
             }
-#ifdef VBOX_WITH_PCI_PASSTHROUGH
-            PciRawR0TermVM(pVM);
-#endif
             HMR0TermVM(pVM);
         }
@@ -423 +428 @@
     if (GVMMR0DoingTermVM(pVM, pGVM))
     {
+        GIMR0TermVM(pVM);
+
         /** @todo I wish to call PGMR0PhysFlushHandyPages(pVM, &pVM->aCpus[idCpu])
          *        here to make sure we don't leak any shared pages if we crash... */