Changeset 52465 in vbox for trunk/include/iprt

Timestamp:

Aug 22, 2014 11:39:08 AM (10 years ago)

Author:

vboxsync

Message:

VMM: Fix IEM FXSAVE implementation to match the logic in HM/raw-mode FPU handling.

Location:

trunk/include/iprt

Files:

• x86.h (modified) (2 diffs)
• x86.mac (modified) (1 diff)

trunk/include/iprt/x86.h

@@ -2344 +2344 @@
     } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
     /* - offset 416 - */
-    uint32_t    au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
+    uint32_t    au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
+    /* - offset 464 - Software usable reserved bits. */
+    uint32_t    au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
 } X86FXSTATE;
 #pragma pack()
@@ -2351 +2353 @@
 /** Pointer to a const FPU Extended state. */
 typedef const X86FXSTATE *PCX86FXSTATE;
+
+/** Offset for software usable reserved bits (464:511) where we store a 32-bit
+ *  magic. Don't forget to update x86.mac if you change this! */
+#define X86_OFF_FXSTATE_RSVD            0x1d0
+/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
+ *  forget to update x86.mac if you change this! */
+#define X86_FXSTATE_RSVD_32BIT_MAGIC    0x32b3232b
+AssertCompileSize(X86FXSTATE, 512);
+AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, 0x1d0);
 
 /** @name FPU status word flags.

trunk/include/iprt/x86.mac

@@ -271 +271 @@
 %define X86_DR7_RW_LEN_ALL_MASKS            0xffff0000
 %define X86_DR7_INIT_VAL                    0x400
+%define X86_OFF_FXSTATE_RSVD                0x1d0
+%define X86_FXSTATE_RSVD_32BIT_MAGIC        0x32b3232b
 %define MSR_P5_MC_ADDR                      0x00000000
 %define MSR_P5_MC_TYPE                      0x00000001