VirtualBox

Changeset 55001 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Mar 29, 2015 4:59:20 PM (10 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
99270
Message:

CPUMCTXCORE elimination.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r54908 r55001  
    37043704 * @param   pVCpu           Pointer to the VMCPU.
    37053705 * @param   pCpu            Pointer to the disassembler state.
    3706  * @param   pRegFrame       Pointer to the register frame.
    3707  */
    3708 static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
     3706 * @param   pCtx            The guest CPU context.
     3707 */
     3708static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
    37093709{
    37103710    DISQPVPARAMVAL Param1;
    37113711    RTGCPTR        GCPtrPage;
    37123712
    3713     int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
     3713    int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
    37143714    if (RT_FAILURE(rc))
    37153715        return VERR_EM_INTERPRETER;
     
    37223722
    37233723        GCPtrPage = Param1.val.val64;
    3724         VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
     3724        VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
    37253725        rc = VBOXSTRICTRC_VAL(rc2);
    37263726    }
     
    37443744 *
    37453745 * @param   pVM         Pointer to the VM.
    3746  * @param   pRegFrame   Pointer to the register frame.
     3746 * @param   pCtx        The guest CPU context.
    37473747 *
    37483748 * @remarks Updates the RIP if the instruction was executed successfully.
    37493749 */
    3750 static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
     3750static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
    37513751{
    37523752    /* Only allow 32 & 64 bit code. */
     
    37583758            && pDis->pCurInstr->uOpcode == OP_INVLPG)
    37593759        {
    3760             rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
     3760            rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
    37613761            if (RT_SUCCESS(rc))
    3762                 pRegFrame->rip += pDis->cbInstr;
     3762                pCtx->rip += pDis->cbInstr;
    37633763            return rc;
    37643764        }
     
    43264326
    43274327    /** @todo Decode Assist. */
    4328     int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx));    /* Updates RIP if successful. */
     4328    int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx);    /* Updates RIP if successful. */
    43294329    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
    43304330    Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
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