Changeset 55129 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Apr 8, 2015 11:31:47 AM (10 years ago)
- svn:sync-xref-src-repo-rev:
- 99427
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r55118 r55129 1214 1214 pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid; 1215 1215 1216 pVM->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVM);1217 1218 1216 if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */ 1219 1217 { … … 1229 1227 { 1230 1228 PVMCPU pVCpu = &pVM->aCpus[i]; 1231 pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID; 1232 pVCpu->hm.s.idLastCpu = NIL_RTCPUID; 1229 pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID; 1230 pVCpu->hm.s.idLastCpu = NIL_RTCPUID; 1231 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); 1233 1232 1234 1233 /* We'll aways increment this the first time (host uses ASID 0). */ -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r55118 r55129 670 670 Assert(pVM->hm.s.svm.fSupported); 671 671 672 uint32_t const fGimXcptIntercepts = pVM->hm.s.fGIMTrapXcptUD ? RT_BIT(X86_XCPT_UD) : 0;673 672 for (VMCPUID i = 0; i < pVM->cCpus; i++) 674 673 { … … 787 786 788 787 /* Apply the exceptions intercepts needed by the GIM provider. */ 789 pVmcb->ctrl.u32InterceptException |= fGimXcptIntercepts; 788 if (pVCpu->hm.s.fGIMTrapXcptUD) 789 pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_UD); 790 790 791 791 /* … … 1634 1634 1635 1635 /** 1636 * Loads the exception interrupts required for guest execution in the VMCB. 1637 * 1638 * @returns VBox status code. 1639 * @param pVCpu Pointer to the VMCPU. 1640 * @param pVmcb Pointer to the VM control block. 1641 * @param pCtx Pointer to the guest-CPU context. 1642 */ 1643 static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx) 1644 { 1645 int rc = VINF_SUCCESS; 1646 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS)) 1647 { 1648 if (pVCpu->hm.s.fGIMTrapXcptUD) 1649 hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD); 1650 else 1651 hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD); 1652 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 1653 } 1654 return rc; 1655 } 1656 1657 1658 /** 1636 1659 * Sets up the appropriate function to run guest code. 1637 1660 * … … 1816 1839 rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx); 1817 1840 AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc); 1841 1842 rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx); 1843 AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc); 1818 1844 1819 1845 rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx); … … 5008 5034 else if (rc == VERR_NOT_FOUND) 5009 5035 { 5010 PVM pVM = pVCpu->CTX_SUFF(pVM); 5011 if (pVM->hm.s.fHypercallsEnabled) 5036 if (pVCpu->hm.s.fHypercallsEnabled) 5012 5037 { 5013 5038 rc = GIMHypercall(pVCpu, pCtx); … … 5227 5252 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(); 5228 5253 5229 PVM pVM = pVCpu->CTX_SUFF(pVM); 5230 if (pVM->hm.s.fGIMTrapXcptUD) 5254 if (pVCpu->hm.s.fGIMTrapXcptUD) 5231 5255 GIMXcptUD(pVCpu, pCtx, NULL /* pDis */); 5232 5256 else -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r55118 r55129 2635 2635 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu)); 2636 2636 2637 uint32_t u32XcptBitmap = 0;2637 uint32_t u32XcptBitmap = pVCpu->hm.s.fGIMTrapXcptUD ? RT_BIT(X86_XCPT_UD) : 0; 2638 2638 2639 2639 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */ … … 3554 3554 3555 3555 /** 3556 * Loads the exception intercepts required for guest execution in the VMCS. 3557 * 3558 * @returns VBox status code. 3559 * @param pVCpu Pointer to the VMCPU. 3560 * @param pMixedCtx Pointer to the guest-CPU context. The data may be 3561 * out-of-sync. Make sure to update the required fields 3562 * before using them. 3563 */ 3564 static int hmR0VmxLoadGuestXcptIntercepts(PVMCPU pVCpu, PCPUMCTX pMixedCtx) 3565 { 3566 NOREF(pMixedCtx); 3567 int rc = VINF_SUCCESS; 3568 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS)) 3569 { 3570 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxLoadSharedCR0(). */ 3571 if (pVCpu->hm.s.fGIMTrapXcptUD) 3572 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_UD); 3573 else 3574 { 3575 #ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS 3576 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_UD); 3577 #endif 3578 } 3579 3580 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap); 3581 AssertRCReturn(rc, rc); 3582 3583 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 3584 Log4(("Load[%RU32]: VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu, 3585 pVCpu->hm.s.vmx.u32XcptBitmap, HMCPU_CF_VALUE(pVCpu))); 3586 } 3587 return rc; 3588 } 3589 3590 3591 /** 3556 3592 * Loads the guest's RIP into the guest-state area in the VMCS. 3557 3593 * … … 3779 3815 pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK; 3780 3816 } 3817 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 3781 3818 3782 3819 if (fInterceptNM) … … 3823 3860 u32GuestCR0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */ 3824 3861 3825 /* Write VT-x's view of the guest CR0 into the VMCS and update the exception bitmap. */3862 /* Write VT-x's view of the guest CR0 into the VMCS. */ 3826 3863 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0); 3827 AssertRCReturn(rc, rc);3828 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);3829 3864 AssertRCReturn(rc, rc); 3830 3865 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", pVCpu->idCpu, u32GuestCR0, uSetCR0, … … 4220 4255 if ( fInterceptDB 4221 4256 || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active) 4257 { 4222 4258 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_DB); 4259 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 4260 } 4223 4261 else 4224 4262 { 4225 4263 #ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS 4226 4264 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_DB); 4227 #endif 4228 } 4229 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap); 4230 AssertRCReturn(rc, rc); 4265 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 4266 #endif 4267 } 4231 4268 4232 4269 /* … … 8295 8332 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc); 8296 8333 8334 rc = hmR0VmxLoadGuestXcptIntercepts(pVCpu, pMixedCtx); 8335 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc); 8336 8297 8337 /* 8298 8338 * Loading Rflags here is fine, even though Rflags.TF might depend on guest debug state (which is not loaded here). … … 8354 8394 #endif 8355 8395 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS); 8396 } 8397 8398 /* Loading CR0, debug state might have changed intercepts, update VMCS. */ 8399 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS)) 8400 { 8401 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap); 8402 AssertRC(rc); 8403 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 8356 8404 } 8357 8405 … … 10243 10291 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall); 10244 10292 10245 PVM pVM = pVCpu->CTX_SUFF(pVM); 10246 if (pVM->hm.s.fHypercallsEnabled) 10293 if (pVCpu->hm.s.fHypercallsEnabled) 10247 10294 { 10248 10295 #if 0 … … 11405 11452 #ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS 11406 11453 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_DB); 11407 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap); 11408 AssertRCReturn(rc, rc); 11454 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS); 11409 11455 #endif 11410 11456 }
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