- Timestamp:
- May 21, 2015 7:22:15 PM (10 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r55899 r56021 136 136 typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PIEMCPU pIemCpu); 137 137 # define FNIEMOP_DEF(a_Name) \ 138 staticVBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu)138 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu) 139 139 # define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \ 140 staticVBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0)140 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) 141 141 # define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \ 142 staticVBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1)142 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) 143 143 144 144 #elif defined(_MSC_VER) && defined(RT_ARCH_X86) 145 145 typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PIEMCPU pIemCpu); 146 146 # define FNIEMOP_DEF(a_Name) \ 147 static/*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu) RT_NO_THROW147 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu) RT_NO_THROW 148 148 # define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \ 149 static/*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW149 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW 150 150 # define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \ 151 static/*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW151 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW 152 152 153 153 #elif defined(__GNUC__) 154 154 typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); 155 155 # define FNIEMOP_DEF(a_Name) \ 156 staticVBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu)156 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu) 157 157 # define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \ 158 staticVBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0)158 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) 159 159 # define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \ 160 staticVBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1)160 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) 161 161 162 162 #else 163 163 typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); 164 164 # define FNIEMOP_DEF(a_Name) \ 165 staticVBOXSTRICTRC a_Name(PIEMCPU pIemCpu) RT_NO_THROW165 IEM_STATIC VBOXSTRICTRC a_Name(PIEMCPU pIemCpu) RT_NO_THROW 166 166 # define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \ 167 staticVBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW167 IEM_STATIC VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW 168 168 # define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \ 169 staticVBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW169 IEM_STATIC VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW 170 170 171 171 #endif … … 323 323 324 324 /** Function table for the ADD instruction. */ 325 staticconst IEMOPBINSIZES g_iemAImpl_add =325 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_add = 326 326 { 327 327 iemAImpl_add_u8, iemAImpl_add_u8_locked, … … 332 332 333 333 /** Function table for the ADC instruction. */ 334 staticconst IEMOPBINSIZES g_iemAImpl_adc =334 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_adc = 335 335 { 336 336 iemAImpl_adc_u8, iemAImpl_adc_u8_locked, … … 341 341 342 342 /** Function table for the SUB instruction. */ 343 staticconst IEMOPBINSIZES g_iemAImpl_sub =343 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_sub = 344 344 { 345 345 iemAImpl_sub_u8, iemAImpl_sub_u8_locked, … … 350 350 351 351 /** Function table for the SBB instruction. */ 352 staticconst IEMOPBINSIZES g_iemAImpl_sbb =352 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_sbb = 353 353 { 354 354 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked, … … 359 359 360 360 /** Function table for the OR instruction. */ 361 staticconst IEMOPBINSIZES g_iemAImpl_or =361 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_or = 362 362 { 363 363 iemAImpl_or_u8, iemAImpl_or_u8_locked, … … 368 368 369 369 /** Function table for the XOR instruction. */ 370 staticconst IEMOPBINSIZES g_iemAImpl_xor =370 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_xor = 371 371 { 372 372 iemAImpl_xor_u8, iemAImpl_xor_u8_locked, … … 377 377 378 378 /** Function table for the AND instruction. */ 379 staticconst IEMOPBINSIZES g_iemAImpl_and =379 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_and = 380 380 { 381 381 iemAImpl_and_u8, iemAImpl_and_u8_locked, … … 388 388 * @remarks Making operand order ASSUMPTIONS. 389 389 */ 390 staticconst IEMOPBINSIZES g_iemAImpl_cmp =390 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_cmp = 391 391 { 392 392 iemAImpl_cmp_u8, NULL, … … 399 399 * @remarks Making operand order ASSUMPTIONS. 400 400 */ 401 staticconst IEMOPBINSIZES g_iemAImpl_test =401 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_test = 402 402 { 403 403 iemAImpl_test_u8, NULL, … … 408 408 409 409 /** Function table for the BT instruction. */ 410 staticconst IEMOPBINSIZES g_iemAImpl_bt =410 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bt = 411 411 { 412 412 NULL, NULL, … … 417 417 418 418 /** Function table for the BTC instruction. */ 419 staticconst IEMOPBINSIZES g_iemAImpl_btc =419 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_btc = 420 420 { 421 421 NULL, NULL, … … 426 426 427 427 /** Function table for the BTR instruction. */ 428 staticconst IEMOPBINSIZES g_iemAImpl_btr =428 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_btr = 429 429 { 430 430 NULL, NULL, … … 435 435 436 436 /** Function table for the BTS instruction. */ 437 staticconst IEMOPBINSIZES g_iemAImpl_bts =437 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bts = 438 438 { 439 439 NULL, NULL, … … 444 444 445 445 /** Function table for the BSF instruction. */ 446 staticconst IEMOPBINSIZES g_iemAImpl_bsf =446 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf = 447 447 { 448 448 NULL, NULL, … … 453 453 454 454 /** Function table for the BSR instruction. */ 455 staticconst IEMOPBINSIZES g_iemAImpl_bsr =455 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr = 456 456 { 457 457 NULL, NULL, … … 462 462 463 463 /** Function table for the IMUL instruction. */ 464 staticconst IEMOPBINSIZES g_iemAImpl_imul_two =464 IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two = 465 465 { 466 466 NULL, NULL, … … 471 471 472 472 /** Group 1 /r lookup table. */ 473 staticconst PCIEMOPBINSIZES g_apIemImplGrp1[8] =473 IEM_STATIC const PCIEMOPBINSIZES g_apIemImplGrp1[8] = 474 474 { 475 475 &g_iemAImpl_add, … … 484 484 485 485 /** Function table for the INC instruction. */ 486 staticconst IEMOPUNARYSIZES g_iemAImpl_inc =486 IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_inc = 487 487 { 488 488 iemAImpl_inc_u8, iemAImpl_inc_u8_locked, … … 493 493 494 494 /** Function table for the DEC instruction. */ 495 staticconst IEMOPUNARYSIZES g_iemAImpl_dec =495 IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_dec = 496 496 { 497 497 iemAImpl_dec_u8, iemAImpl_dec_u8_locked, … … 502 502 503 503 /** Function table for the NEG instruction. */ 504 staticconst IEMOPUNARYSIZES g_iemAImpl_neg =504 IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_neg = 505 505 { 506 506 iemAImpl_neg_u8, iemAImpl_neg_u8_locked, … … 511 511 512 512 /** Function table for the NOT instruction. */ 513 staticconst IEMOPUNARYSIZES g_iemAImpl_not =513 IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_not = 514 514 { 515 515 iemAImpl_not_u8, iemAImpl_not_u8_locked, … … 521 521 522 522 /** Function table for the ROL instruction. */ 523 staticconst IEMOPSHIFTSIZES g_iemAImpl_rol =523 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol = 524 524 { 525 525 iemAImpl_rol_u8, … … 530 530 531 531 /** Function table for the ROR instruction. */ 532 staticconst IEMOPSHIFTSIZES g_iemAImpl_ror =532 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror = 533 533 { 534 534 iemAImpl_ror_u8, … … 539 539 540 540 /** Function table for the RCL instruction. */ 541 staticconst IEMOPSHIFTSIZES g_iemAImpl_rcl =541 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl = 542 542 { 543 543 iemAImpl_rcl_u8, … … 548 548 549 549 /** Function table for the RCR instruction. */ 550 staticconst IEMOPSHIFTSIZES g_iemAImpl_rcr =550 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr = 551 551 { 552 552 iemAImpl_rcr_u8, … … 557 557 558 558 /** Function table for the SHL instruction. */ 559 staticconst IEMOPSHIFTSIZES g_iemAImpl_shl =559 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl = 560 560 { 561 561 iemAImpl_shl_u8, … … 566 566 567 567 /** Function table for the SHR instruction. */ 568 staticconst IEMOPSHIFTSIZES g_iemAImpl_shr =568 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr = 569 569 { 570 570 iemAImpl_shr_u8, … … 575 575 576 576 /** Function table for the SAR instruction. */ 577 staticconst IEMOPSHIFTSIZES g_iemAImpl_sar =577 IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar = 578 578 { 579 579 iemAImpl_sar_u8, … … 585 585 586 586 /** Function table for the MUL instruction. */ 587 staticconst IEMOPMULDIVSIZES g_iemAImpl_mul =587 IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul = 588 588 { 589 589 iemAImpl_mul_u8, … … 594 594 595 595 /** Function table for the IMUL instruction working implicitly on rAX. */ 596 staticconst IEMOPMULDIVSIZES g_iemAImpl_imul =596 IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul = 597 597 { 598 598 iemAImpl_imul_u8, … … 603 603 604 604 /** Function table for the DIV instruction. */ 605 staticconst IEMOPMULDIVSIZES g_iemAImpl_div =605 IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div = 606 606 { 607 607 iemAImpl_div_u8, … … 612 612 613 613 /** Function table for the MUL instruction. */ 614 staticconst IEMOPMULDIVSIZES g_iemAImpl_idiv =614 IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv = 615 615 { 616 616 iemAImpl_idiv_u8, … … 621 621 622 622 /** Function table for the SHLD instruction */ 623 staticconst IEMOPSHIFTDBLSIZES g_iemAImpl_shld =623 IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld = 624 624 { 625 625 iemAImpl_shld_u16, … … 629 629 630 630 /** Function table for the SHRD instruction */ 631 staticconst IEMOPSHIFTDBLSIZES g_iemAImpl_shrd =631 IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd = 632 632 { 633 633 iemAImpl_shrd_u16, … … 638 638 639 639 /** Function table for the PUNPCKLBW instruction */ 640 staticconst IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw = { iemAImpl_punpcklbw_u64, iemAImpl_punpcklbw_u128 };640 IEM_STATIC const IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw = { iemAImpl_punpcklbw_u64, iemAImpl_punpcklbw_u128 }; 641 641 /** Function table for the PUNPCKLBD instruction */ 642 staticconst IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd = { iemAImpl_punpcklwd_u64, iemAImpl_punpcklwd_u128 };642 IEM_STATIC const IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd = { iemAImpl_punpcklwd_u64, iemAImpl_punpcklwd_u128 }; 643 643 /** Function table for the PUNPCKLDQ instruction */ 644 staticconst IEMOPMEDIAF1L1 g_iemAImpl_punpckldq = { iemAImpl_punpckldq_u64, iemAImpl_punpckldq_u128 };644 IEM_STATIC const IEMOPMEDIAF1L1 g_iemAImpl_punpckldq = { iemAImpl_punpckldq_u64, iemAImpl_punpckldq_u128 }; 645 645 /** Function table for the PUNPCKLQDQ instruction */ 646 staticconst IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq = { NULL, iemAImpl_punpcklqdq_u128 };646 IEM_STATIC const IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq = { NULL, iemAImpl_punpcklqdq_u128 }; 647 647 648 648 /** Function table for the PUNPCKHBW instruction */ 649 staticconst IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw = { iemAImpl_punpckhbw_u64, iemAImpl_punpckhbw_u128 };649 IEM_STATIC const IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw = { iemAImpl_punpckhbw_u64, iemAImpl_punpckhbw_u128 }; 650 650 /** Function table for the PUNPCKHBD instruction */ 651 staticconst IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd = { iemAImpl_punpckhwd_u64, iemAImpl_punpckhwd_u128 };651 IEM_STATIC const IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd = { iemAImpl_punpckhwd_u64, iemAImpl_punpckhwd_u128 }; 652 652 /** Function table for the PUNPCKHDQ instruction */ 653 staticconst IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq = { iemAImpl_punpckhdq_u64, iemAImpl_punpckhdq_u128 };653 IEM_STATIC const IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq = { iemAImpl_punpckhdq_u64, iemAImpl_punpckhdq_u128 }; 654 654 /** Function table for the PUNPCKHQDQ instruction */ 655 staticconst IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq = { NULL, iemAImpl_punpckhqdq_u128 };655 IEM_STATIC const IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq = { NULL, iemAImpl_punpckhqdq_u128 }; 656 656 657 657 /** Function table for the PXOR instruction */ 658 staticconst IEMOPMEDIAF2 g_iemAImpl_pxor = { iemAImpl_pxor_u64, iemAImpl_pxor_u128 };658 IEM_STATIC const IEMOPMEDIAF2 g_iemAImpl_pxor = { iemAImpl_pxor_u64, iemAImpl_pxor_u128 }; 659 659 /** Function table for the PCMPEQB instruction */ 660 staticconst IEMOPMEDIAF2 g_iemAImpl_pcmpeqb = { iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqb_u128 };660 IEM_STATIC const IEMOPMEDIAF2 g_iemAImpl_pcmpeqb = { iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqb_u128 }; 661 661 /** Function table for the PCMPEQW instruction */ 662 staticconst IEMOPMEDIAF2 g_iemAImpl_pcmpeqw = { iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqw_u128 };662 IEM_STATIC const IEMOPMEDIAF2 g_iemAImpl_pcmpeqw = { iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqw_u128 }; 663 663 /** Function table for the PCMPEQD instruction */ 664 staticconst IEMOPMEDIAF2 g_iemAImpl_pcmpeqd = { iemAImpl_pcmpeqd_u64, iemAImpl_pcmpeqd_u128 };664 IEM_STATIC const IEMOPMEDIAF2 g_iemAImpl_pcmpeqd = { iemAImpl_pcmpeqd_u64, iemAImpl_pcmpeqd_u128 }; 665 665 666 666 … … 676 676 * Internal Functions * 677 677 *******************************************************************************/ 678 staticVBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr);679 staticVBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu);680 staticVBOXSTRICTRC iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu);681 staticVBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel);682 /* staticVBOXSTRICTRC iemRaiseSelectorNotPresent(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);*/683 staticVBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel);684 staticVBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr);685 staticVBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel);686 staticVBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr);687 staticVBOXSTRICTRC iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr);688 staticVBOXSTRICTRC iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu);689 staticVBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL uSel);690 staticVBOXSTRICTRC iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);691 staticVBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel);692 staticVBOXSTRICTRC iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);693 staticVBOXSTRICTRC iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc);694 staticVBOXSTRICTRC iemRaiseAlignmentCheckException(PIEMCPU pIemCpu);695 staticVBOXSTRICTRC iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess);696 staticVBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess);697 staticVBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);698 staticVBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);699 staticVBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);700 staticVBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);701 staticVBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);702 staticVBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);703 staticVBOXSTRICTRC iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt, uint16_t uErrorCode);704 staticVBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt);705 staticVBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp);706 staticVBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void **ppvMem, uint64_t *puNewRsp);707 staticVBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value);708 staticVBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value);709 staticVBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel);710 staticuint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg);678 IEM_STATIC VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr); 679 IEM_STATIC VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu); 680 IEM_STATIC VBOXSTRICTRC iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu); 681 IEM_STATIC VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel); 682 /*IEM_STATIC VBOXSTRICTRC iemRaiseSelectorNotPresent(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);*/ 683 IEM_STATIC VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel); 684 IEM_STATIC VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr); 685 IEM_STATIC VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel); 686 IEM_STATIC VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr); 687 IEM_STATIC VBOXSTRICTRC iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr); 688 IEM_STATIC VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu); 689 IEM_STATIC VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL uSel); 690 IEM_STATIC VBOXSTRICTRC iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess); 691 IEM_STATIC VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel); 692 IEM_STATIC VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess); 693 IEM_STATIC VBOXSTRICTRC iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc); 694 IEM_STATIC VBOXSTRICTRC iemRaiseAlignmentCheckException(PIEMCPU pIemCpu); 695 IEM_STATIC VBOXSTRICTRC iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess); 696 IEM_STATIC VBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess); 697 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 698 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 699 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 700 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 701 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 702 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem); 703 IEM_STATIC VBOXSTRICTRC iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt, uint16_t uErrorCode); 704 IEM_STATIC VBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt); 705 IEM_STATIC VBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp); 706 IEM_STATIC VBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void **ppvMem, uint64_t *puNewRsp); 707 IEM_STATIC VBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value); 708 IEM_STATIC VBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value); 709 IEM_STATIC VBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel); 710 IEM_STATIC uint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg); 711 711 712 712 #if defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE_MINIMAL) 713 staticPIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu);713 IEM_STATIC PIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu); 714 714 #endif 715 staticVBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue);716 staticVBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue);715 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue); 716 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue); 717 717 718 718 … … 726 726 * VINF_SUCCESS is not allowed. 727 727 */ 728 staticint iemSetPassUpStatus(PIEMCPU pIemCpu, VBOXSTRICTRC rcPassUp)728 IEM_STATIC int iemSetPassUpStatus(PIEMCPU pIemCpu, VBOXSTRICTRC rcPassUp) 729 729 { 730 730 AssertRC(VBOXSTRICTRC_VAL(rcPassUp)); Assert(rcPassUp != VINF_SUCCESS); … … 911 911 * @param fBypassHandlers Whether to bypass access handlers. 912 912 */ 913 staticVBOXSTRICTRC iemInitDecoderAndPrefetchOpcodes(PIEMCPU pIemCpu, bool fBypassHandlers)913 IEM_STATIC VBOXSTRICTRC iemInitDecoderAndPrefetchOpcodes(PIEMCPU pIemCpu, bool fBypassHandlers) 914 914 { 915 915 #ifdef IEM_VERIFICATION_MODE_FULL … … 1027 1027 1028 1028 if (!pIemCpu->fBypassHandlers) 1029 rc = PGMPhysRead(pVM, GCPhys, pIemCpu->abOpcode, cbToTryRead, PGMACCESSORIGIN_IEM); 1029 { 1030 VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, GCPhys, pIemCpu->abOpcode, cbToTryRead, PGMACCESSORIGIN_IEM); 1031 if (RT_LIKELY(rcStrict == VINF_SUCCESS)) 1032 { /* likely */ } 1033 else 1034 { 1035 Log(("iemInitDecoderAndPrefetchOpcodes: %RGv/%RGp LB %#x - read error - rc=%Rrc (!!)\n", 1036 GCPtrPC, GCPhys, rc, cbToTryRead)); 1037 return rc; 1038 } 1039 } 1030 1040 else 1041 { 1031 1042 rc = PGMPhysSimpleReadGCPhys(pVM, pIemCpu->abOpcode, GCPhys, cbToTryRead); 1032 if (rc != VINF_SUCCESS) 1033 { 1034 /** @todo status code handling */ 1035 Log(("iemInitDecoderAndPrefetchOpcodes: %RGv/%RGp LB %#x - read error - rc=%Rrc (!!)\n", 1036 GCPtrPC, GCPhys, rc, cbToTryRead)); 1037 return rc; 1043 if (RT_SUCCESS(rc)) 1044 { /* likely */ } 1045 else 1046 { 1047 Log(("iemInitDecoderAndPrefetchOpcodes: %RGv/%RGp LB %#x - read error - rc=%Rrc (!!)\n", 1048 GCPtrPC, GCPhys, rc, cbToTryRead)); 1049 return rc; 1050 } 1038 1051 } 1039 1052 pIemCpu->cbOpcode = cbToTryRead; … … 1053 1066 * that must be read. 1054 1067 */ 1055 staticVBOXSTRICTRC iemOpcodeFetchMoreBytes(PIEMCPU pIemCpu, size_t cbMin)1068 IEM_STATIC VBOXSTRICTRC iemOpcodeFetchMoreBytes(PIEMCPU pIemCpu, size_t cbMin) 1056 1069 { 1057 1070 /* … … 1168 1181 * @param pb Where to return the opcode byte. 1169 1182 */ 1170 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU8Slow(PIEMCPU pIemCpu, uint8_t *pb)1183 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU8Slow(PIEMCPU pIemCpu, uint8_t *pb) 1171 1184 { 1172 1185 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 1); … … 1254 1267 * @param pu16 Where to return the opcode dword. 1255 1268 */ 1256 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU16Slow(PIEMCPU pIemCpu, uint16_t *pu16)1269 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextS8SxU16Slow(PIEMCPU pIemCpu, uint16_t *pu16) 1257 1270 { 1258 1271 uint8_t u8; … … 1307 1320 * @param pu32 Where to return the opcode dword. 1308 1321 */ 1309 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)1322 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextS8SxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32) 1310 1323 { 1311 1324 uint8_t u8; … … 1360 1373 * @param pu64 Where to return the opcode qword. 1361 1374 */ 1362 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)1375 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextS8SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) 1363 1376 { 1364 1377 uint8_t u8; … … 1413 1426 * @param pu16 Where to return the opcode word. 1414 1427 */ 1415 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU16Slow(PIEMCPU pIemCpu, uint16_t *pu16)1428 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU16Slow(PIEMCPU pIemCpu, uint16_t *pu16) 1416 1429 { 1417 1430 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2); … … 1469 1482 * @param pu32 Where to return the opcode double word. 1470 1483 */ 1471 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)1484 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32) 1472 1485 { 1473 1486 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2); … … 1526 1539 * @param pu64 Where to return the opcode quad word. 1527 1540 */ 1528 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)1541 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) 1529 1542 { 1530 1543 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2); … … 1612 1625 * @param pu32 Where to return the opcode dword. 1613 1626 */ 1614 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)1627 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU32Slow(PIEMCPU pIemCpu, uint32_t *pu32) 1615 1628 { 1616 1629 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4); … … 1674 1687 * @param pu32 Where to return the opcode dword. 1675 1688 */ 1676 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)1689 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) 1677 1690 { 1678 1691 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4); … … 1765 1778 * @param pu64 Where to return the opcode qword. 1766 1779 */ 1767 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextS32SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)1780 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextS32SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) 1768 1781 { 1769 1782 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4); … … 1829 1842 * @param pu64 Where to return the opcode qword. 1830 1843 */ 1831 DECL_NO_INLINE( static, VBOXSTRICTRC) iemOpcodeGetNextU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)1844 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemOpcodeGetNextU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) 1832 1845 { 1833 1846 VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 8); … … 1907 1920 * @param pDesc Where to return the descriptor. 1908 1921 */ 1909 staticVBOXSTRICTRC iemMiscValidateNewSS(PIEMCPU pIemCpu, PCCPUMCTX pCtx, RTSEL NewSS, uint8_t uCpl, PIEMSELDESC pDesc)1922 IEM_STATIC VBOXSTRICTRC iemMiscValidateNewSS(PIEMCPU pIemCpu, PCCPUMCTX pCtx, RTSEL NewSS, uint8_t uCpl, PIEMSELDESC pDesc) 1910 1923 { 1911 1924 NOREF(pCtx); … … 2042 2055 * @param puEsp Where to return the new stack pointer. 2043 2056 */ 2044 staticVBOXSTRICTRC iemRaiseLoadStackFromTss32Or16(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl,2045 PRTSEL pSelSS, uint32_t *puEsp)2057 IEM_STATIC VBOXSTRICTRC iemRaiseLoadStackFromTss32Or16(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl, 2058 PRTSEL pSelSS, uint32_t *puEsp) 2046 2059 { 2047 2060 VBOXSTRICTRC rcStrict; … … 2117 2130 * @param puRsp Where to return the new stack pointer. 2118 2131 */ 2119 static VBOXSTRICTRC iemRaiseLoadStackFromTss64(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl, uint8_t uIst, 2120 uint64_t *puRsp) 2132 IEM_STATIC VBOXSTRICTRC iemRaiseLoadStackFromTss64(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl, uint8_t uIst, uint64_t *puRsp) 2121 2133 { 2122 2134 Assert(uCpl < 4); … … 2172 2184 * @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set. 2173 2185 */ 2174 staticVBOXSTRICTRC2186 IEM_STATIC VBOXSTRICTRC 2175 2187 iemRaiseXcptOrIntInRealMode(PIEMCPU pIemCpu, 2176 2188 PCPUMCTX pCtx, … … 2242 2254 * @param pSReg Pointer to the segment register. 2243 2255 */ 2244 staticvoid iemHlpLoadNullDataSelectorOnV86Xcpt(PIEMCPU pIemCpu, PCPUMSELREG pSReg)2256 IEM_STATIC void iemHlpLoadNullDataSelectorOnV86Xcpt(PIEMCPU pIemCpu, PCPUMSELREG pSReg) 2245 2257 { 2246 2258 pSReg->Sel = 0; … … 2269 2281 * @param uSel The selector value to load. 2270 2282 */ 2271 staticvoid iemHlpLoadSelectorInV86Mode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel)2283 IEM_STATIC void iemHlpLoadSelectorInV86Mode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel) 2272 2284 { 2273 2285 /* See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */ … … 2289 2301 * @param uRpl The RPL. 2290 2302 */ 2291 staticvoid iemHlpLoadNullDataSelectorProt(PIEMCPU pIemCpu, PCPUMSELREG pSReg, RTSEL uRpl)2303 IEM_STATIC void iemHlpLoadNullDataSelectorProt(PIEMCPU pIemCpu, PCPUMSELREG pSReg, RTSEL uRpl) 2292 2304 { 2293 2305 /** @todo Testcase: write a testcase checking what happends when loading a NULL … … 2324 2336 * @remarks This expects pIemCpu->uCpl to be up to date. 2325 2337 */ 2326 staticVBOXSTRICTRC iemHlpTaskSwitchLoadDataSelectorInProtMode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel)2338 IEM_STATIC VBOXSTRICTRC iemHlpTaskSwitchLoadDataSelectorInProtMode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel) 2327 2339 { 2328 2340 Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT); … … 2432 2444 * @param pNewDescTSS Pointer to the new TSS descriptor. 2433 2445 */ 2434 static VBOXSTRICTRC iemTaskSwitch(PIEMCPU pIemCpu, 2435 PCPUMCTX pCtx, 2436 IEMTASKSWITCH enmTaskSwitch, 2437 uint32_t uNextEip, 2438 uint32_t fFlags, 2439 uint16_t uErr, 2440 uint64_t uCr2, 2441 RTSEL SelTSS, 2442 PIEMSELDESC pNewDescTSS) 2446 IEM_STATIC VBOXSTRICTRC 2447 iemTaskSwitch(PIEMCPU pIemCpu, 2448 PCPUMCTX pCtx, 2449 IEMTASKSWITCH enmTaskSwitch, 2450 uint32_t uNextEip, 2451 uint32_t fFlags, 2452 uint16_t uErr, 2453 uint64_t uCr2, 2454 RTSEL SelTSS, 2455 PIEMSELDESC pNewDescTSS) 2443 2456 { 2444 2457 Assert(!IEM_IS_REAL_MODE(pIemCpu)); … … 3163 3176 * @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set. 3164 3177 */ 3165 staticVBOXSTRICTRC3178 IEM_STATIC VBOXSTRICTRC 3166 3179 iemRaiseXcptOrIntInProtMode(PIEMCPU pIemCpu, 3167 3180 PCPUMCTX pCtx, … … 3598 3611 * @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set. 3599 3612 */ 3600 staticVBOXSTRICTRC3613 IEM_STATIC VBOXSTRICTRC 3601 3614 iemRaiseXcptOrIntInLongMode(PIEMCPU pIemCpu, 3602 3615 PCPUMCTX pCtx, … … 3843 3856 * @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set. 3844 3857 */ 3845 DECL_NO_INLINE( static, VBOXSTRICTRC)3858 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) 3846 3859 iemRaiseXcptOrInt(PIEMCPU pIemCpu, 3847 3860 uint8_t cbInstr, … … 3976 3989 3977 3990 /** \#DE - 00. */ 3978 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseDivideError(PIEMCPU pIemCpu)3991 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseDivideError(PIEMCPU pIemCpu) 3979 3992 { 3980 3993 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); … … 3984 3997 /** \#DB - 01. 3985 3998 * @note This automatically clear DR7.GD. */ 3986 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseDebugException(PIEMCPU pIemCpu)3999 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseDebugException(PIEMCPU pIemCpu) 3987 4000 { 3988 4001 /** @todo set/clear RF. */ … … 3993 4006 3994 4007 /** \#UD - 06. */ 3995 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseUndefinedOpcode(PIEMCPU pIemCpu)4008 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseUndefinedOpcode(PIEMCPU pIemCpu) 3996 4009 { 3997 4010 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); … … 4000 4013 4001 4014 /** \#NM - 07. */ 4002 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseDeviceNotAvailable(PIEMCPU pIemCpu)4015 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseDeviceNotAvailable(PIEMCPU pIemCpu) 4003 4016 { 4004 4017 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); … … 4007 4020 4008 4021 /** \#TS(err) - 0a. */ 4009 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr)4022 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr) 4010 4023 { 4011 4024 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); … … 4014 4027 4015 4028 /** \#TS(tr) - 0a. */ 4016 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu)4029 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu) 4017 4030 { 4018 4031 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4022 4035 4023 4036 /** \#TS(0) - 0a. */ 4024 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu)4037 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu) 4025 4038 { 4026 4039 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4030 4043 4031 4044 /** \#TS(err) - 0a. */ 4032 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel)4045 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel) 4033 4046 { 4034 4047 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4038 4051 4039 4052 /** \#NP(err) - 0b. */ 4040 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr)4053 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr) 4041 4054 { 4042 4055 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); … … 4045 4058 4046 4059 /** \#NP(seg) - 0b. */ 4047 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySegReg(PIEMCPU pIemCpu, uint32_t iSegReg)4060 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySegReg(PIEMCPU pIemCpu, uint32_t iSegReg) 4048 4061 { 4049 4062 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4053 4066 4054 4067 /** \#NP(sel) - 0b. */ 4055 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel)4068 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel) 4056 4069 { 4057 4070 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4061 4074 4062 4075 /** \#SS(seg) - 0c. */ 4063 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel)4076 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel) 4064 4077 { 4065 4078 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_SS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4069 4082 4070 4083 /** \#SS(err) - 0c. */ 4071 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr)4084 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr) 4072 4085 { 4073 4086 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_SS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); … … 4076 4089 4077 4090 /** \#GP(n) - 0d. */ 4078 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr)4091 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr) 4079 4092 { 4080 4093 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); … … 4083 4096 4084 4097 /** \#GP(0) - 0d. */ 4085 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu)4098 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu) 4086 4099 { 4087 4100 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); … … 4090 4103 4091 4104 /** \#GP(sel) - 0d. */ 4092 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel)4105 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel) 4093 4106 { 4094 4107 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, … … 4098 4111 4099 4112 /** \#GP(0) - 0d. */ 4100 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseNotCanonical(PIEMCPU pIemCpu)4113 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseNotCanonical(PIEMCPU pIemCpu) 4101 4114 { 4102 4115 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); … … 4105 4118 4106 4119 /** \#GP(sel) - 0d. */ 4107 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess)4120 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) 4108 4121 { 4109 4122 NOREF(iSegReg); NOREF(fAccess); … … 4114 4127 4115 4128 /** \#GP(sel) - 0d. */ 4116 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel)4129 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel) 4117 4130 { 4118 4131 NOREF(Sel); … … 4122 4135 4123 4136 /** \#GP(sel) - 0d. */ 4124 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess)4137 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) 4125 4138 { 4126 4139 NOREF(iSegReg); NOREF(fAccess); … … 4130 4143 4131 4144 /** \#PF(n) - 0e. */ 4132 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc)4145 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) 4133 4146 { 4134 4147 uint16_t uErr; … … 4179 4192 4180 4193 /** \#MF(0) - 10. */ 4181 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseMathFault(PIEMCPU pIemCpu)4194 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseMathFault(PIEMCPU pIemCpu) 4182 4195 { 4183 4196 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); … … 4186 4199 4187 4200 /** \#AC(0) - 11. */ 4188 DECL_NO_INLINE( static, VBOXSTRICTRC) iemRaiseAlignmentCheckException(PIEMCPU pIemCpu)4201 DECL_NO_INLINE(IEM_STATIC, VBOXSTRICTRC) iemRaiseAlignmentCheckException(PIEMCPU pIemCpu) 4189 4202 { 4190 4203 return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_AC, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); … … 4256 4269 * @param pIemCpu The IEM state. 4257 4270 */ 4258 staticvoid iemRecalEffOpSize(PIEMCPU pIemCpu)4271 IEM_STATIC void iemRecalEffOpSize(PIEMCPU pIemCpu) 4259 4272 { 4260 4273 switch (pIemCpu->enmCpuMode) … … 4293 4306 * @param pIemCpu The IEM state. 4294 4307 */ 4295 staticvoid iemRecalEffOpSize64Default(PIEMCPU pIemCpu)4308 IEM_STATIC void iemRecalEffOpSize64Default(PIEMCPU pIemCpu) 4296 4309 { 4297 4310 Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT); … … 4317 4330 * @param pIemCpu The IEM per CPU state. 4318 4331 */ 4319 staticvoid iemOpStubMsg2(PIEMCPU pIemCpu)4332 IEM_STATIC void iemOpStubMsg2(PIEMCPU pIemCpu) 4320 4333 { 4321 4334 #if defined(LOG_ENABLED) && defined(IN_RING3) … … 4429 4442 * @param iSegReg The segment register. 4430 4443 */ 4431 staticPCPUMSELREG iemSRegGetHid(PIEMCPU pIemCpu, uint8_t iSegReg)4444 IEM_STATIC PCPUMSELREG iemSRegGetHid(PIEMCPU pIemCpu, uint8_t iSegReg) 4432 4445 { 4433 4446 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4462 4475 * @param iSegReg The segment register. 4463 4476 */ 4464 staticuint16_t *iemSRegRef(PIEMCPU pIemCpu, uint8_t iSegReg)4477 IEM_STATIC uint16_t *iemSRegRef(PIEMCPU pIemCpu, uint8_t iSegReg) 4465 4478 { 4466 4479 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4485 4498 * @param iSegReg The segment register. 4486 4499 */ 4487 staticuint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg)4500 IEM_STATIC uint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg) 4488 4501 { 4489 4502 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4508 4521 * @param iReg The general register. 4509 4522 */ 4510 staticvoid *iemGRegRef(PIEMCPU pIemCpu, uint8_t iReg)4523 IEM_STATIC void *iemGRegRef(PIEMCPU pIemCpu, uint8_t iReg) 4511 4524 { 4512 4525 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4543 4556 * @param iReg The register. 4544 4557 */ 4545 staticuint8_t *iemGRegRefU8(PIEMCPU pIemCpu, uint8_t iReg)4558 IEM_STATIC uint8_t *iemGRegRefU8(PIEMCPU pIemCpu, uint8_t iReg) 4546 4559 { 4547 4560 if (pIemCpu->fPrefixes & IEM_OP_PRF_REX) … … 4562 4575 * @param iReg The register. 4563 4576 */ 4564 staticuint8_t iemGRegFetchU8(PIEMCPU pIemCpu, uint8_t iReg)4577 IEM_STATIC uint8_t iemGRegFetchU8(PIEMCPU pIemCpu, uint8_t iReg) 4565 4578 { 4566 4579 uint8_t const *pbSrc = iemGRegRefU8(pIemCpu, iReg); … … 4576 4589 * @param iReg The register. 4577 4590 */ 4578 staticuint16_t iemGRegFetchU16(PIEMCPU pIemCpu, uint8_t iReg)4591 IEM_STATIC uint16_t iemGRegFetchU16(PIEMCPU pIemCpu, uint8_t iReg) 4579 4592 { 4580 4593 return *(uint16_t *)iemGRegRef(pIemCpu, iReg); … … 4589 4602 * @param iReg The register. 4590 4603 */ 4591 staticuint32_t iemGRegFetchU32(PIEMCPU pIemCpu, uint8_t iReg)4604 IEM_STATIC uint32_t iemGRegFetchU32(PIEMCPU pIemCpu, uint8_t iReg) 4592 4605 { 4593 4606 return *(uint32_t *)iemGRegRef(pIemCpu, iReg); … … 4602 4615 * @param iReg The register. 4603 4616 */ 4604 staticuint64_t iemGRegFetchU64(PIEMCPU pIemCpu, uint8_t iReg)4617 IEM_STATIC uint64_t iemGRegFetchU64(PIEMCPU pIemCpu, uint8_t iReg) 4605 4618 { 4606 4619 return *(uint64_t *)iemGRegRef(pIemCpu, iReg); … … 4617 4630 * @param offNextInstr The offset of the next instruction. 4618 4631 */ 4619 staticVBOXSTRICTRC iemRegRipRelativeJumpS8(PIEMCPU pIemCpu, int8_t offNextInstr)4632 IEM_STATIC VBOXSTRICTRC iemRegRipRelativeJumpS8(PIEMCPU pIemCpu, int8_t offNextInstr) 4620 4633 { 4621 4634 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4673 4686 * @param offNextInstr The offset of the next instruction. 4674 4687 */ 4675 staticVBOXSTRICTRC iemRegRipRelativeJumpS16(PIEMCPU pIemCpu, int16_t offNextInstr)4688 IEM_STATIC VBOXSTRICTRC iemRegRipRelativeJumpS16(PIEMCPU pIemCpu, int16_t offNextInstr) 4676 4689 { 4677 4690 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4700 4713 * @param offNextInstr The offset of the next instruction. 4701 4714 */ 4702 staticVBOXSTRICTRC iemRegRipRelativeJumpS32(PIEMCPU pIemCpu, int32_t offNextInstr)4715 IEM_STATIC VBOXSTRICTRC iemRegRipRelativeJumpS32(PIEMCPU pIemCpu, int32_t offNextInstr) 4703 4716 { 4704 4717 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4737 4750 * @param uNewRip The new RIP value. 4738 4751 */ 4739 staticVBOXSTRICTRC iemRegRipJump(PIEMCPU pIemCpu, uint64_t uNewRip)4752 IEM_STATIC VBOXSTRICTRC iemRegRipJump(PIEMCPU pIemCpu, uint64_t uNewRip) 4740 4753 { 4741 4754 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4808 4821 * @param cbInstr The number of bytes to add. 4809 4822 */ 4810 staticvoid iemRegAddToRipKeepRF(PIEMCPU pIemCpu, uint8_t cbInstr)4823 IEM_STATIC void iemRegAddToRipKeepRF(PIEMCPU pIemCpu, uint8_t cbInstr) 4811 4824 { 4812 4825 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4838 4851 * @param pIemCpu The per CPU data. 4839 4852 */ 4840 staticvoid iemRegUpdateRipKeepRF(PIEMCPU pIemCpu)4853 IEM_STATIC void iemRegUpdateRipKeepRF(PIEMCPU pIemCpu) 4841 4854 { 4842 4855 return iemRegAddToRipKeepRF(pIemCpu, pIemCpu->offOpcode); … … 4852 4865 * @param cbInstr The number of bytes to add. 4853 4866 */ 4854 staticvoid iemRegAddToRipAndClearRF(PIEMCPU pIemCpu, uint8_t cbInstr)4867 IEM_STATIC void iemRegAddToRipAndClearRF(PIEMCPU pIemCpu, uint8_t cbInstr) 4855 4868 { 4856 4869 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 4884 4897 * @param pIemCpu The per CPU data. 4885 4898 */ 4886 staticvoid iemRegUpdateRipAndClearRF(PIEMCPU pIemCpu)4899 IEM_STATIC void iemRegUpdateRipAndClearRF(PIEMCPU pIemCpu) 4887 4900 { 4888 4901 return iemRegAddToRipAndClearRF(pIemCpu, pIemCpu->offOpcode); … … 5254 5267 * @param pFpuCtx The FPU context. 5255 5268 */ 5256 staticvoid iemFpuMaybePushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, PX86FXSTATE pFpuCtx)5269 IEM_STATIC void iemFpuMaybePushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, PX86FXSTATE pFpuCtx) 5257 5270 { 5258 5271 /* Update FSW and bail if there are pending exceptions afterwards. */ … … 5302 5315 * @param iStReg Which FPU register to store it in. 5303 5316 */ 5304 staticvoid iemFpuStoreResultOnly(PX86FXSTATE pFpuCtx, PIEMFPURESULT pResult, uint8_t iStReg)5317 IEM_STATIC void iemFpuStoreResultOnly(PX86FXSTATE pFpuCtx, PIEMFPURESULT pResult, uint8_t iStReg) 5305 5318 { 5306 5319 Assert(iStReg < 8); … … 5320 5333 * @param u16FSW The FSW output of the current instruction. 5321 5334 */ 5322 staticvoid iemFpuUpdateFSWOnly(PX86FXSTATE pFpuCtx, uint16_t u16FSW)5335 IEM_STATIC void iemFpuUpdateFSWOnly(PX86FXSTATE pFpuCtx, uint16_t u16FSW) 5323 5336 { 5324 5337 pFpuCtx->FSW &= ~X86_FSW_C_MASK; … … 5332 5345 * @param pFpuCtx The FPU context. 5333 5346 */ 5334 staticvoid iemFpuMaybePopOne(PX86FXSTATE pFpuCtx)5347 IEM_STATIC void iemFpuMaybePopOne(PX86FXSTATE pFpuCtx) 5335 5348 { 5336 5349 /* Check pending exceptions. */ … … 5361 5374 * @param pResult The FPU operation result to push. 5362 5375 */ 5363 staticvoid iemFpuPushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult)5376 IEM_STATIC void iemFpuPushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult) 5364 5377 { 5365 5378 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5379 5392 * @param GCPtrEff The effective address relative to @a iEffSeg. 5380 5393 */ 5381 staticvoid iemFpuPushResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff)5394 IEM_STATIC void iemFpuPushResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5382 5395 { 5383 5396 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5396 5409 * @param pResult The FPU operation result to store and push. 5397 5410 */ 5398 staticvoid iemFpuPushResultTwo(PIEMCPU pIemCpu, PIEMFPURESULTTWO pResult)5411 IEM_STATIC void iemFpuPushResultTwo(PIEMCPU pIemCpu, PIEMFPURESULTTWO pResult) 5399 5412 { 5400 5413 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5452 5465 * @param pCtx The CPU context. 5453 5466 */ 5454 staticvoid iemFpuStoreResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg)5467 IEM_STATIC void iemFpuStoreResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg) 5455 5468 { 5456 5469 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5470 5483 * @param pCtx The CPU context. 5471 5484 */ 5472 staticvoid iemFpuStoreResultThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg)5485 IEM_STATIC void iemFpuStoreResultThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg) 5473 5486 { 5474 5487 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5491 5504 * @param GCPtrEff The effective memory operand offset. 5492 5505 */ 5493 staticvoid iemFpuStoreResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)5506 IEM_STATIC void iemFpuStoreResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5494 5507 { 5495 5508 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5512 5525 * @param GCPtrEff The effective memory operand offset. 5513 5526 */ 5514 staticvoid iemFpuStoreResultWithMemOpThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult,5515 uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)5527 IEM_STATIC void iemFpuStoreResultWithMemOpThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult, 5528 uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5516 5529 { 5517 5530 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5529 5542 * @param pIemCpu The IEM per CPU data. 5530 5543 */ 5531 staticvoid iemFpuUpdateOpcodeAndIp(PIEMCPU pIemCpu)5544 IEM_STATIC void iemFpuUpdateOpcodeAndIp(PIEMCPU pIemCpu) 5532 5545 { 5533 5546 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5543 5556 * @param iStReg The register to free. 5544 5557 */ 5545 staticvoid iemFpuStackFree(PIEMCPU pIemCpu, uint8_t iStReg)5558 IEM_STATIC void iemFpuStackFree(PIEMCPU pIemCpu, uint8_t iStReg) 5546 5559 { 5547 5560 Assert(iStReg < 8); … … 5557 5570 * @param pIemCpu The IEM per CPU data. 5558 5571 */ 5559 staticvoid iemFpuStackIncTop(PIEMCPU pIemCpu)5572 IEM_STATIC void iemFpuStackIncTop(PIEMCPU pIemCpu) 5560 5573 { 5561 5574 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5574 5587 * @param pIemCpu The IEM per CPU data. 5575 5588 */ 5576 staticvoid iemFpuStackDecTop(PIEMCPU pIemCpu)5589 IEM_STATIC void iemFpuStackDecTop(PIEMCPU pIemCpu) 5577 5590 { 5578 5591 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5592 5605 * @param u16FSW The FSW from the current instruction. 5593 5606 */ 5594 staticvoid iemFpuUpdateFSW(PIEMCPU pIemCpu, uint16_t u16FSW)5607 IEM_STATIC void iemFpuUpdateFSW(PIEMCPU pIemCpu, uint16_t u16FSW) 5595 5608 { 5596 5609 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5607 5620 * @param u16FSW The FSW from the current instruction. 5608 5621 */ 5609 staticvoid iemFpuUpdateFSWThenPop(PIEMCPU pIemCpu, uint16_t u16FSW)5622 IEM_STATIC void iemFpuUpdateFSWThenPop(PIEMCPU pIemCpu, uint16_t u16FSW) 5610 5623 { 5611 5624 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5625 5638 * @param GCPtrEff The effective memory operand offset. 5626 5639 */ 5627 staticvoid iemFpuUpdateFSWWithMemOp(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff)5640 IEM_STATIC void iemFpuUpdateFSWWithMemOp(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5628 5641 { 5629 5642 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5641 5654 * @param u16FSW The FSW from the current instruction. 5642 5655 */ 5643 staticvoid iemFpuUpdateFSWThenPopPop(PIEMCPU pIemCpu, uint16_t u16FSW)5656 IEM_STATIC void iemFpuUpdateFSWThenPopPop(PIEMCPU pIemCpu, uint16_t u16FSW) 5644 5657 { 5645 5658 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5660 5673 * @param GCPtrEff The effective memory operand offset. 5661 5674 */ 5662 staticvoid iemFpuUpdateFSWWithMemOpThenPop(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff)5675 IEM_STATIC void iemFpuUpdateFSWWithMemOpThenPop(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5663 5676 { 5664 5677 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5678 5691 * @param iStReg The stack register being accessed. 5679 5692 */ 5680 staticvoid iemFpuStackUnderflowOnly(PIEMCPU pIemCpu, PX86FXSTATE pFpuCtx, uint8_t iStReg)5693 IEM_STATIC void iemFpuStackUnderflowOnly(PIEMCPU pIemCpu, PX86FXSTATE pFpuCtx, uint8_t iStReg) 5681 5694 { 5682 5695 Assert(iStReg < 8 || iStReg == UINT8_MAX); … … 5709 5722 * UINT8_MAX if none (like for fcom). 5710 5723 */ 5711 DECL_NO_INLINE( static, void) iemFpuStackUnderflow(PIEMCPU pIemCpu, uint8_t iStReg)5724 DECL_NO_INLINE(IEM_STATIC, void) iemFpuStackUnderflow(PIEMCPU pIemCpu, uint8_t iStReg) 5712 5725 { 5713 5726 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5718 5731 5719 5732 5720 DECL_NO_INLINE( static, void)5733 DECL_NO_INLINE(IEM_STATIC, void) 5721 5734 iemFpuStackUnderflowWithMemOp(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5722 5735 { … … 5729 5742 5730 5743 5731 DECL_NO_INLINE( static, void) iemFpuStackUnderflowThenPop(PIEMCPU pIemCpu, uint8_t iStReg)5744 DECL_NO_INLINE(IEM_STATIC, void) iemFpuStackUnderflowThenPop(PIEMCPU pIemCpu, uint8_t iStReg) 5732 5745 { 5733 5746 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5739 5752 5740 5753 5741 DECL_NO_INLINE( static, void)5754 DECL_NO_INLINE(IEM_STATIC, void) 5742 5755 iemFpuStackUnderflowWithMemOpThenPop(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5743 5756 { … … 5751 5764 5752 5765 5753 DECL_NO_INLINE( static, void) iemFpuStackUnderflowThenPopPop(PIEMCPU pIemCpu)5766 DECL_NO_INLINE(IEM_STATIC, void) iemFpuStackUnderflowThenPopPop(PIEMCPU pIemCpu) 5754 5767 { 5755 5768 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5762 5775 5763 5776 5764 DECL_NO_INLINE( static, void)5777 DECL_NO_INLINE(IEM_STATIC, void) 5765 5778 iemFpuStackPushUnderflow(PIEMCPU pIemCpu) 5766 5779 { … … 5789 5802 5790 5803 5791 DECL_NO_INLINE( static, void)5804 DECL_NO_INLINE(IEM_STATIC, void) 5792 5805 iemFpuStackPushUnderflowTwo(PIEMCPU pIemCpu) 5793 5806 { … … 5822 5835 * @param pFpuCtx The FPU context. 5823 5836 */ 5824 staticvoid iemFpuStackPushOverflowOnly(PX86FXSTATE pFpuCtx)5837 IEM_STATIC void iemFpuStackPushOverflowOnly(PX86FXSTATE pFpuCtx) 5825 5838 { 5826 5839 if (pFpuCtx->FCW & X86_FCW_IM) … … 5849 5862 * @param pIemCpu The IEM per CPU data. 5850 5863 */ 5851 DECL_NO_INLINE( static, void) iemFpuStackPushOverflow(PIEMCPU pIemCpu)5864 DECL_NO_INLINE(IEM_STATIC, void) iemFpuStackPushOverflow(PIEMCPU pIemCpu) 5852 5865 { 5853 5866 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 5865 5878 * @param GCPtrEff The effective memory operand offset. 5866 5879 */ 5867 DECL_NO_INLINE( static, void)5880 DECL_NO_INLINE(IEM_STATIC, void) 5868 5881 iemFpuStackPushOverflowWithMemOp(PIEMCPU pIemCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) 5869 5882 { … … 5876 5889 5877 5890 5878 staticint iemFpuStRegNotEmpty(PIEMCPU pIemCpu, uint8_t iStReg)5891 IEM_STATIC int iemFpuStRegNotEmpty(PIEMCPU pIemCpu, uint8_t iStReg) 5879 5892 { 5880 5893 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5886 5899 5887 5900 5888 staticint iemFpuStRegNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg, PCRTFLOAT80U *ppRef)5901 IEM_STATIC int iemFpuStRegNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg, PCRTFLOAT80U *ppRef) 5889 5902 { 5890 5903 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5899 5912 5900 5913 5901 staticint iemFpu2StRegsNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0,5902 uint8_t iStReg1, PCRTFLOAT80U *ppRef1)5914 IEM_STATIC int iemFpu2StRegsNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, 5915 uint8_t iStReg1, PCRTFLOAT80U *ppRef1) 5903 5916 { 5904 5917 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5916 5929 5917 5930 5918 staticint iemFpu2StRegsNotEmptyRefFirst(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, uint8_t iStReg1)5931 IEM_STATIC int iemFpu2StRegsNotEmptyRefFirst(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, uint8_t iStReg1) 5919 5932 { 5920 5933 PX86FXSTATE pFpuCtx = &pIemCpu->CTX_SUFF(pCtx)->CTX_SUFF(pXState)->x87; … … 5936 5949 * @param pFpuCtx The FPU context. 5937 5950 */ 5938 staticvoid iemFpuRecalcExceptionStatus(PX86FXSTATE pFpuCtx)5951 IEM_STATIC void iemFpuRecalcExceptionStatus(PX86FXSTATE pFpuCtx) 5939 5952 { 5940 5953 uint16_t u16Fsw = pFpuCtx->FSW; … … 5953 5966 * @param pFpuCtx The FPU context. 5954 5967 */ 5955 staticuint16_t iemFpuCalcFullFtw(PCX86FXSTATE pFpuCtx)5968 IEM_STATIC uint16_t iemFpuCalcFullFtw(PCX86FXSTATE pFpuCtx) 5956 5969 { 5957 5970 uint8_t const u8Ftw = (uint8_t)pFpuCtx->FTW; … … 5995 6008 * @param u16FullFtw The full FTW to convert. 5996 6009 */ 5997 staticuint16_t iemFpuCompressFtw(uint16_t u16FullFtw)6010 IEM_STATIC uint16_t iemFpuCompressFtw(uint16_t u16FullFtw) 5998 6011 { 5999 6012 uint8_t u8Ftw = 0; … … 6045 6058 * base in the hidden segment.) 6046 6059 */ 6047 static VBOXSTRICTRC iemMemSegCheckWriteAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr) 6060 IEM_STATIC VBOXSTRICTRC 6061 iemMemSegCheckWriteAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr) 6048 6062 { 6049 6063 if (pIemCpu->enmCpuMode == IEMMODE_64BIT) … … 6077 6091 * base in the hidden segment.) 6078 6092 */ 6079 static VBOXSTRICTRC iemMemSegCheckReadAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr) 6093 IEM_STATIC VBOXSTRICTRC 6094 iemMemSegCheckReadAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr) 6080 6095 { 6081 6096 if (pIemCpu->enmCpuMode == IEMMODE_64BIT) … … 6109 6124 * segmentation to. Input and output parameter. 6110 6125 */ 6111 static VBOXSTRICTRC iemMemApplySegment(PIEMCPU pIemCpu, uint32_t fAccess, uint8_t iSegReg, 6112 6126 IEM_STATIC VBOXSTRICTRC 6127 iemMemApplySegment(PIEMCPU pIemCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) 6113 6128 { 6114 6129 if (iSegReg == UINT8_MAX) … … 6204 6219 * @param pGCPhysMem Where to return the physical address. 6205 6220 */ 6206 static VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PIEMCPU pIemCpu, RTGCPTR GCPtrMem, uint32_t fAccess, 6207 6221 IEM_STATIC VBOXSTRICTRC 6222 iemMemPageTranslateAndCheckAccess(PIEMCPU pIemCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) 6208 6223 { 6209 6224 /** @todo Need a different PGM interface here. We're currently using … … 6286 6301 * @param pLock The PGM lock. 6287 6302 */ 6288 staticint iemMemPageMap(PIEMCPU pIemCpu, RTGCPHYS GCPhysMem, uint32_t fAccess, void **ppvMem, PPGMPAGEMAPLOCK pLock)6303 IEM_STATIC int iemMemPageMap(PIEMCPU pIemCpu, RTGCPHYS GCPhysMem, uint32_t fAccess, void **ppvMem, PPGMPAGEMAPLOCK pLock) 6289 6304 { 6290 6305 #ifdef IEM_VERIFICATION_MODE_FULL … … 6380 6395 * @param pIemCpu The IEM per CPU data. 6381 6396 */ 6382 staticunsigned iemMemMapFindFree(PIEMCPU pIemCpu)6397 IEM_STATIC unsigned iemMemMapFindFree(PIEMCPU pIemCpu) 6383 6398 { 6384 6399 /* … … 6409 6424 * @param iMemMap The index of the buffer to commit. 6410 6425 */ 6411 staticVBOXSTRICTRC iemMemBounceBufferCommitAndUnmap(PIEMCPU pIemCpu, unsigned iMemMap)6426 IEM_STATIC VBOXSTRICTRC iemMemBounceBufferCommitAndUnmap(PIEMCPU pIemCpu, unsigned iMemMap) 6412 6427 { 6413 6428 Assert(pIemCpu->aMemMappings[iMemMap].fAccess & IEM_ACCESS_BOUNCE_BUFFERED); … … 6527 6542 * iemMemMap worker that deals with a request crossing pages. 6528 6543 */ 6529 static VBOXSTRICTRC iemMemBounceBufferMapCrossPage(PIEMCPU pIemCpu, int iMemMap, void **ppvMem, 6530 6544 IEM_STATIC VBOXSTRICTRC 6545 iemMemBounceBufferMapCrossPage(PIEMCPU pIemCpu, int iMemMap, void **ppvMem, size_t cbMem, RTGCPTR GCPtrFirst, uint32_t fAccess) 6531 6546 { 6532 6547 /* … … 6669 6684 * iemMemMap woker that deals with iemMemPageMap failures. 6670 6685 */ 6671 staticVBOXSTRICTRC iemMemBounceBufferMapPhys(PIEMCPU pIemCpu, unsigned iMemMap, void **ppvMem, size_t cbMem,6672 RTGCPHYS GCPhysFirst, uint32_t fAccess, VBOXSTRICTRC rcMap)6686 IEM_STATIC VBOXSTRICTRC iemMemBounceBufferMapPhys(PIEMCPU pIemCpu, unsigned iMemMap, void **ppvMem, size_t cbMem, 6687 RTGCPHYS GCPhysFirst, uint32_t fAccess, VBOXSTRICTRC rcMap) 6673 6688 { 6674 6689 /* … … 6786 6801 * exceptions. 6787 6802 */ 6788 static VBOXSTRICTRC iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess) 6803 IEM_STATIC VBOXSTRICTRC 6804 iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess) 6789 6805 { 6790 6806 /* … … 6845 6861 * @param fAccess The kind of access. 6846 6862 */ 6847 staticVBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess)6863 IEM_STATIC VBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess) 6848 6864 { 6849 6865 int iMemMap = iemMapLookup(pIemCpu, pvMem, fAccess); … … 6876 6892 * @param pIemCpu The IEM per CPU data. 6877 6893 */ 6878 staticvoid iemMemRollback(PIEMCPU pIemCpu)6894 IEM_STATIC void iemMemRollback(PIEMCPU pIemCpu) 6879 6895 { 6880 6896 Assert(pIemCpu->cActiveMappings > 0); … … 6906 6922 * @param GCPtrMem The address of the guest memory. 6907 6923 */ 6908 staticVBOXSTRICTRC iemMemFetchDataU8(PIEMCPU pIemCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)6924 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU8(PIEMCPU pIemCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 6909 6925 { 6910 6926 /* The lazy approach for now... */ … … 6930 6946 * @param GCPtrMem The address of the guest memory. 6931 6947 */ 6932 staticVBOXSTRICTRC iemMemFetchDataU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)6948 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 6933 6949 { 6934 6950 /* The lazy approach for now... */ … … 6954 6970 * @param GCPtrMem The address of the guest memory. 6955 6971 */ 6956 staticVBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)6972 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 6957 6973 { 6958 6974 /* The lazy approach for now... */ … … 6979 6995 * @param GCPtrMem The address of the guest memory. 6980 6996 */ 6981 staticVBOXSTRICTRC iemMemFetchDataS32SxU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)6997 IEM_STATIC VBOXSTRICTRC iemMemFetchDataS32SxU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 6982 6998 { 6983 6999 /* The lazy approach for now... */ … … 7008 7024 * @param GCPtrMem The address of the guest memory. 7009 7025 */ 7010 staticVBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)7026 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7011 7027 { 7012 7028 /* The lazy approach for now... */ … … 7032 7048 * @param GCPtrMem The address of the guest memory. 7033 7049 */ 7034 staticVBOXSTRICTRC iemMemFetchDataU64AlignedU128(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)7050 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7035 7051 { 7036 7052 /* The lazy approach for now... */ … … 7060 7076 * @param GCPtrMem The address of the guest memory. 7061 7077 */ 7062 staticVBOXSTRICTRC iemMemFetchDataR80(PIEMCPU pIemCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)7078 IEM_STATIC VBOXSTRICTRC iemMemFetchDataR80(PIEMCPU pIemCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7063 7079 { 7064 7080 /* The lazy approach for now... */ … … 7084 7100 * @param GCPtrMem The address of the guest memory. 7085 7101 */ 7086 staticVBOXSTRICTRC iemMemFetchDataU128(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)7102 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU128(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7087 7103 { 7088 7104 /* The lazy approach for now... */ … … 7111 7127 * @param GCPtrMem The address of the guest memory. 7112 7128 */ 7113 staticVBOXSTRICTRC iemMemFetchDataU128AlignedSse(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)7129 IEM_STATIC VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7114 7130 { 7115 7131 /* The lazy approach for now... */ … … 7144 7160 * @param enmOpSize The effective operand size. 7145 7161 */ 7146 static VBOXSTRICTRC iemMemFetchDataXdtr(PIEMCPU pIemCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase,7147 uint8_t iSegReg,RTGCPTR GCPtrMem, IEMMODE enmOpSize)7162 IEM_STATIC VBOXSTRICTRC iemMemFetchDataXdtr(PIEMCPU pIemCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg, 7163 RTGCPTR GCPtrMem, IEMMODE enmOpSize) 7148 7164 { 7149 7165 uint8_t const *pu8Src; … … 7193 7209 * @param u8Value The value to store. 7194 7210 */ 7195 staticVBOXSTRICTRC iemMemStoreDataU8(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value)7211 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU8(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) 7196 7212 { 7197 7213 /* The lazy approach for now... */ … … 7217 7233 * @param u16Value The value to store. 7218 7234 */ 7219 staticVBOXSTRICTRC iemMemStoreDataU16(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value)7235 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU16(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) 7220 7236 { 7221 7237 /* The lazy approach for now... */ … … 7241 7257 * @param u32Value The value to store. 7242 7258 */ 7243 staticVBOXSTRICTRC iemMemStoreDataU32(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value)7259 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU32(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) 7244 7260 { 7245 7261 /* The lazy approach for now... */ … … 7265 7281 * @param u64Value The value to store. 7266 7282 */ 7267 staticVBOXSTRICTRC iemMemStoreDataU64(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value)7283 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU64(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) 7268 7284 { 7269 7285 /* The lazy approach for now... */ … … 7289 7305 * @param u64Value The value to store. 7290 7306 */ 7291 staticVBOXSTRICTRC iemMemStoreDataU128(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value)7307 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU128(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value) 7292 7308 { 7293 7309 /* The lazy approach for now... */ … … 7313 7329 * @param u64Value The value to store. 7314 7330 */ 7315 staticVBOXSTRICTRC iemMemStoreDataU128AlignedSse(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value)7331 IEM_STATIC VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value) 7316 7332 { 7317 7333 /* The lazy approach for now... */ … … 7343 7359 * @param enmOpSize The effective operand size. 7344 7360 */ 7345 static VBOXSTRICTRC iemMemStoreDataXdtr(PIEMCPU pIemCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, 7346 7361 IEM_STATIC VBOXSTRICTRC 7362 iemMemStoreDataXdtr(PIEMCPU pIemCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem, IEMMODE enmOpSize) 7347 7363 { 7348 7364 uint8_t *pu8Src; … … 7390 7406 * @param u16Value The value to push. 7391 7407 */ 7392 staticVBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value)7408 IEM_STATIC VBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value) 7393 7409 { 7394 7410 /* Increment the stack pointer. */ … … 7421 7437 * @param u32Value The value to push. 7422 7438 */ 7423 staticVBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value)7439 IEM_STATIC VBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value) 7424 7440 { 7425 7441 /* Increment the stack pointer. */ … … 7452 7468 * @param u16Value The value to push. 7453 7469 */ 7454 staticVBOXSTRICTRC iemMemStackPushU32SReg(PIEMCPU pIemCpu, uint32_t u32Value)7470 IEM_STATIC VBOXSTRICTRC iemMemStackPushU32SReg(PIEMCPU pIemCpu, uint32_t u32Value) 7455 7471 { 7456 7472 /* Increment the stack pointer. */ … … 7504 7520 * @param u64Value The value to push. 7505 7521 */ 7506 staticVBOXSTRICTRC iemMemStackPushU64(PIEMCPU pIemCpu, uint64_t u64Value)7522 IEM_STATIC VBOXSTRICTRC iemMemStackPushU64(PIEMCPU pIemCpu, uint64_t u64Value) 7507 7523 { 7508 7524 /* Increment the stack pointer. */ … … 7535 7551 * @param pu16Value Where to store the popped value. 7536 7552 */ 7537 staticVBOXSTRICTRC iemMemStackPopU16(PIEMCPU pIemCpu, uint16_t *pu16Value)7553 IEM_STATIC VBOXSTRICTRC iemMemStackPopU16(PIEMCPU pIemCpu, uint16_t *pu16Value) 7538 7554 { 7539 7555 /* Increment the stack pointer. */ … … 7566 7582 * @param pu32Value Where to store the popped value. 7567 7583 */ 7568 staticVBOXSTRICTRC iemMemStackPopU32(PIEMCPU pIemCpu, uint32_t *pu32Value)7584 IEM_STATIC VBOXSTRICTRC iemMemStackPopU32(PIEMCPU pIemCpu, uint32_t *pu32Value) 7569 7585 { 7570 7586 /* Increment the stack pointer. */ … … 7597 7613 * @param pu64Value Where to store the popped value. 7598 7614 */ 7599 staticVBOXSTRICTRC iemMemStackPopU64(PIEMCPU pIemCpu, uint64_t *pu64Value)7615 IEM_STATIC VBOXSTRICTRC iemMemStackPopU64(PIEMCPU pIemCpu, uint64_t *pu64Value) 7600 7616 { 7601 7617 /* Increment the stack pointer. */ … … 7629 7645 * @param pTmpRsp Pointer to the temporary stack pointer. 7630 7646 */ 7631 staticVBOXSTRICTRC iemMemStackPushU16Ex(PIEMCPU pIemCpu, uint16_t u16Value, PRTUINT64U pTmpRsp)7647 IEM_STATIC VBOXSTRICTRC iemMemStackPushU16Ex(PIEMCPU pIemCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) 7632 7648 { 7633 7649 /* Increment the stack pointer. */ … … 7661 7677 * @param pTmpRsp Pointer to the temporary stack pointer. 7662 7678 */ 7663 staticVBOXSTRICTRC iemMemStackPushU32Ex(PIEMCPU pIemCpu, uint32_t u32Value, PRTUINT64U pTmpRsp)7679 IEM_STATIC VBOXSTRICTRC iemMemStackPushU32Ex(PIEMCPU pIemCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) 7664 7680 { 7665 7681 /* Increment the stack pointer. */ … … 7693 7709 * @param pTmpRsp Pointer to the temporary stack pointer. 7694 7710 */ 7695 staticVBOXSTRICTRC iemMemStackPushU64Ex(PIEMCPU pIemCpu, uint64_t u64Value, PRTUINT64U pTmpRsp)7711 IEM_STATIC VBOXSTRICTRC iemMemStackPushU64Ex(PIEMCPU pIemCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) 7696 7712 { 7697 7713 /* Increment the stack pointer. */ … … 7725 7741 * @param pTmpRsp Pointer to the temporary stack pointer. 7726 7742 */ 7727 staticVBOXSTRICTRC iemMemStackPopU16Ex(PIEMCPU pIemCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp)7743 IEM_STATIC VBOXSTRICTRC iemMemStackPopU16Ex(PIEMCPU pIemCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) 7728 7744 { 7729 7745 /* Increment the stack pointer. */ … … 7757 7773 * @param pTmpRsp Pointer to the temporary stack pointer. 7758 7774 */ 7759 staticVBOXSTRICTRC iemMemStackPopU32Ex(PIEMCPU pIemCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp)7775 IEM_STATIC VBOXSTRICTRC iemMemStackPopU32Ex(PIEMCPU pIemCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) 7760 7776 { 7761 7777 /* Increment the stack pointer. */ … … 7789 7805 * @param pTmpRsp Pointer to the temporary stack pointer. 7790 7806 */ 7791 staticVBOXSTRICTRC iemMemStackPopU64Ex(PIEMCPU pIemCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp)7807 IEM_STATIC VBOXSTRICTRC iemMemStackPopU64Ex(PIEMCPU pIemCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) 7792 7808 { 7793 7809 /* Increment the stack pointer. */ … … 7830 7846 * iemMemStackPushCommitSpecial(). 7831 7847 */ 7832 staticVBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void **ppvMem, uint64_t *puNewRsp)7848 IEM_STATIC VBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void **ppvMem, uint64_t *puNewRsp) 7833 7849 { 7834 7850 Assert(cbMem < UINT8_MAX); … … 7851 7867 * iemMemStackPushBeginSpecial(). 7852 7868 */ 7853 staticVBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp)7869 IEM_STATIC VBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp) 7854 7870 { 7855 7871 VBOXSTRICTRC rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem, IEM_ACCESS_STACK_W); … … 7874 7890 * manually if iemMemStackPopDoneSpecial() is used. 7875 7891 */ 7876 staticVBOXSTRICTRC iemMemStackPopBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void const **ppvMem, uint64_t *puNewRsp)7892 IEM_STATIC VBOXSTRICTRC iemMemStackPopBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void const **ppvMem, uint64_t *puNewRsp) 7877 7893 { 7878 7894 Assert(cbMem < UINT8_MAX); … … 7897 7913 * manually if iemMemStackPopDoneSpecial() is used. 7898 7914 */ 7899 staticVBOXSTRICTRC iemMemStackPopContinueSpecial(PIEMCPU pIemCpu, size_t cbMem, void const **ppvMem, uint64_t *puNewRsp)7915 IEM_STATIC VBOXSTRICTRC iemMemStackPopContinueSpecial(PIEMCPU pIemCpu, size_t cbMem, void const **ppvMem, uint64_t *puNewRsp) 7900 7916 { 7901 7917 Assert(cbMem < UINT8_MAX); … … 7921 7937 * iemMemStackPopBeginSpecial(). 7922 7938 */ 7923 staticVBOXSTRICTRC iemMemStackPopCommitSpecial(PIEMCPU pIemCpu, void const *pvMem, uint64_t uNewRsp)7939 IEM_STATIC VBOXSTRICTRC iemMemStackPopCommitSpecial(PIEMCPU pIemCpu, void const *pvMem, uint64_t uNewRsp) 7924 7940 { 7925 7941 VBOXSTRICTRC rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pvMem, IEM_ACCESS_STACK_R); … … 7942 7958 * iemMemStackPopContinueSpecial(). 7943 7959 */ 7944 staticVBOXSTRICTRC iemMemStackPopDoneSpecial(PIEMCPU pIemCpu, void const *pvMem)7960 IEM_STATIC VBOXSTRICTRC iemMemStackPopDoneSpecial(PIEMCPU pIemCpu, void const *pvMem) 7945 7961 { 7946 7962 return iemMemCommitAndUnmap(pIemCpu, (void *)pvMem, IEM_ACCESS_STACK_R); … … 7958 7974 * @param GCPtrMem The address of the guest memory. 7959 7975 */ 7960 staticVBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint8_t *pbDst, uint8_t iSegReg, RTGCPTR GCPtrMem)7976 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint8_t *pbDst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7961 7977 { 7962 7978 /* The lazy approach for now... */ … … 7982 7998 * @param GCPtrMem The address of the guest memory. 7983 7999 */ 7984 staticVBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)8000 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 7985 8001 { 7986 8002 /* The lazy approach for now... */ … … 8006 8022 * @param GCPtrMem The address of the guest memory. 8007 8023 */ 8008 staticVBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)8024 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 8009 8025 { 8010 8026 /* The lazy approach for now... */ … … 8030 8046 * @param GCPtrMem The address of the guest memory. 8031 8047 */ 8032 staticVBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)8048 IEM_STATIC VBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) 8033 8049 { 8034 8050 /* The lazy approach for now... */ … … 8054 8070 * @param uErrorCode The error code associated with the exception. 8055 8071 */ 8056 static VBOXSTRICTRC iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt, 8057 8072 IEM_STATIC VBOXSTRICTRC 8073 iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt, uint16_t uErrorCode) 8058 8074 { 8059 8075 AssertPtr(pDesc); … … 8122 8138 * @param uXcpt The exception to raise on table lookup error. 8123 8139 */ 8124 staticVBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt)8140 IEM_STATIC VBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) 8125 8141 { 8126 8142 return iemMemFetchSelDescWithErr(pIemCpu, pDesc, uSel, uXcpt, uSel & X86_SEL_MASK_OFF_RPL); … … 8134 8150 * @param uDpl The DPL we want. 8135 8151 */ 8136 staticvoid iemMemFakeStackSelDesc(PIEMSELDESC pDescSs, uint32_t uDpl)8152 IEM_STATIC void iemMemFakeStackSelDesc(PIEMSELDESC pDescSs, uint32_t uDpl) 8137 8153 { 8138 8154 pDescSs->Long.au64[0] = 0; … … 8156 8172 * @param uSel The selector. 8157 8173 */ 8158 staticVBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel)8174 IEM_STATIC VBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel) 8159 8175 { 8160 8176 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 9244 9260 * @param pGCPtrEff Where to return the effective address. 9245 9261 */ 9246 staticVBOXSTRICTRC iemOpHlpCalcRmEffAddr(PIEMCPU pIemCpu, uint8_t bRm, uint8_t cbImm, PRTGCPTR pGCPtrEff)9262 IEM_STATIC VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PIEMCPU pIemCpu, uint8_t bRm, uint8_t cbImm, PRTGCPTR pGCPtrEff) 9247 9263 { 9248 9264 Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm)); … … 9548 9564 * Sets up execution verification mode. 9549 9565 */ 9550 staticvoid iemExecVerificationModeSetup(PIEMCPU pIemCpu)9566 IEM_STATIC void iemExecVerificationModeSetup(PIEMCPU pIemCpu) 9551 9567 { 9552 9568 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); … … 9725 9741 * @returns Pointer to a record. 9726 9742 */ 9727 staticPIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu)9743 IEM_STATIC PIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu) 9728 9744 { 9729 9745 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) … … 9853 9869 * @param cbValue The size of the access. 9854 9870 */ 9855 staticVBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)9871 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue) 9856 9872 { 9857 9873 PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu); … … 9879 9895 * @param cbValue The size of the access. 9880 9896 */ 9881 staticVBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue)9897 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue) 9882 9898 { 9883 9899 PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu); … … 9900 9916 * @param pIemCpu The IEM per CPU state. 9901 9917 */ 9902 staticvoid iemVerifyAssertMsg2(PIEMCPU pIemCpu)9918 IEM_STATIC void iemVerifyAssertMsg2(PIEMCPU pIemCpu) 9903 9919 { 9904 9920 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); … … 9952 9968 * @param pEvtRec The record to dump. 9953 9969 */ 9954 staticvoid iemVerifyAssertAddRecordDump(PIEMVERIFYEVTREC pEvtRec)9970 IEM_STATIC void iemVerifyAssertAddRecordDump(PIEMVERIFYEVTREC pEvtRec) 9955 9971 { 9956 9972 switch (pEvtRec->enmEvent) … … 9995 10011 * @param pszMsg The message explaining why we're asserting. 9996 10012 */ 9997 staticvoid iemVerifyAssertRecords(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec1, PIEMVERIFYEVTREC pEvtRec2, const char *pszMsg)10013 IEM_STATIC void iemVerifyAssertRecords(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec1, PIEMVERIFYEVTREC pEvtRec2, const char *pszMsg) 9998 10014 { 9999 10015 RTAssertMsg1(pszMsg, __LINE__, __FILE__, __PRETTY_FUNCTION__); … … 10013 10029 * @param pszMsg The message explaining why we're asserting. 10014 10030 */ 10015 staticvoid iemVerifyAssertRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, const char *pszMsg)10031 IEM_STATIC void iemVerifyAssertRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, const char *pszMsg) 10016 10032 { 10017 10033 RTAssertMsg1(pszMsg, __LINE__, __FILE__, __PRETTY_FUNCTION__); … … 10030 10046 * it was HM. 10031 10047 */ 10032 staticvoid iemVerifyWriteRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, bool fRem)10048 IEM_STATIC void iemVerifyWriteRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, bool fRem) 10033 10049 { 10034 10050 uint8_t abBuf[sizeof(pEvtRec->u.RamWrite.ab)]; RT_ZERO(abBuf); … … 10072 10088 * Performs the post-execution verfication checks. 10073 10089 */ 10074 staticvoid iemExecVerificationModeCheck(PIEMCPU pIemCpu)10090 IEM_STATIC void iemExecVerificationModeCheck(PIEMCPU pIemCpu) 10075 10091 { 10076 10092 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) … … 10446 10462 10447 10463 /* stubs */ 10448 staticVBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)10464 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue) 10449 10465 { 10450 10466 NOREF(pIemCpu); NOREF(Port); NOREF(pu32Value); NOREF(cbValue); … … 10452 10468 } 10453 10469 10454 staticVBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue)10470 IEM_STATIC VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue) 10455 10471 { 10456 10472 NOREF(pIemCpu); NOREF(Port); NOREF(u32Value); NOREF(cbValue); … … 10471 10487 * valid CPU mode info. 10472 10488 */ 10473 staticvoid iemLogCurInstr(PVMCPU pVCpu, PCPUMCTX pCtx, bool fSameCtx)10489 IEM_STATIC void iemLogCurInstr(PVMCPU pVCpu, PCPUMCTX pCtx, bool fSameCtx) 10474 10490 { 10475 10491 # ifdef IN_RING3 -
trunk/src/VBox/VMM/include/IEMInternal.h
r55229 r56021 33 33 * @{ 34 34 */ 35 36 /** For expanding symbol in slickedit and other products tagging and 37 * crossreferencing IEM symbols. */ 38 #ifndef IEM_STATIC 39 # define IEM_STATIC static 40 #endif 35 41 36 42 /** @def IEM_VERIFICATION_MODE_FULL
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