Changeset 56364 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jun 11, 2015 2:52:57 PM (9 years ago)

Author:

vboxsync

Message:

VMM/HM: g_HvmR0 -> g_HmR0.

File:

• trunk/src/VBox/VMM/VMMR0/HMR0.cpp (modified) (66 diffs)

trunk/src/VBox/VMM/VMMR0/HMR0.cpp

@@ -165 +165 @@
     /** Serialize initialization in HMR0EnableAllCpus. */
     RTONCE                          EnableAllCpusOnce;
-} g_HvmR0;
+} g_HmR0;
 
 
@@ -344 +344 @@
     {
         /** @todo move this into a separate function. */
-        g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
+        g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
 
         /*
@@ -350 +350 @@
          * (This is only supported by some Mac OS X kernels atm.)
          */
-        int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
-        g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
-        if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+        int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
+        g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
+        if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
         {
             AssertLogRelMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
             if (RT_SUCCESS(rc))
             {
-                g_HvmR0.vmx.fSupported = true;
+                g_HmR0.vmx.fSupported = true;
                 rc = SUPR0EnableVTx(false /* fEnable */);
                 AssertLogRelRC(rc);
@@ -368 +368 @@
             HMR0FIRSTRC FirstRc;
             hmR0FirstRcInit(&FirstRc);
-            g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
-            if (RT_SUCCESS(g_HvmR0.lLastError))
-                g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
+            g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
+            if (RT_SUCCESS(g_HmR0.lLastError))
+                g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
         }
-        if (RT_SUCCESS(g_HvmR0.lLastError))
+        if (RT_SUCCESS(g_HmR0.lLastError))
         {
             /* Reread in case it was changed by hmR0InitIntelCpu(). */
-            g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
+            g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
 
             /*
              * Read all relevant registers and MSRs.
              */
-            g_HvmR0.vmx.u64HostCr4          = ASMGetCR4();
-            g_HvmR0.vmx.u64HostEfer         = ASMRdMsr(MSR_K6_EFER);
-            g_HvmR0.vmx.Msrs.u64BasicInfo   = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
-            g_HvmR0.vmx.Msrs.VmxPinCtls.u   = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
-            g_HvmR0.vmx.Msrs.VmxProcCtls.u  = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
-            g_HvmR0.vmx.Msrs.VmxExit.u      = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
-            g_HvmR0.vmx.Msrs.VmxEntry.u     = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
-            g_HvmR0.vmx.Msrs.u64Misc        = ASMRdMsr(MSR_IA32_VMX_MISC);
-            g_HvmR0.vmx.Msrs.u64Cr0Fixed0   = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
-            g_HvmR0.vmx.Msrs.u64Cr0Fixed1   = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
-            g_HvmR0.vmx.Msrs.u64Cr4Fixed0   = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
-            g_HvmR0.vmx.Msrs.u64Cr4Fixed1   = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
-            g_HvmR0.vmx.Msrs.u64VmcsEnum    = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
+            g_HmR0.vmx.u64HostCr4          = ASMGetCR4();
+            g_HmR0.vmx.u64HostEfer         = ASMRdMsr(MSR_K6_EFER);
+            g_HmR0.vmx.Msrs.u64BasicInfo   = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
+            g_HmR0.vmx.Msrs.VmxPinCtls.u   = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
+            g_HmR0.vmx.Msrs.VmxProcCtls.u  = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
+            g_HmR0.vmx.Msrs.VmxExit.u      = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
+            g_HmR0.vmx.Msrs.VmxEntry.u     = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
+            g_HmR0.vmx.Msrs.u64Misc        = ASMRdMsr(MSR_IA32_VMX_MISC);
+            g_HmR0.vmx.Msrs.u64Cr0Fixed0   = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
+            g_HmR0.vmx.Msrs.u64Cr0Fixed1   = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
+            g_HmR0.vmx.Msrs.u64Cr4Fixed0   = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
+            g_HmR0.vmx.Msrs.u64Cr4Fixed1   = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
+            g_HmR0.vmx.Msrs.u64VmcsEnum    = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
             /* VPID 16 bits ASID. */
-            g_HvmR0.uMaxAsid                = 0x10000; /* exclusive */
-
-            if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+            g_HmR0.uMaxAsid                = 0x10000; /* exclusive */
+
+            if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
             {
-                g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
-                if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID))
-                    g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
-
-                if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
-                    g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
+                g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
+                if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID))
+                    g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
+
+                if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
+                    g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
             }
 
-            if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+            if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
             {
                 /*
@@ -424 +424 @@
 
                 /* Set revision dword at the beginning of the structure. */
-                *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
+                *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
 
                 /* Make sure we don't get rescheduled to another cpu during this probe. */
@@ -432 +432 @@
                  * Check CR4.VMXE
                  */
-                g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
-                if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
+                g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
+                if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
                 {
                     /* In theory this bit could be cleared behind our back.  Which would cause
                        #UD faults when we try to execute the VMX instructions... */
-                    ASMSetCR4(g_HvmR0.vmx.u64HostCr4 | X86_CR4_VMXE);
+                    ASMSetCR4(g_HmR0.vmx.u64HostCr4 | X86_CR4_VMXE);
                 }
 
@@ -448 +448 @@
                 if (RT_SUCCESS(rc))
                 {
-                    g_HvmR0.vmx.fSupported = true;
+                    g_HmR0.vmx.fSupported = true;
                     VMXDisable();
                 }
@@ -464 +464 @@
                      * They should fix their code, but until they do we simply refuse to run.
                      */
-                    g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
-                    Assert(g_HvmR0.vmx.fSupported == false);
+                    g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
+                    Assert(g_HmR0.vmx.fSupported == false);
                 }
 
@@ -471 +471 @@
                    if it wasn't so before (some software could incorrectly
                    think it's in VMX mode). */
-                ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
+                ASMSetCR4(g_HmR0.vmx.u64HostCr4);
                 ASMSetFlags(fFlags);
 
@@ -477 +477 @@
             }
 
-            if (g_HvmR0.vmx.fSupported)
+            if (g_HmR0.vmx.fSupported)
             {
                 rc = VMXR0GlobalInit();
                 if (RT_FAILURE(rc))
-                    g_HvmR0.lLastError = rc;
+                    g_HmR0.lLastError = rc;
 
                 /*
                  * Install the VT-x methods.
                  */
-                g_HvmR0.pfnEnterSession      = VMXR0Enter;
-                g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
-                g_HvmR0.pfnSaveHostState     = VMXR0SaveHostState;
-                g_HvmR0.pfnRunGuestCode      = VMXR0RunGuestCode;
-                g_HvmR0.pfnEnableCpu         = VMXR0EnableCpu;
-                g_HvmR0.pfnDisableCpu        = VMXR0DisableCpu;
-                g_HvmR0.pfnInitVM            = VMXR0InitVM;
-                g_HvmR0.pfnTermVM            = VMXR0TermVM;
-                g_HvmR0.pfnSetupVM           = VMXR0SetupVM;
+                g_HmR0.pfnEnterSession      = VMXR0Enter;
+                g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
+                g_HmR0.pfnSaveHostState     = VMXR0SaveHostState;
+                g_HmR0.pfnRunGuestCode      = VMXR0RunGuestCode;
+                g_HmR0.pfnEnableCpu         = VMXR0EnableCpu;
+                g_HmR0.pfnDisableCpu        = VMXR0DisableCpu;
+                g_HmR0.pfnInitVM            = VMXR0InitVM;
+                g_HmR0.pfnTermVM            = VMXR0TermVM;
+                g_HmR0.pfnSetupVM           = VMXR0SetupVM;
 
                 /*
@@ -500 +500 @@
                  * Timer Does Not Count Down at the Rate Specified" erratum.
                  */
-                if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
+                if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
                 {
-                    g_HvmR0.vmx.fUsePreemptTimer   = true;
-                    g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
+                    g_HmR0.vmx.fUsePreemptTimer   = true;
+                    g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
                     if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
-                        g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
+                        g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
                 }
             }
@@ -511 +511 @@
 #ifdef LOG_ENABLED
         else
-            SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
+            SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
 #endif
     }
     else
-        g_HvmR0.lLastError = VERR_VMX_NO_VMX;
+        g_HmR0.lLastError = VERR_VMX_NO_VMX;
     return VINF_SUCCESS;
 }
@@ -532 +532 @@
      */
     int rc;
-    if (   (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
+    if (   (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
         && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
         && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
@@ -543 +543 @@
         if (RT_FAILURE(rc))
         {
-            g_HvmR0.lLastError = rc;
+            g_HmR0.lLastError = rc;
             return rc;
         }
@@ -550 +550 @@
          * Install the AMD-V methods.
          */
-        g_HvmR0.pfnEnterSession      = SVMR0Enter;
-        g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
-        g_HvmR0.pfnSaveHostState     = SVMR0SaveHostState;
-        g_HvmR0.pfnRunGuestCode      = SVMR0RunGuestCode;
-        g_HvmR0.pfnEnableCpu         = SVMR0EnableCpu;
-        g_HvmR0.pfnDisableCpu        = SVMR0DisableCpu;
-        g_HvmR0.pfnInitVM            = SVMR0InitVM;
-        g_HvmR0.pfnTermVM            = SVMR0TermVM;
-        g_HvmR0.pfnSetupVM           = SVMR0SetupVM;
+        g_HmR0.pfnEnterSession      = SVMR0Enter;
+        g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
+        g_HmR0.pfnSaveHostState     = SVMR0SaveHostState;
+        g_HmR0.pfnRunGuestCode      = SVMR0RunGuestCode;
+        g_HmR0.pfnEnableCpu         = SVMR0EnableCpu;
+        g_HmR0.pfnDisableCpu        = SVMR0DisableCpu;
+        g_HmR0.pfnInitVM            = SVMR0InitVM;
+        g_HmR0.pfnTermVM            = SVMR0TermVM;
+        g_HmR0.pfnSetupVM           = SVMR0SetupVM;
 
         /* Query AMD features. */
         uint32_t u32Dummy;
-        ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
+        ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
 
         /*
@@ -581 +581 @@
         {
             /* Read the HWCR MSR for diagnostics. */
-            g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
-            g_HvmR0.svm.fSupported = true;
+            g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
+            g_HmR0.svm.fSupported = true;
         }
         else
         {
-            g_HvmR0.lLastError = rc;
+            g_HmR0.lLastError = rc;
             if (rc == VERR_SVM_DISABLED || rc == VERR_SVM_IN_USE)
                 rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
@@ -594 +594 @@
     {
         rc = VINF_SUCCESS;              /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
-        g_HvmR0.lLastError = VERR_SVM_NO_SVM;
+        g_HmR0.lLastError = VERR_SVM_NO_SVM;
     }
     return rc;
@@ -610 +610 @@
      * Initialize the globals.
      */
-    g_HvmR0.fEnabled = false;
+    g_HmR0.fEnabled = false;
     static RTONCE s_OnceInit = RTONCE_INITIALIZER;
-    g_HvmR0.EnableAllCpusOnce = s_OnceInit;
-    for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
-    {
-        g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
-        g_HvmR0.aCpuInfo[i].idCpu   = NIL_RTCPUID;
+    g_HmR0.EnableAllCpusOnce = s_OnceInit;
+    for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
+    {
+        g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
+        g_HmR0.aCpuInfo[i].idCpu   = NIL_RTCPUID;
     }
 
     /* Fill in all callbacks with placeholders. */
-    g_HvmR0.pfnEnterSession      = hmR0DummyEnter;
-    g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
-    g_HvmR0.pfnSaveHostState     = hmR0DummySaveHostState;
-    g_HvmR0.pfnRunGuestCode      = hmR0DummyRunGuestCode;
-    g_HvmR0.pfnEnableCpu         = hmR0DummyEnableCpu;
-    g_HvmR0.pfnDisableCpu        = hmR0DummyDisableCpu;
-    g_HvmR0.pfnInitVM            = hmR0DummyInitVM;
-    g_HvmR0.pfnTermVM            = hmR0DummyTermVM;
-    g_HvmR0.pfnSetupVM           = hmR0DummySetupVM;
+    g_HmR0.pfnEnterSession      = hmR0DummyEnter;
+    g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
+    g_HmR0.pfnSaveHostState     = hmR0DummySaveHostState;
+    g_HmR0.pfnRunGuestCode      = hmR0DummyRunGuestCode;
+    g_HmR0.pfnEnableCpu         = hmR0DummyEnableCpu;
+    g_HmR0.pfnDisableCpu        = hmR0DummyDisableCpu;
+    g_HmR0.pfnInitVM            = hmR0DummyInitVM;
+    g_HmR0.pfnTermVM            = hmR0DummyTermVM;
+    g_HmR0.pfnSetupVM           = hmR0DummySetupVM;
 
     /* Default is global VT-x/AMD-V init. */
-    g_HvmR0.fGlobalInit         = true;
+    g_HmR0.fGlobalInit         = true;
 
     /*
      * Make sure aCpuInfo is big enough for all the CPUs on this system.
      */
-    if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
-    {
-        LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
+    if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
+    {
+        LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
         return VERR_TOO_MANY_CPUS;
     }
@@ -660 +660 @@
             if (ASMIsValidExtRange(uMaxExtLeaf))
                 ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
-                         &g_HvmR0.cpuid.u32AMDFeatureECX,
-                         &g_HvmR0.cpuid.u32AMDFeatureEDX);
+                         &g_HmR0.cpuid.u32AMDFeatureECX,
+                         &g_HmR0.cpuid.u32AMDFeatureEDX);
             else
-                g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
+                g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
 
             /* Go to CPU specific initialization code. */
@@ -680 +680 @@
             }
             else
-                g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
+                g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
         }
         else
-            g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
+            g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
     }
     else
-        g_HvmR0.lLastError = VERR_HM_NO_CPUID;
+        g_HmR0.lLastError = VERR_HM_NO_CPUID;
 
     /*
@@ -692 +692 @@
      * when brought offline/online or suspending/resuming.
      */
-    if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+    if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
     {
         rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
@@ -715 +715 @@
 {
     int rc;
-    if (   g_HvmR0.vmx.fSupported
-        && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+    if (   g_HmR0.vmx.fSupported
+        && g_HmR0.vmx.fUsingSUPR0EnableVTx)
     {
         /*
          * Simple if the host OS manages VT-x.
          */
-        Assert(g_HvmR0.fGlobalInit);
+        Assert(g_HmR0.fGlobalInit);
         rc = SUPR0EnableVTx(false /* fEnable */);
 
-        for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
+        for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
         {
-            g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
-            Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
+            g_HmR0.aCpuInfo[iCpu].fConfigured = false;
+            Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
         }
     }
     else
     {
-        Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+        Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
 
         /* Doesn't really matter if this fails. */
@@ -741 +741 @@
          * Disable VT-x/AMD-V on all CPUs if we enabled it before.
          */
-        if (g_HvmR0.fGlobalInit)
+        if (g_HmR0.fGlobalInit)
         {
             HMR0FIRSTRC FirstRc;
@@ -754 +754 @@
          * Free the per-cpu pages used for VT-x and AMD-V.
          */
-        for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
+        for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
         {
-            if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
+            if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
             {
-                RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
-                g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
+                RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
+                g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
             }
         }
@@ -768 +768 @@
      *        should move into their respective modules. */
     /* Finally, call global VT-x/AMD-V termination. */
-    if (g_HvmR0.vmx.fSupported)
+    if (g_HmR0.vmx.fSupported)
         VMXR0GlobalTerm();
-    else if (g_HvmR0.svm.fSupported)
+    else if (g_HmR0.svm.fSupported)
         SVMR0GlobalTerm();
 
@@ -828 +828 @@
 static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
 {
-    PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
+    PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
 
     Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
-    Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
+    Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
     Assert(!pCpu->fConfigured);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -839 +839 @@
 
     int rc;
-    if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
-        rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
+    if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
+        rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
     else
     {
@@ -847 +847 @@
         RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
 
-        if (g_HvmR0.vmx.fSupported)
-            rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
+        if (g_HmR0.vmx.fSupported)
+            rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
         else
-            rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
+            rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
     }
     if (RT_SUCCESS(rc))
@@ -870 +870 @@
     PVM             pVM      = (PVM)pvUser1;     /* can be NULL! */
     PHMR0FIRSTRC    pFirstRc = (PHMR0FIRSTRC)pvUser2;
-    AssertReturnVoid(g_HvmR0.fGlobalInit);
+    AssertReturnVoid(g_HmR0.fGlobalInit);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
     hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
@@ -893 +893 @@
      *       notification.  Kind of unlikely though, so ignored for now.
      */
-    AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
-    ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
+    AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
+    ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
 
     /*
      * The global init variable is set by the first VM.
      */
-    g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
+    g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
 
 #ifdef VBOX_STRICT
-    for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
-    {
-        Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
-        Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
-        Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
-        Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
+    for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
+    {
+        Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
+        Assert(!g_HmR0.aCpuInfo[i].fConfigured);
+        Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
+        Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
     }
 #endif
 
     int rc;
-    if (   g_HvmR0.vmx.fSupported
-        && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+    if (   g_HmR0.vmx.fSupported
+        && g_HmR0.vmx.fUsingSUPR0EnableVTx)
     {
         /*
@@ -922 +922 @@
         {
             /* If the host provides a VT-x init API, then we'll rely on that for global init. */
-            g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
+            g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
         }
         else
@@ -933 +933 @@
          */
         /* Allocate one page per cpu for the global VT-x and AMD-V pages */
-        for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
+        for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
         {
-            Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
+            Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
 
             if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
             {
-                rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
+                rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
                 AssertLogRelRCReturn(rc, rc);
 
-                void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
+                void *pvR0 = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
                 ASMMemZeroPage(pvR0);
             }
@@ -951 +951 @@
 
     if (   RT_SUCCESS(rc)
-        && g_HvmR0.fGlobalInit)
+        && g_HmR0.fGlobalInit)
     {
         /* First time, so initialize each cpu/core. */
@@ -974 +974 @@
 {
     /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
-    if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
+    if (ASMAtomicReadBool(&g_HmR0.fSuspended))
         return VERR_HM_SUSPEND_PENDING;
 
-    return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
+    return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
 }
 
@@ -991 +991 @@
 static int hmR0DisableCpu(RTCPUID idCpu)
 {
-    PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
-
-    Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+    PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
+
+    Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
     Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
-    Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
+    Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
     Assert(!pCpu->fConfigured || pCpu->hMemObj != NIL_RTR0MEMOBJ);
     AssertRelease(idCpu == RTMpCpuId());
@@ -1009 +1009 @@
         RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
 
-        rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
+        rc = g_HmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
         AssertRCReturn(rc, rc);
 
@@ -1032 +1032 @@
 {
     PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
-    AssertReturnVoid(g_HvmR0.fGlobalInit);
+    AssertReturnVoid(g_HmR0.fGlobalInit);
     hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
 }
@@ -1063 +1063 @@
 {
     NOREF(pvData);
-    Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+    Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
 
     /*
@@ -1104 +1104 @@
 {
     NOREF(pvUser);
-    Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+    Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
 
 #ifdef LOG_ENABLED
@@ -1114 +1114 @@
 
     if (enmEvent == RTPOWEREVENT_SUSPEND)
-        ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
-
-    if (g_HvmR0.fEnabled)
+        ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
+
+    if (g_HmR0.fEnabled)
     {
         int         rc;
@@ -1124 +1124 @@
         if (enmEvent == RTPOWEREVENT_SUSPEND)
         {
-            if (g_HvmR0.fGlobalInit)
+            if (g_HmR0.fGlobalInit)
             {
                 /* Turn off VT-x or AMD-V on all CPUs. */
@@ -1136 +1136 @@
             /* Reinit the CPUs from scratch as the suspend state might have
                messed with the MSRs. (lousy BIOSes as usual) */
-            if (g_HvmR0.vmx.fSupported)
+            if (g_HmR0.vmx.fSupported)
                 rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
             else
@@ -1147 +1147 @@
                 SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
 #endif
-            if (g_HvmR0.fGlobalInit)
+            if (g_HmR0.fGlobalInit)
             {
                 /* Turn VT-x or AMD-V back on on all CPUs. */
@@ -1158 +1158 @@
 
     if (enmEvent == RTPOWEREVENT_RESUME)
-        ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
+        ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
 }
 
@@ -1183 +1183 @@
 
     /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
-    if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
+    if (ASMAtomicReadBool(&g_HmR0.fSuspended))
         return VERR_HM_SUSPEND_PENDING;
 
@@ -1189 +1189 @@
      * Copy globals to the VM structure.
      */
-    pVM->hm.s.vmx.fSupported            = g_HvmR0.vmx.fSupported;
-    pVM->hm.s.svm.fSupported            = g_HvmR0.svm.fSupported;
-
-    pVM->hm.s.vmx.fUsePreemptTimer     &= g_HvmR0.vmx.fUsePreemptTimer;     /* Can be overridden by CFGM. See HMR3Init(). */
-    pVM->hm.s.vmx.cPreemptTimerShift    = g_HvmR0.vmx.cPreemptTimerShift;
-    pVM->hm.s.vmx.u64HostCr4            = g_HvmR0.vmx.u64HostCr4;
-    pVM->hm.s.vmx.u64HostEfer           = g_HvmR0.vmx.u64HostEfer;
-    pVM->hm.s.vmx.Msrs                  = g_HvmR0.vmx.Msrs;
-    pVM->hm.s.svm.u64MsrHwcr            = g_HvmR0.svm.u64MsrHwcr;
-    pVM->hm.s.svm.u32Rev                = g_HvmR0.svm.u32Rev;
-    pVM->hm.s.svm.u32Features           = g_HvmR0.svm.u32Features;
-    pVM->hm.s.cpuid.u32AMDFeatureECX    = g_HvmR0.cpuid.u32AMDFeatureECX;
-    pVM->hm.s.cpuid.u32AMDFeatureEDX    = g_HvmR0.cpuid.u32AMDFeatureEDX;
-    pVM->hm.s.lLastError                = g_HvmR0.lLastError;
-    pVM->hm.s.uMaxAsid                  = g_HvmR0.uMaxAsid;
+    pVM->hm.s.vmx.fSupported            = g_HmR0.vmx.fSupported;
+    pVM->hm.s.svm.fSupported            = g_HmR0.svm.fSupported;
+
+    pVM->hm.s.vmx.fUsePreemptTimer     &= g_HmR0.vmx.fUsePreemptTimer;     /* Can be overridden by CFGM. See HMR3Init(). */
+    pVM->hm.s.vmx.cPreemptTimerShift    = g_HmR0.vmx.cPreemptTimerShift;
+    pVM->hm.s.vmx.u64HostCr4            = g_HmR0.vmx.u64HostCr4;
+    pVM->hm.s.vmx.u64HostEfer           = g_HmR0.vmx.u64HostEfer;
+    pVM->hm.s.vmx.Msrs                  = g_HmR0.vmx.Msrs;
+    pVM->hm.s.svm.u64MsrHwcr            = g_HmR0.svm.u64MsrHwcr;
+    pVM->hm.s.svm.u32Rev                = g_HmR0.svm.u32Rev;
+    pVM->hm.s.svm.u32Features           = g_HmR0.svm.u32Features;
+    pVM->hm.s.cpuid.u32AMDFeatureECX    = g_HmR0.cpuid.u32AMDFeatureECX;
+    pVM->hm.s.cpuid.u32AMDFeatureEDX    = g_HmR0.cpuid.u32AMDFeatureEDX;
+    pVM->hm.s.lLastError                = g_HmR0.lLastError;
+    pVM->hm.s.uMaxAsid                  = g_HmR0.uMaxAsid;
 
     if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
@@ -1231 +1231 @@
      * Call the hardware specific initialization method.
      */
-    return g_HvmR0.pfnInitVM(pVM);
+    return g_HmR0.pfnInitVM(pVM);
 }
 
@@ -1252 +1252 @@
      * mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
      */
-    return g_HvmR0.pfnTermVM(pVM);
+    return g_HmR0.pfnTermVM(pVM);
 }
 
@@ -1270 +1270 @@
 
     /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
-    AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
+    AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
 
     /* On first entry we'll sync everything. */
@@ -1286 +1286 @@
     /* Enable VT-x or AMD-V if local init is required. */
     int rc;
-    if (!g_HvmR0.fGlobalInit)
-    {
-        Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+    if (!g_HmR0.fGlobalInit)
+    {
+        Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
         rc = hmR0EnableCpu(pVM, idCpu);
         if (RT_FAILURE(rc))
@@ -1298 +1298 @@
 
     /* Setup VT-x or AMD-V. */
-    rc = g_HvmR0.pfnSetupVM(pVM);
+    rc = g_HmR0.pfnSetupVM(pVM);
 
     /* Disable VT-x or AMD-V if local init was done before. */
-    if (!g_HvmR0.fGlobalInit)
-    {
-        Assert(!g_HvmR0.vmx.fSupported || !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
+    if (!g_HmR0.fGlobalInit)
+    {
+        Assert(!g_HmR0.vmx.fSupported || !g_HmR0.vmx.fUsingSUPR0EnableVTx);
         int rc2 = hmR0DisableCpu(idCpu);
         AssertRC(rc2);
@@ -1328 +1328 @@
     int              rc    = VINF_SUCCESS;
     RTCPUID          idCpu = RTMpCpuId();
-    PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
+    PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
     AssertPtr(pCpu);
 
@@ -1356 +1356 @@
 {
     /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
-    AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
+    AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
 
@@ -1369 +1369 @@
 
     RTCPUID          idCpu = RTMpCpuId();
-    PHMGLOBALCPUINFO pCpu  = &g_HvmR0.aCpuInfo[idCpu];
+    PHMGLOBALCPUINFO pCpu  = &g_HmR0.aCpuInfo[idCpu];
     Assert(pCpu);
     Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
 
-    rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
+    rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
     AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
 
     /* Load the host-state as we may be resuming code after a longjmp and quite
        possibly now be scheduled on a different CPU. */
-    rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
+    rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
     AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
 
@@ -1408 +1408 @@
 
     RTCPUID          idCpu = RTMpCpuId();
-    PHMGLOBALCPUINFO pCpu  = &g_HvmR0.aCpuInfo[idCpu];
-
-    if (   !g_HvmR0.fGlobalInit
+    PHMGLOBALCPUINFO pCpu  = &g_HmR0.aCpuInfo[idCpu];
+
+    if (   !g_HmR0.fGlobalInit
         && pCpu->fConfigured)
     {
@@ -1439 +1439 @@
     PVMCPU pVCpu = (PVMCPU)pvUser;
     Assert(pVCpu);
-    Assert(g_HvmR0.pfnThreadCtxCallback);
-
-    g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
+    Assert(g_HmR0.pfnThreadCtxCallback);
+
+    g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
 }
 
@@ -1461 +1461 @@
     if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
     {
-        PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
+        PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
         Assert(pCpu->fConfigured);
-        AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
+        AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
     }
 #endif
@@ -1474 +1474 @@
 #endif
 
-    int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
+    int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
 
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
@@ -1550 +1550 @@
 VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
 {
-    return ASMAtomicReadBool(&g_HvmR0.fSuspended);
+    return ASMAtomicReadBool(&g_HmR0.fSuspended);
 }
 
@@ -1564 +1564 @@
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
     RTCPUID idCpu = RTMpCpuId();
-    Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
-    return &g_HvmR0.aCpuInfo[idCpu];
+    Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
+    return &g_HmR0.aCpuInfo[idCpu];
 }
 
@@ -1578 +1578 @@
 VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
 {
-    Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
-    return &g_HvmR0.aCpuInfo[idCpu];
+    Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
+    return &g_HmR0.aCpuInfo[idCpu];
 }
 
@@ -1646 +1646 @@
 
     /* No such issues with AMD-V */
-    if (!g_HvmR0.vmx.fSupported)
+    if (!g_HmR0.vmx.fSupported)
         return VINF_SUCCESS;
 
@@ -1668 +1668 @@
     /* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
        regardless of whether we're currently using VT-x or not. */
-    if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+    if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
     {
         *pfVTxDisabled = SUPR0SuspendVTxOnCpu();
@@ -1678 +1678 @@
 
     /* Nothing to do if we haven't enabled VT-x. */
-    if (!g_HvmR0.fEnabled)
+    if (!g_HmR0.fEnabled)
         return VINF_SUCCESS;
 
     /* Local init implies the CPU is currently not in VMX root mode. */
-    if (!g_HvmR0.fGlobalInit)
+    if (!g_HmR0.fGlobalInit)
         return VINF_SUCCESS;
 
@@ -1710 +1710 @@
         return;         /* nothing to do */
 
-    Assert(g_HvmR0.vmx.fSupported);
-    if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
+    Assert(g_HmR0.vmx.fSupported);
+    if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
         SUPR0ResumeVTxOnCpu(fVTxDisabled);
     else
     {
-        Assert(g_HvmR0.fEnabled);
-        Assert(g_HvmR0.fGlobalInit);
+        Assert(g_HmR0.fEnabled);
+        Assert(g_HmR0.fGlobalInit);
 
         PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
@@ -1723 +1723 @@
         void           *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
         RTHCPHYS        HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
-        VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
+        VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HmR0.vmx.Msrs);
     }
 }