Changeset 57218 in vbox for trunk/src/VBox/HostDrivers/Support/testcase

Timestamp:

Aug 6, 2015 2:53:27 PM (10 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

101971

Message:

SUPDrv, tstGIP-2: Add support for GIP flags and testing TSC frequency compatibility.

File:

• trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp (modified) (9 diffs)

trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp

@@ -41 +41 @@
 #include <iprt/x86.h>
 
-
-/**
- * Checks whether the CPU advertises an invariant TSC or not.
- *
- * @returns true if invariant, false otherwise.
- */
-bool tstIsInvariantTsc(void)
-{
-    if (ASMHasCpuId())
-    {
-        uint32_t uEax, uEbx, uEcx, uEdx;
-        ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx);
-        if (uEax >= 0x80000007)
-        {
-            ASMCpuId(0x80000007, &uEax, &uEbx, &uEcx, &uEdx);
-            if (uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
-                return true;
-        }
-    }
-    return false;
-}
-
-
 int main(int argc, char **argv)
 {
@@ -79 +56 @@
         { "--reference",        'r', RTGETOPT_REQ_UINT64 },  /* reference value of CpuHz, display the
                                                               * CpuHz deviation in a separate column. */
+        { "--notestmode",       't', RTGETOPT_REQ_NOTHING }  /* don't run GIP in test-mode (atm, test-mode
+                                                              * implies updating GIP CpuHz even when invariant) */
     };
 
@@ -85 +64 @@
     bool fSpin = false;
     bool fCompat = true;
+    bool fTestMode = true;
     int ch;
-    uint64_t uCpuHzRef = 0;
+    uint64_t uCpuHzRef = UINT64_MAX;
     uint64_t uCpuHzOverallDeviation = 0;
     uint32_t cCpuHzNotCompat = 0;
@@ -118 +98 @@
                 break;
 
+            case 't':
+                fTestMode = false;
+                break;
+
             default:
                 return RTGetOptPrintError(ch, &ValueUnion);
@@ -132 +116 @@
         if (g_pSUPGlobalInfoPage)
         {
+            /* Pick current CpuHz as the reference if none was specified. */
+            if (uCpuHzRef == UINT64_MAX)
+                uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
+
+            if (   fTestMode
+                && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
+                SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
+
             RTPrintf("tstGIP-2: cCpus=%d  u32UpdateHz=%RU32  u32UpdateIntervalNS=%RU32  u64NanoTSLastUpdateHz=%RX64  u64CpuHz=%RU64  uCpuHzRef=%RU64  u32Mode=%d (%s) u32Version=%#x\n",
                      g_pSUPGlobalInfoPage->cCpus,
@@ -147 +139 @@
                      uCpuHzRef ? "  CpuHz deviation  Compat  " : "");
             static SUPGIPCPU s_aaCPUs[2][256];
+
             for (uint32_t i = 0; i < cIterations; i++)
             {
@@ -170 +163 @@
                             {
                                 /* Wait until the history validation code takes effect. */
+                                bool fCurHzCompat = true;
                                 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
                                 {
@@ -176 +170 @@
                                     uCpuHzOverallDeviation += uCpuHzDeviation;
                                     cCpuHzOverallDevCnt++;
+                                    fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /* fRelax */);
                                 }
-                                bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /* fRelax */);
                                 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
                                 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%%  %RTbool   ",
@@ -271 +265 @@
                 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz)\n", fCompat,
                          cCpuHzNotCompat, cIterations * g_pSUPGlobalInfoPage->cCpus, uCpuHzRef);
+
+                if (   !fCompat
+                    && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
+                    rc = -1;
             }
+
+            /* Disable GIP test mode. */
+            if (fTestMode)
+                SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
         }
         else