Changeset 58106 in vbox for trunk/src/recompiler/VBoxRecompiler.c

Timestamp:

Oct 7, 2015 5:07:25 PM (9 years ago)

Author:

vboxsync

Message:

include,misc: Corrected a bunch of doxygen errors.

File:

• trunk/src/recompiler/VBoxRecompiler.c (modified) (5 diffs)

trunk/src/recompiler/VBoxRecompiler.c

@@ -3525 +3525 @@
  * @param   addr        The virtual address.
  * @param   pTLBEntry   The TLB entry.
+ * @param   IoTlbEntry  The I/O TLB entry address.
  */
 target_ulong remR3PhysGetPhysicalAddressCode(CPUX86State       *env,
                                              target_ulong       addr,
                                              CPUTLBEntry       *pTLBEntry,
-                                             target_phys_addr_t ioTLBEntry)
+                                             target_phys_addr_t IoTlbEntry)
 {
     PVM pVM = env->pVM;
 
-    if ((ioTLBEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
+    if ((IoTlbEntry & ~TARGET_PAGE_MASK) == pVM->rem.s.iHandlerMemType)
     {
         /* If code memory is being monitored, appropriate IOTLB entry will have
            handler IO type, and addend will provide real physical address, no
            matter if we store VA in TLB or not, as handlers are always passed PA */
-        target_ulong ret = (ioTLBEntry & TARGET_PAGE_MASK) + addr;
+        target_ulong ret = (IoTlbEntry & TARGET_PAGE_MASK) + addr;
         return ret;
     }
     LogRel(("\nTrying to execute code with memory type addr_code=%RGv addend=%RGp at %RGv! (iHandlerMemType=%#x iMMIOMemType=%#x IOTLB=%RGp)\n"
             "*** handlers\n",
-            (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)ioTLBEntry));
+            (RTGCPTR)pTLBEntry->addr_code, (RTGCPHYS)pTLBEntry->addend, (RTGCPTR)addr, pVM->rem.s.iHandlerMemType, pVM->rem.s.iMMIOMemType, (RTGCPHYS)IoTlbEntry));
     DBGFR3Info(pVM->pUVM, "handlers", NULL, DBGFR3InfoLogRelHlp());
     LogRel(("*** mmio\n"));
@@ -4094 +4095 @@
  * @param   cb              Size of the code block.
  */
-void disas(FILE *phFile, void *pvCode, unsigned long cb)
+void disas(FILE *phFileIgnored, void *pvCode, unsigned long cb)
 {
     if (LogIs2Enabled())
@@ -4134 +4135 @@
  * @param   fFlags          Flags, probably something which tells if this is 16, 32 or 64 bit code.
  */
-void target_disas(FILE *phFile, target_ulong uCode, target_ulong cb, int fFlags)
+void target_disas(FILE *phFileIgnored, target_ulong uCode, target_ulong cb, int fFlags)
 {
     if (LogIs2Enabled())
@@ -4583 +4584 @@
  * @retval -1 failure, raise \#GP(0).
  * @param   env     The cpu state.
- * @param   idMsr   The MSR to read.
- * @param   puValue Where to return the value.
+ * @param   idMsr   The MSR to write to.
+ * @param   uValue  The value to write.
  */
 int cpu_wrmsr(CPUX86State *env, uint32_t idMsr, uint64_t uValue)
@@ -4717 +4718 @@
  * @param   idx         The CPUID leaf (eax).
  * @param   idxSub      The CPUID sub-leaf (ecx) where applicable.
- * @param   pvEAX       Where to store eax.
- * @param   pvEBX       Where to store ebx.
- * @param   pvECX       Where to store ecx.
- * @param   pvEDX       Where to store edx.
+ * @param   pEAX        Where to store eax.
+ * @param   pEBX        Where to store ebx.
+ * @param   pECX        Where to store ecx.
+ * @param   pEDX        Where to store edx.
  */
 void cpu_x86_cpuid(CPUX86State *env, uint32_t idx, uint32_t idxSub,