VirtualBox

Ignore:
Timestamp:
Oct 28, 2015 8:17:18 PM (9 years ago)
Author:
vboxsync
Message:

EFI/Firmware: 'svn merge /vendor/edk2/UDK2010.SR1 /vendor/edk2/current .', reverting and removing files+dirs listed in ReadMe.vbox, resolving conflicts with help from ../UDK2014.SP1/. This is a raw untested merge.

Location:
trunk/src/VBox/Devices/EFI/Firmware
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/Firmware

  • trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Library/SmmPciLibPciRootBridgeIo/PciLib.c

    r48674 r58459  
    22  PCI Library using SMM PCI Root Bridge I/O Protocol.
    33
    4   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
     4  Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
    55  This program and the accompanying materials are
    66  licensed and made available under the terms and conditions of
    … …  
    363363  If EndBit is greater than 7, then ASSERT().
    364364  If EndBit is less than StartBit, then ASSERT().
     365  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    365366
    366367  @param  Address   The PCI configuration register to write.
    … …  
    404405  If EndBit is greater than 7, then ASSERT().
    405406  If EndBit is less than StartBit, then ASSERT().
     407  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    406408
    407409  @param  Address   The PCI configuration register to write.
    … …  
    445447  If EndBit is greater than 7, then ASSERT().
    446448  If EndBit is less than StartBit, then ASSERT().
     449  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    447450
    448451  @param  Address   The PCI configuration register to write.
    … …  
    488491  If EndBit is greater than 7, then ASSERT().
    489492  If EndBit is less than StartBit, then ASSERT().
     493  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
     494  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    490495
    491496  @param  Address   The PCI configuration register to write.
    … …  
    714719  If EndBit is greater than 15, then ASSERT().
    715720  If EndBit is less than StartBit, then ASSERT().
     721  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    716722
    717723  @param  Address   The PCI configuration register to write.
    … …  
    756762  If EndBit is greater than 15, then ASSERT().
    757763  If EndBit is less than StartBit, then ASSERT().
     764  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    758765
    759766  @param  Address   The PCI configuration register to write.
    … …  
    798805  If EndBit is greater than 15, then ASSERT().
    799806  If EndBit is less than StartBit, then ASSERT().
     807  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    800808
    801809  @param  Address   The PCI configuration register to write.
    … …  
    842850  If EndBit is greater than 15, then ASSERT().
    843851  If EndBit is less than StartBit, then ASSERT().
     852  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
     853  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    844854
    845855  @param  Address   The PCI configuration register to write.
    … …  
    10681078  If EndBit is greater than 31, then ASSERT().
    10691079  If EndBit is less than StartBit, then ASSERT().
     1080  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    10701081
    10711082  @param  Address   The PCI configuration register to write.
    … …  
    11101121  If EndBit is greater than 31, then ASSERT().
    11111122  If EndBit is less than StartBit, then ASSERT().
     1123  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    11121124
    11131125  @param  Address   The PCI configuration register to write.
    … …  
    11521164  If EndBit is greater than 31, then ASSERT().
    11531165  If EndBit is less than StartBit, then ASSERT().
     1166  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    11541167
    11551168  @param  Address   The PCI configuration register to write.
    … …  
    11961209  If EndBit is greater than 31, then ASSERT().
    11971210  If EndBit is less than StartBit, then ASSERT().
     1211  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
     1212  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
    11981213
    11991214  @param  Address   The PCI configuration register to write.

  • trunk/src/VBox/Devices/EFI/Firmware/MdePkg/Library/SmmPciLibPciRootBridgeIo/SmmPciLibPciRootBridgeIo.inf

    r48674 r58459  
    33#
    44# This library produces the APIs from the PCI Library and implements these APIs
    5 #  by calling into the PCI Root Bridge I/O Protocol. The PCI Root Bridge I/O Protocol is
    6 #  typically produced by a chipset specific DXE driver.
    7 #  This library binds to the first PCI Root Bridge I/O Protocol in the platform. As a result,
     5#  by calling into SMM PCI Root Bridge I/O Protocol. SMM PCI Root Bridge I/O Protocol is
     6#  typically produced by a chipset specific SMM driver.
     7#  This library binds to the first SMM PCI Root Bridge I/O Protocol in the platform. As a result,
    88#  it should only be used on platforms that contain a single PCI root bridge.
    99#
    10 # Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
     10# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
    1111#
    1212#  This program and the accompanying materials
    … …  
    2323  INF_VERSION                    = 0x00010005
    2424  BASE_NAME                      = SmmPciLibPciRootBridgeIo
     25  MODULE_UNI_FILE                = SmmPciLibPciRootBridgeIo.uni
    2526  FILE_GUID                      = F6994CBA-2351-4ebc-A2DA-20BAC2FE2CF3
    2627  MODULE_TYPE                    = DXE_SMM_DRIVER
    … …  
    5253[Depex.common.DXE_SMM_DRIVER]
    5354  gEfiSmmPciRootBridgeIoProtocolGuid
     55
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette