Changeset 59004 in vbox
- Timestamp:
- Dec 5, 2015 12:07:54 AM (9 years ago)
- svn:sync-xref-src-repo-rev:
- 104532
- Location:
- trunk
- Files:
-
- 3 edited
-
include/VBox/vmm/dbgf.h (modified) (2 diffs)
-
src/VBox/VMM/VBoxVMM.d (modified) (2 diffs)
-
src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (17 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/dbgf.h
r59000 r59004 201 201 * via DBGFR3xxx and queried via DBGFR3yyy. */ 202 202 DBGFEVENT_FIRST_SELECTABLE, 203 /** Tripple fault. 204 * @todo not yet implemented. */ 203 /** Tripple fault. */ 205 204 DBGFEVENT_TRIPLE_FAULT = DBGFEVENT_FIRST_SELECTABLE, 206 DBGFEVENT_XCPT_DE, /**< 0x00 - \#DE - Fault - NoErr - Integer divide error (zero/overflow). */ 207 DBGFEVENT_XCPT_DB, /**< 0x01 - \#DB - trap/fault - NoErr - debug event. */ 208 DBGFEVENT_XCPT_02, /**< 0x02 - Reserved for NMI, see interrupt events. */ 209 DBGFEVENT_XCPT_BP, /**< 0x03 - \#BP - Trap - NoErr - Breakpoint, INT 3 instruction. */ 210 DBGFEVENT_XCPT_OF, /**< 0x04 - \#OF - Trap - NoErr - Overflow, INTO instruction. */ 211 DBGFEVENT_XCPT_BR, /**< 0x05 - \#BR - Fault - NoErr - BOUND Range Exceeded, BOUND instruction. */ 212 DBGFEVENT_XCPT_UD, /**< 0x06 - \#UD - Fault - NoErr - Undefined(/Invalid) Opcode. */ 213 DBGFEVENT_XCPT_NM, /**< 0x07 - \#NM - Fault - NoErr - Device not available, FP or (F)WAIT instruction. */ 214 DBGFEVENT_XCPT_DF, /**< 0x08 - \#DF - Abort - Err=0 - Double fault. */ 215 DBGFEVENT_XCPT_09, /**< 0x09 - Int9 - Fault - NoErr - Coprocessor Segment Overrun (obsolete). */ 216 DBGFEVENT_XCPT_TS, /**< 0x0a - \#TS - Fault - ErrCd - Invalid TSS, Taskswitch or TSS access. */ 217 DBGFEVENT_XCPT_NP, /**< 0x0b - \#NP - Fault - ErrCd - Segment not present. */ 218 DBGFEVENT_XCPT_SS, /**< 0x0c - \#SS - Fault - ErrCd - Stack-Segment fault. */ 219 DBGFEVENT_XCPT_GP, /**< 0x0d - \#GP - Fault - ErrCd - General protection fault. */ 220 DBGFEVENT_XCPT_PF, /**< 0x0e - \#PF - Fault - ErrCd - Page fault. - interrupt gate!!! */ 221 DBGFEVENT_XCPT_0f, /**< 0x0f - Rsvd - Resvd - Resvd - Intel Reserved. */ 222 DBGFEVENT_XCPT_MF, /**< 0x10 - \#MF - Fault - NoErr - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */ 223 DBGFEVENT_XCPT_AC, /**< 0x11 - \#AC - Fault - Err=0 - Alignment Check. */ 224 DBGFEVENT_XCPT_MC, /**< 0x12 - \#MC - Abort - NoErr - Machine Check. */ 225 DBGFEVENT_XCPT_XF, /**< 0x13 - \#XF - Fault - NoErr - SIMD Floating-Point Exception. */ 226 DBGFEVENT_XCPT_VE, /**< 0x14 - \#VE - Fault - Noerr - Virtualization exception. */ 227 DBGFEVENT_XCPT_15, /**< 0x15 - Intel Reserved. */ 228 DBGFEVENT_XCPT_16, /**< 0x16 - Intel Reserved. */ 229 DBGFEVENT_XCPT_17, /**< 0x17 - Intel Reserved. */ 230 DBGFEVENT_XCPT_18, /**< 0x18 - Intel Reserved. */ 231 DBGFEVENT_XCPT_19, /**< 0x19 - Intel Reserved. */ 232 DBGFEVENT_XCPT_1a, /**< 0x1a - Intel Reserved. */ 233 DBGFEVENT_XCPT_1b, /**< 0x1b - Intel Reserved. */ 234 DBGFEVENT_XCPT_1c, /**< 0x1c - Intel Reserved. */ 235 DBGFEVENT_XCPT_1d, /**< 0x1d - Intel Reserved. */ 236 DBGFEVENT_XCPT_SX, /**< 0x1e - \#SX - Fault - ErrCd - Security Exception. */ 237 DBGFEVENT_XCPT_1f, /**< 0x1f - Intel Reserved. */ 238 /** The first exception event. */ 239 DBGFEVENT_XCPT_FIRST = DBGFEVENT_XCPT_DE, 240 /** The last exception event. */ 241 DBGFEVENT_XCPT_LAST = DBGFEVENT_XCPT_1f, 205 206 /** @name Exception events 207 * The exception events normally represents guest exceptions, but depending on 208 * the execution mode some virtualization exceptions may occure (no nested 209 * paging, raw-mode, ++). When necessary, we will request additional VM exits. 210 * @{ */ 211 DBGFEVENT_XCPT_FIRST, /**< The first exception event. */ 212 DBGFEVENT_XCPT_DE /**< 0x00 - \#DE - Fault - NoErr - Integer divide error (zero/overflow). */ 213 = DBGFEVENT_XCPT_FIRST, 214 DBGFEVENT_XCPT_DB, /**< 0x01 - \#DB - trap/fault - NoErr - debug event. */ 215 DBGFEVENT_XCPT_02, /**< 0x02 - Reserved for NMI, see interrupt events. */ 216 DBGFEVENT_XCPT_BP, /**< 0x03 - \#BP - Trap - NoErr - Breakpoint, INT 3 instruction. */ 217 DBGFEVENT_XCPT_OF, /**< 0x04 - \#OF - Trap - NoErr - Overflow, INTO instruction. */ 218 DBGFEVENT_XCPT_BR, /**< 0x05 - \#BR - Fault - NoErr - BOUND Range Exceeded, BOUND instruction. */ 219 DBGFEVENT_XCPT_UD, /**< 0x06 - \#UD - Fault - NoErr - Undefined(/Invalid) Opcode. */ 220 DBGFEVENT_XCPT_NM, /**< 0x07 - \#NM - Fault - NoErr - Device not available, FP or (F)WAIT instruction. */ 221 DBGFEVENT_XCPT_DF, /**< 0x08 - \#DF - Abort - Err=0 - Double fault. */ 222 DBGFEVENT_XCPT_09, /**< 0x09 - Int9 - Fault - NoErr - Coprocessor Segment Overrun (obsolete). */ 223 DBGFEVENT_XCPT_TS, /**< 0x0a - \#TS - Fault - ErrCd - Invalid TSS, Taskswitch or TSS access. */ 224 DBGFEVENT_XCPT_NP, /**< 0x0b - \#NP - Fault - ErrCd - Segment not present. */ 225 DBGFEVENT_XCPT_SS, /**< 0x0c - \#SS - Fault - ErrCd - Stack-Segment fault. */ 226 DBGFEVENT_XCPT_GP, /**< 0x0d - \#GP - Fault - ErrCd - General protection fault. */ 227 DBGFEVENT_XCPT_PF, /**< 0x0e - \#PF - Fault - ErrCd - Page fault. - interrupt gate!!! */ 228 DBGFEVENT_XCPT_0f, /**< 0x0f - Rsvd - Resvd - Resvd - Intel Reserved. */ 229 DBGFEVENT_XCPT_MF, /**< 0x10 - \#MF - Fault - NoErr - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */ 230 DBGFEVENT_XCPT_AC, /**< 0x11 - \#AC - Fault - Err=0 - Alignment Check. */ 231 DBGFEVENT_XCPT_MC, /**< 0x12 - \#MC - Abort - NoErr - Machine Check. */ 232 DBGFEVENT_XCPT_XF, /**< 0x13 - \#XF - Fault - NoErr - SIMD Floating-Point Exception. */ 233 DBGFEVENT_XCPT_VE, /**< 0x14 - \#VE - Fault - Noerr - Virtualization exception. */ 234 DBGFEVENT_XCPT_15, /**< 0x15 - Intel Reserved. */ 235 DBGFEVENT_XCPT_16, /**< 0x16 - Intel Reserved. */ 236 DBGFEVENT_XCPT_17, /**< 0x17 - Intel Reserved. */ 237 DBGFEVENT_XCPT_18, /**< 0x18 - Intel Reserved. */ 238 DBGFEVENT_XCPT_19, /**< 0x19 - Intel Reserved. */ 239 DBGFEVENT_XCPT_1a, /**< 0x1a - Intel Reserved. */ 240 DBGFEVENT_XCPT_1b, /**< 0x1b - Intel Reserved. */ 241 DBGFEVENT_XCPT_1c, /**< 0x1c - Intel Reserved. */ 242 DBGFEVENT_XCPT_1d, /**< 0x1d - Intel Reserved. */ 243 DBGFEVENT_XCPT_SX, /**< 0x1e - \#SX - Fault - ErrCd - Security Exception. */ 244 DBGFEVENT_XCPT_1f, /**< 0x1f - Intel Reserved. */ 245 DBGFEVENT_XCPT_LAST /**< The last exception event. */ 246 = DBGFEVENT_XCPT_1f, 247 /** @} */ 248 249 /** @name Instruction events 250 * The instruction events exerts all possible effort to intercept the 251 * relevant instructions. However, in some execution modes we won't be able 252 * to catch them. So it goes. 253 * @{ */ 254 DBGFEVENT_INSTR_FIRST, /**< The first VM instruction event. */ 255 DBGFEVENT_INSTR_HALT /**< Instruction: HALT */ 256 = DBGFEVENT_INSTR_FIRST, 257 DBGFEVENT_INSTR_MWAIT, /**< Instruction: MWAIT */ 258 DBGFEVENT_INSTR_MONITOR, /**< Instruction: MONITOR */ 259 DBGFEVENT_INSTR_CPUID, /**< Instruction: CPUID (missing stuff in raw-mode). */ 260 DBGFEVENT_INSTR_INVD, /**< Instruction: INVD */ 261 DBGFEVENT_INSTR_WBINVD, /**< Instruction: WBINVD */ 262 DBGFEVENT_INSTR_INVLPG, /**< Instruction: INVLPG */ 263 DBGFEVENT_INSTR_RDTSC, /**< Instruction: RDTSC */ 264 DBGFEVENT_INSTR_RDTSCP, /**< Instruction: RDTSCP */ 265 DBGFEVENT_INSTR_RDPMC, /**< Instruction: RDPMC */ 266 DBGFEVENT_INSTR_RDMSR, /**< Instruction: RDMSR */ 267 DBGFEVENT_INSTR_WRMSR, /**< Instruction: WRMSR */ 268 DBGFEVENT_INSTR_CRX_READ, /**< Instruction: CRx read instruction (missing smsw in raw-mode, and reads in general in VT-x). */ 269 DBGFEVENT_INSTR_CRX_WRITE, /**< Instruction: CRx write */ 270 DBGFEVENT_INSTR_DRX_READ, /**< Instruction: DRx read */ 271 DBGFEVENT_INSTR_DRX_WRITE, /**< Instruction: DRx write */ 272 DBGFEVENT_INSTR_PAUSE, /**< Instruction: PAUSE instruction (not in raw-mode). */ 273 DBGFEVENT_INSTR_XSETBV, /**< Instruction: XSETBV */ 274 DBGFEVENT_INSTR_SIDT, /**< Instruction: SIDT */ 275 DBGFEVENT_INSTR_LIDT, /**< Instruction: LIDT */ 276 DBGFEVENT_INSTR_SGDT, /**< Instruction: SGDT */ 277 DBGFEVENT_INSTR_LGDT, /**< Instruction: LGDT */ 278 DBGFEVENT_INSTR_SLDT, /**< Instruction: SLDT */ 279 DBGFEVENT_INSTR_LLDT, /**< Instruction: LLDT */ 280 DBGFEVENT_INSTR_STR, /**< Instruction: STR */ 281 DBGFEVENT_INSTR_LTR, /**< Instruction: LTR */ 282 DBGFEVENT_INSTR_GETSEC, /**< Instruction: GETSEC */ 283 DBGFEVENT_INSTR_RSM, /**< Instruction: RSM */ 284 DBGFEVENT_INSTR_RDRAND, /**< Instruction: RDRAND */ 285 DBGFEVENT_INSTR_RDSEED, /**< Instruction: RDSEED */ 286 DBGFEVENT_INSTR_XSAVES, /**< Instruction: XSAVES */ 287 DBGFEVENT_INSTR_XRSTORS, /**< Instruction: XRSTORS */ 288 DBGFEVENT_INSTR_VMM_CALL, /**< Instruction: VMCALL (intel) or VMMCALL (AMD) */ 289 DBGFEVENT_INSTR_LAST_COMMON /**< Instruction: the last common event. */ 290 = DBGFEVENT_INSTR_VMM_CALL, 291 DBGFEVENT_INSTR_VMX_FIRST, /**< Instruction: VT-x - First. */ 292 DBGFEVENT_INSTR_VMX_VMCLEAR /**< Instruction: VT-x VMCLEAR */ 293 = DBGFEVENT_INSTR_VMX_FIRST, 294 DBGFEVENT_INSTR_VMX_VMLAUNCH, /**< Instruction: VT-x VMLAUNCH */ 295 DBGFEVENT_INSTR_VMX_VMPTRLD, /**< Instruction: VT-x VMPTRLD */ 296 DBGFEVENT_INSTR_VMX_VMPTRST, /**< Instruction: VT-x VMPTRST */ 297 DBGFEVENT_INSTR_VMX_VMREAD, /**< Instruction: VT-x VMREAD */ 298 DBGFEVENT_INSTR_VMX_VMRESUME, /**< Instruction: VT-x VMRESUME */ 299 DBGFEVENT_INSTR_VMX_VMWRITE, /**< Instruction: VT-x VMWRITE */ 300 DBGFEVENT_INSTR_VMX_VMXOFF, /**< Instruction: VT-x VMXOFF */ 301 DBGFEVENT_INSTR_VMX_VMXON, /**< Instruction: VT-x VMXON */ 302 DBGFEVENT_INSTR_VMX_VMFUNC, /**< Instruction: VT-x VMFUNC */ 303 DBGFEVENT_INSTR_VMX_INVEPT, /**< Instruction: VT-x INVEPT */ 304 DBGFEVENT_INSTR_VMX_INVVPID, /**< Instruction: VT-x INVVPID */ 305 DBGFEVENT_INSTR_VMX_INVPCID, /**< Instruction: VT-x INVPCID */ 306 DBGFEVENT_INSTR_VMX_LAST /**< Instruction: VT-x - Last. */ 307 = DBGFEVENT_INSTR_VMX_INVPCID, 308 DBGFEVENT_INSTR_SVM_FIRST, /**< Instruction: AMD-V - first */ 309 DBGFEVENT_INSTR_SVM_VMRUN /**< Instruction: AMD-V VMRUN */ 310 = DBGFEVENT_INSTR_SVM_FIRST, 311 DBGFEVENT_INSTR_SVM_VMLOAD, /**< Instruction: AMD-V VMLOAD */ 312 DBGFEVENT_INSTR_SVM_VMSAVE, /**< Instruction: AMD-V VMSAVE */ 313 DBGFEVENT_INSTR_SVM_STGI, /**< Instruction: AMD-V STGI */ 314 DBGFEVENT_INSTR_SVM_CLGI, /**< Instruction: AMD-V CLGI */ 315 DBGFEVENT_INSTR_SVM_LAST /**< Instruction: The last ADM-V VM exit event. */ 316 = DBGFEVENT_INSTR_SVM_CLGI, 317 DBGFEVENT_INSTR_LAST /**< Instruction: The last instruction event. */ 318 = DBGFEVENT_INSTR_SVM_LAST, 319 /** @} */ 320 321 322 /** @name VM exit events. 323 * VM exits events for VT-x and AMD-V execution mode. Many of the VM exits 324 * behind these events are also directly translated into instruction events, but 325 * the difference here is that the exit events will not try provoke the exits. 326 * @{ */ 327 DBGFEVENT_EXIT_FIRST, /**< The first VM exit event. */ 328 DBGFEVENT_EXIT_TASK_SWITCH /**< Exit: Task switch. */ 329 = DBGFEVENT_EXIT_FIRST, 330 DBGFEVENT_EXIT_HALT, /**< Exit: HALT instruction. */ 331 DBGFEVENT_EXIT_MWAIT, /**< Exit: MWAIT instruction. */ 332 DBGFEVENT_EXIT_MONITOR, /**< Exit: MONITOR instruction. */ 333 DBGFEVENT_EXIT_CPUID, /**< Exit: CPUID instruction (missing stuff in raw-mode). */ 334 DBGFEVENT_EXIT_INVD, /**< Exit: INVD instruction. */ 335 DBGFEVENT_EXIT_WBINVD, /**< Exit: WBINVD instruction. */ 336 DBGFEVENT_EXIT_INVLPG, /**< Exit: INVLPG instruction. */ 337 DBGFEVENT_EXIT_RDTSC, /**< Exit: RDTSC instruction. */ 338 DBGFEVENT_EXIT_RDTSCP, /**< Exit: RDTSCP instruction. */ 339 DBGFEVENT_EXIT_RDPMC, /**< Exit: RDPMC instruction. */ 340 DBGFEVENT_EXIT_RDMSR, /**< Exit: RDMSR instruction. */ 341 DBGFEVENT_EXIT_WRMSR, /**< Exit: WRMSR instruction. */ 342 DBGFEVENT_EXIT_CRX_READ, /**< Exit: CRx read instruction (missing smsw in raw-mode, and reads in general in VT-x). */ 343 DBGFEVENT_EXIT_CRX_WRITE, /**< Exit: CRx write instruction. */ 344 DBGFEVENT_EXIT_DRX_READ, /**< Exit: DRx read instruction. */ 345 DBGFEVENT_EXIT_DRX_WRITE, /**< Exit: DRx write instruction. */ 346 DBGFEVENT_EXIT_PAUSE, /**< Exit: PAUSE instruction (not in raw-mode). */ 347 DBGFEVENT_EXIT_XSETBV, /**< Exit: XSETBV instruction. */ 348 DBGFEVENT_EXIT_SIDT, /**< Exit: SIDT instruction. */ 349 DBGFEVENT_EXIT_LIDT, /**< Exit: LIDT instruction. */ 350 DBGFEVENT_EXIT_SGDT, /**< Exit: SGDT instruction. */ 351 DBGFEVENT_EXIT_LGDT, /**< Exit: LGDT instruction. */ 352 DBGFEVENT_EXIT_SLDT, /**< Exit: SLDT instruction. */ 353 DBGFEVENT_EXIT_LLDT, /**< Exit: LLDT instruction. */ 354 DBGFEVENT_EXIT_STR, /**< Exit: STR instruction. */ 355 DBGFEVENT_EXIT_LTR, /**< Exit: LTR instruction. */ 356 DBGFEVENT_EXIT_GETSEC, /**< Exit: GETSEC instruction. */ 357 DBGFEVENT_EXIT_RSM, /**< Exit: RSM instruction. */ 358 DBGFEVENT_EXIT_RDRAND, /**< Exit: RDRAND instruction. */ 359 DBGFEVENT_EXIT_RDSEED, /**< Exit: RDSEED instruction. */ 360 DBGFEVENT_EXIT_XSAVES, /**< Exit: XSAVES instruction. */ 361 DBGFEVENT_EXIT_XRSTORS, /**< Exit: XRSTORS instruction. */ 362 DBGFEVENT_EXIT_VMM_CALL, /**< Exit: VMCALL (intel) or VMMCALL (AMD) instruction. */ 363 DBGFEVENT_EXIT_LAST_COMMON /**< Exit: the last common event. */ 364 = DBGFEVENT_EXIT_VMM_CALL, 365 DBGFEVENT_EXIT_VMX_FIRST, /**< Exit: VT-x - First. */ 366 DBGFEVENT_EXIT_VMX_VMCLEAR /**< Exit: VT-x VMCLEAR instruction. */ 367 = DBGFEVENT_EXIT_VMX_FIRST, 368 DBGFEVENT_EXIT_VMX_VMLAUNCH, /**< Exit: VT-x VMLAUNCH instruction. */ 369 DBGFEVENT_EXIT_VMX_VMPTRLD, /**< Exit: VT-x VMPTRLD instruction. */ 370 DBGFEVENT_EXIT_VMX_VMPTRST, /**< Exit: VT-x VMPTRST instruction. */ 371 DBGFEVENT_EXIT_VMX_VMREAD, /**< Exit: VT-x VMREAD instruction. */ 372 DBGFEVENT_EXIT_VMX_VMRESUME, /**< Exit: VT-x VMRESUME instruction. */ 373 DBGFEVENT_EXIT_VMX_VMWRITE, /**< Exit: VT-x VMWRITE instruction. */ 374 DBGFEVENT_EXIT_VMX_VMXOFF, /**< Exit: VT-x VMXOFF instruction. */ 375 DBGFEVENT_EXIT_VMX_VMXON, /**< Exit: VT-x VMXON instruction. */ 376 DBGFEVENT_EXIT_VMX_VMFUNC, /**< Exit: VT-x VMFUNC instruction. */ 377 DBGFEVENT_EXIT_VMX_INVEPT, /**< Exit: VT-x INVEPT instruction. */ 378 DBGFEVENT_EXIT_VMX_INVVPID, /**< Exit: VT-x INVVPID instruction. */ 379 DBGFEVENT_EXIT_VMX_INVPCID, /**< Exit: VT-x INVPCID instruction. */ 380 DBGFEVENT_EXIT_VMX_EPT_VIOLATION, /**< Exit: VT-x EPT violation. */ 381 DBGFEVENT_EXIT_VMX_EPT_MISCONFIG, /**< Exit: VT-x EPT misconfiguration. */ 382 DBGFEVENT_EXIT_VMX_VAPIC_ACCESS, /**< Exit: VT-x Virtual APIC page access. */ 383 DBGFEVENT_EXIT_VMX_VAPIC_WRITE, /**< Exit: VT-x Virtual APIC write. */ 384 DBGFEVENT_EXIT_VMX_LAST /**< Exit: VT-x - Last. */ 385 = DBGFEVENT_EXIT_VMX_VAPIC_WRITE, 386 DBGFEVENT_EXIT_SVM_FIRST, /**< Exit: AMD-V - first */ 387 DBGFEVENT_EXIT_SVM_VMRUN /**< Exit: AMD-V VMRUN instruction. */ 388 = DBGFEVENT_EXIT_SVM_FIRST, 389 DBGFEVENT_EXIT_SVM_VMLOAD, /**< Exit: AMD-V VMLOAD instruction. */ 390 DBGFEVENT_EXIT_SVM_VMSAVE, /**< Exit: AMD-V VMSAVE instruction. */ 391 DBGFEVENT_EXIT_SVM_STGI, /**< Exit: AMD-V STGI instruction. */ 392 DBGFEVENT_EXIT_SVM_CLGI, /**< Exit: AMD-V CLGI instruction. */ 393 DBGFEVENT_EXIT_SVM_LAST /**< Exit: The last ADM-V VM exit event. */ 394 = DBGFEVENT_EXIT_SVM_CLGI, 395 DBGFEVENT_EXIT_LAST /**< Exit: The last VM exit event. */ 396 = DBGFEVENT_EXIT_SVM_LAST, 397 /** @} */ 398 399 242 400 /** Access to an unassigned I/O port. 243 401 * @todo not yet implemented. */ … … 252 410 * @todo not yet implemented. */ 253 411 DBGFEVENT_MEMORY_ROM_WRITE, 254 255 /** The first VM exit event. */256 DBGFEVENT_EXIT_FIRST,257 /** Exit - Task switch.258 * @todo not yet implemented. */259 DBGFEVENT_EXIT_TASK_SWITCH = DBGFEVENT_EXIT_FIRST,260 /** Exit - HALT instruction.261 * @todo not yet implemented. */262 DBGFEVENT_EXIT_HALT,263 /** Exit - MWAIT instruction.264 * @todo not yet implemented. */265 DBGFEVENT_EXIT_MWAIT,266 /** Exit - MONITOR instruction.267 * @todo not yet implemented. */268 DBGFEVENT_EXIT_MONITOR,269 /** Exit - CPUID instruction (missing stuff in raw-mode).270 * @todo not yet implemented. */271 DBGFEVENT_EXIT_CPUID,272 /** Exit - INVD instruction.273 * @todo not yet implemented. */274 DBGFEVENT_EXIT_INVD,275 /** Exit - WBINVD instruction.276 * @todo not yet implemented. */277 DBGFEVENT_EXIT_WBINVD,278 /** Exit - INVLPG instruction.279 * @todo not yet implemented. */280 DBGFEVENT_EXIT_INVLPG,281 /** Exit - RDTSC instruction.282 * @todo not yet implemented. */283 DBGFEVENT_EXIT_RDTSC,284 /** Exit - RDTSCP instruction.285 * @todo not yet implemented. */286 DBGFEVENT_EXIT_RDTSCP,287 /** Exit - RDPMC instruction.288 * @todo not yet implemented. */289 DBGFEVENT_EXIT_RDPMC,290 /** Exit - RDMSR instruction.291 * @todo not yet implemented. */292 DBGFEVENT_EXIT_RDMSR,293 /** Exit - WRMSR instruction.294 * @todo not yet implemented. */295 DBGFEVENT_EXIT_WRMSR,296 /** Exit - CRx read instruction (missing smsw in raw-mode, and reads in297 * general in VT-x).298 * @todo not yet implemented. */299 DBGFEVENT_EXIT_CRX_READ,300 /** Exit - CRx write instruction.301 * @todo not yet implemented. */302 DBGFEVENT_EXIT_CRX_WRITE,303 /** Exit - DRx read instruction.304 * @todo not yet implemented. */305 DBGFEVENT_EXIT_DRX_READ,306 /** Exit - DRx write instruction.307 * @todo not yet implemented. */308 DBGFEVENT_EXIT_DRX_WRITE,309 /** Exit - PAUSE instruction (not in raw-mode).310 * @todo not yet implemented. */311 DBGFEVENT_EXIT_PAUSE,312 /** Exit - XSETBV instruction.313 * @todo not yet implemented. */314 DBGFEVENT_EXIT_XSETBV,315 /** Exit - SIDT instruction.316 * @todo not yet implemented. */317 DBGFEVENT_EXIT_SIDT,318 /** Exit - LIDT instruction.319 * @todo not yet implemented. */320 DBGFEVENT_EXIT_LIDT,321 /** Exit - SGDT instruction.322 * @todo not yet implemented. */323 DBGFEVENT_EXIT_SGDT,324 /** Exit - LGDT instruction.325 * @todo not yet implemented. */326 DBGFEVENT_EXIT_LGDT,327 /** Exit - SLDT instruction.328 * @todo not yet implemented. */329 DBGFEVENT_EXIT_SLDT,330 /** Exit - LLDT instruction.331 * @todo not yet implemented. */332 DBGFEVENT_EXIT_LLDT,333 /** Exit - STR instruction.334 * @todo not yet implemented. */335 DBGFEVENT_EXIT_STR,336 /** Exit - LTR instruction.337 * @todo not yet implemented. */338 DBGFEVENT_EXIT_LTR,339 /** Exit - GETSEC instruction.340 * @todo not yet implemented. */341 DBGFEVENT_EXIT_GETSEC,342 /** Exit - RSM instruction.343 * @todo not yet implemented. */344 DBGFEVENT_EXIT_RSM,345 /** Exit - RDRAND instruction.346 * @todo not yet implemented. */347 DBGFEVENT_EXIT_RDRAND,348 /** Exit - RDSEED instruction.349 * @todo not yet implemented. */350 DBGFEVENT_EXIT_RDSEED,351 /** Exit - XSAVES instruction.352 * @todo not yet implemented. */353 DBGFEVENT_EXIT_XSAVES,354 /** Exit - XRSTORS instruction.355 * @todo not yet implemented. */356 DBGFEVENT_EXIT_XRSTORS,357 /** Exit - VMCALL (intel) or VMMCALL (AMD) instruction.358 * @todo not yet implemented. */359 DBGFEVENT_EXIT_VMM_CALL,360 /** Exit - the last common event. */361 DBGFEVENT_EXIT_LAST_COMMON = DBGFEVENT_EXIT_VMM_CALL,362 363 /** Exit - VT-x - First. */364 DBGFEVENT_EXIT_VMX_FIRST,365 /** Exit - VT-x VMCLEAR instruction.366 * @todo not yet implemented. */367 DBGFEVENT_EXIT_VMX_VMCLEAR = DBGFEVENT_EXIT_VMX_FIRST,368 /** Exit - VT-x VMLAUNCH instruction.369 * @todo not yet implemented. */370 DBGFEVENT_EXIT_VMX_VMLAUNCH,371 /** Exit - VT-x VMPTRLD instruction.372 * @todo not yet implemented. */373 DBGFEVENT_EXIT_VMX_VMPTRLD,374 /** Exit - VT-x VMPTRST instruction.375 * @todo not yet implemented. */376 DBGFEVENT_EXIT_VMX_VMPTRST,377 /** Exit - VT-x VMREAD instruction.378 * @todo not yet implemented. */379 DBGFEVENT_EXIT_VMX_VMREAD,380 /** Exit - VT-x VMRESUME instruction.381 * @todo not yet implemented. */382 DBGFEVENT_EXIT_VMX_VMRESUME,383 /** Exit - VT-x VMWRITE instruction.384 * @todo not yet implemented. */385 DBGFEVENT_EXIT_VMX_VMWRITE,386 /** Exit - VT-x VMXOFF instruction.387 * @todo not yet implemented. */388 DBGFEVENT_EXIT_VMX_VMXOFF,389 /** Exit - VT-x VMXON instruction.390 * @todo not yet implemented. */391 DBGFEVENT_EXIT_VMX_VMXON,392 /** Exit - VT-x VMFUNC instruction.393 * @todo not yet implemented. */394 DBGFEVENT_EXIT_VMX_VMFUNC,395 /** Exit - VT-x INVEPT instruction.396 * @todo not yet implemented. */397 DBGFEVENT_EXIT_VMX_INVEPT,398 /** Exit - VT-x INVVPID instruction.399 * @todo not yet implemented. */400 DBGFEVENT_EXIT_VMX_INVVPID,401 /** Exit - VT-x INVPCID instruction.402 * @todo not yet implemented. */403 DBGFEVENT_EXIT_VMX_INVPCID,404 /** Exit - VT-x EPT violation. */405 DBGFEVENT_EXIT_VMX_EPT_VIOLATION,406 /** Exit - VT-x EPT misconfiguration. */407 DBGFEVENT_EXIT_VMX_EPT_MISCONFIG,408 /** Exit - VT-x Virtual APIC page access. */409 DBGFEVENT_EXIT_VMX_VAPIC_ACCESS,410 /** Exit - VT-x Virtual APIC write. */411 DBGFEVENT_EXIT_VMX_VAPIC_WRITE,412 /** Exit - VT-x - Last. */413 DBGFEVENT_EXIT_VMX_LAST = DBGFEVENT_EXIT_VMX_VAPIC_WRITE,414 415 /** Exit - AMD-V - first */416 DBGFEVENT_EXIT_SVM_FIRST,417 /** Exit - AMD-V VMRUN instruction.418 * @todo not yet implemented. */419 DBGFEVENT_EXIT_SVM_VMRUN = DBGFEVENT_EXIT_SVM_FIRST,420 /** Exit - AMD-V VMLOAD instruction.421 * @todo not yet implemented. */422 DBGFEVENT_EXIT_SVM_VMLOAD,423 /** Exit - AMD-V VMSAVE instruction.424 * @todo not yet implemented. */425 DBGFEVENT_EXIT_SVM_VMSAVE,426 /** Exit - AMD-V STGI instruction.427 * @todo not yet implemented. */428 DBGFEVENT_EXIT_SVM_STGI,429 /** Exit - AMD-V CLGI instruction.430 * @todo not yet implemented. */431 DBGFEVENT_EXIT_SVM_CLGI,432 /** The last ADM-V VM exit event. */433 DBGFEVENT_EXIT_SVM_LAST = DBGFEVENT_EXIT_SVM_CLGI,434 435 /** The last VM exit event. */436 DBGFEVENT_EXIT_LAST = DBGFEVENT_EXIT_SVM_LAST,437 412 438 413 -
trunk/src/VBox/VMM/VBoxVMM.d
r58998 r59004 60 60 61 61 62 /** @name CPU Exception probes 63 * These probes will intercept guest CPU exceptions as best we 64 * can. In some execution modes some of these probes may also 65 * see non-guest exceptions as we don't try distiguish between 66 * virtualization and guest exceptions before firing the probes. 67 * 68 * Using these probes may have a performance impact on guest 69 * activities involving lots of exceptions. 70 * @{ 71 */ 62 72 /** \#DE - integer divide error. */ 63 73 probe xcpt__de(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); … … 96 106 /** \#SX - security exception. */ 97 107 probe xcpt__sx(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t a_uErr); 98 99 /** Software interrupt (INT XXh). */ 108 /** @} */ 109 110 111 /** Software interrupt (INT XXh). 112 * It may be very difficult to implement this probe when using hardware 113 * virtualization, so maybe we have to drop it... */ 100 114 probe int__software(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iInterrupt); 101 /** Hardware interrupt being dispatched. */ 115 /** Hardware interrupt being dispatched. 116 * 117 * Relates to pdm__irq__get ... 118 */ 102 119 probe int__hardware(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iInterrupt, uint32_t a_uTag, uint32_t a_idSource); 103 120 104 /** Exit - Task switch. */ 121 /** @name Instruction probes 122 * These are instructions normally related to VM exits. These 123 * probes differs from the exit probes in that we will try make 124 * these instructions cause exits and fire the probe whenever 125 * they are executed by the guest. This means some of these 126 * probes will have a noticable performance impact (like 127 * instr__pause). 128 * @{ */ 129 /** Instruction: HALT */ 130 probe instr__halt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 131 /** Instruction: MWAIT */ 132 probe instr__mwait(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 133 /** Instruction: MONITOR */ 134 probe instr__monitor(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 135 /** Instruction: CPUID instruction (missing stuff in raw-mode). */ 136 probe instr__cpuid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t uLeaf, uint32_t uSubLeaf); 137 /** Instruction: INVD */ 138 probe instr__invd(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 139 /** Instruction: WBINVD */ 140 probe instr__wbinvd(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 141 /** Instruction: INVLPG */ 142 probe instr__invlpg(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 143 /** Instruction: RDTSC */ 144 probe instr__rdtsc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 145 /** Instruction: RDTSCP */ 146 probe instr__rdtscp(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 147 /** Instruction: RDPMC */ 148 probe instr__rdpmc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 149 /** Instruction: RDMSR */ 150 probe instr__rdmsr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t a_idMsr); 151 /** Instruction: WRMSR */ 152 probe instr__wrmsr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t a_idMsr, uint64_t a_uValue); 153 /** Instruction: CRx read instruction (missing smsw in raw-mode, 154 * and reads in general in VT-x). */ 155 probe instr__crx__read(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 156 /** Instruction: CRx write instruction. */ 157 probe instr__crx__write(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 158 /** Instruction: DRx read instruction. */ 159 probe instr__drx__read(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 160 /** Instruction: DRx write instruction. */ 161 probe instr__drx__write(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 162 /** Instruction: PAUSE instruction (not in raw-mode). */ 163 probe instr__pause(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 164 /** Instruction: XSETBV */ 165 probe instr__xsetbv(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 166 /** Instruction: SIDT */ 167 probe instr__sidt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 168 /** Instruction: LIDT */ 169 probe instr__lidt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 170 /** Instruction: SGDT */ 171 probe instr__sgdt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 172 /** Instruction: LGDT */ 173 probe instr__lgdt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 174 /** Instruction: SLDT */ 175 probe instr__sldt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 176 /** Instruction: LLDT */ 177 probe instr__lldt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 178 /** Instruction: STR */ 179 probe instr__str(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 180 /** Instruction: LTR */ 181 probe instr__ltr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 182 /** Instruction: GETSEC */ 183 probe instr__getsec(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 184 /** Instruction: RSM */ 185 probe instr__rsm(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 186 /** Instruction: RDRAND */ 187 probe instr__rdrand(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 188 /** Instruction: RDSEED */ 189 probe instr__rdseed(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 190 /** Instruction: XSAVES */ 191 probe instr__xsaves(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 192 /** Instruction: XRSTORS */ 193 probe instr__xrstors(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 194 /** Instruction: VMCALL (intel) or VMMCALL (AMD) instruction. */ 195 probe instr__vmm__call(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 196 197 /** Instruction: VT-x VMCLEAR instruction. */ 198 probe instr__vmx__vmclear(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 199 /** Instruction: VT-x VMLAUNCH */ 200 probe instr__vmx__vmlaunch(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 201 /** Instruction: VT-x VMPTRLD */ 202 probe instr__vmx__vmptrld(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 203 /** Instruction: VT-x VMPTRST */ 204 probe instr__vmx__vmptrst(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 205 /** Instruction: VT-x VMREAD */ 206 probe instr__vmx__vmread(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 207 /** Instruction: VT-x VMRESUME */ 208 probe instr__vmx__vmresume(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 209 /** Instruction: VT-x VMWRITE */ 210 probe instr__vmx__vmwrite(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 211 /** Instruction: VT-x VMXOFF */ 212 probe instr__vmx__vmxoff(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 213 /** Instruction: VT-x VMXON */ 214 probe instr__vmx__vmxon(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 215 /** Instruction: VT-x VMFUNC */ 216 probe instr__vmx__vmfunc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 217 /** Instruction: VT-x INVEPT */ 218 probe instr__vmx__invept(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 219 /** Instruction: VT-x INVVPID */ 220 probe instr__vmx__invvpid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 221 /** Instruction: VT-x INVPCID */ 222 probe instr__vmx__invpcid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 223 224 /** Instruction: AMD-V VMRUN */ 225 probe instr__svm__vmrun(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 226 /** Instruction: AMD-V VMLOAD */ 227 probe instr__svm__vmload(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 228 /** Instruction: AMD-V VMSAVE */ 229 probe instr__svm__vmsave(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 230 /** Instruction: AMD-V STGI */ 231 probe instr__svm__stgi(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 232 /** Instruction: AMD-V CLGI */ 233 probe instr__svm__clgi(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 234 /** @} */ 235 236 237 /** @name VM exit probes 238 * These are named exits with (in some cases at least) useful 239 * information as arguments. Unlike the instruction probes, 240 * these will not change the number of VM exits and have much 241 * less of an impact on VM performance. 242 * @{ */ 243 /** VM Exit: Task switch. */ 105 244 probe exit__task__switch(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 106 /** Exit -HALT instruction.245 /** VM Exit: HALT instruction. 107 246 * @todo not yet implemented. */ 108 247 probe exit__halt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 109 /** Exit -MWAIT instruction. */248 /** VM Exit: MWAIT instruction. */ 110 249 probe exit__mwait(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 111 /** Exit -MONITOR instruction. */250 /** VM Exit: MONITOR instruction. */ 112 251 probe exit__monitor(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 113 /** Exit -CPUID instruction (missing stuff in raw-mode). */252 /** VM Exit: CPUID instruction (missing stuff in raw-mode). */ 114 253 probe exit__cpuid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t uLeaf, uint32_t uSubLeaf); 115 /** Exit -INVD instruction. */254 /** VM Exit: INVD instruction. */ 116 255 probe exit__invd(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 117 /** Exit -WBINVD instruction. */256 /** VM Exit: WBINVD instruction. */ 118 257 probe exit__wbinvd(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 119 /** Exit -INVLPG instruction. */258 /** VM Exit: INVLPG instruction. */ 120 259 probe exit__invlpg(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 121 /** Exit -RDTSC instruction. */260 /** VM Exit: RDTSC instruction. */ 122 261 probe exit__rdtsc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 123 /** Exit -RDTSCP instruction. */262 /** VM Exit: RDTSCP instruction. */ 124 263 probe exit__rdtscp(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 125 /** Exit -RDPMC instruction. */264 /** VM Exit: RDPMC instruction. */ 126 265 probe exit__rdpmc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 127 /** Exit -RDMSR instruction. */266 /** VM Exit: RDMSR instruction. */ 128 267 probe exit__rdmsr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t a_idMsr); 129 /** Exit -WRMSR instruction. */268 /** VM Exit: WRMSR instruction. */ 130 269 probe exit__wrmsr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint32_t a_idMsr, uint64_t a_uValue); 131 /** Exit -CRx read instruction (missing smsw in raw-mode,270 /** VM Exit: CRx read instruction (missing smsw in raw-mode, 132 271 * and reads in general in VT-x). */ 133 272 probe exit__crx__read(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 134 /** Exit -CRx write instruction. */273 /** VM Exit: CRx write instruction. */ 135 274 probe exit__crx__write(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 136 /** Exit -DRx read instruction. */275 /** VM Exit: DRx read instruction. */ 137 276 probe exit__drx__read(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 138 /** Exit -DRx write instruction. */277 /** VM Exit: DRx write instruction. */ 139 278 probe exit__drx__write(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx, uint8_t a_iReg); 140 /** Exit -PAUSE instruction (not in raw-mode). */279 /** VM Exit: PAUSE instruction (not in raw-mode). */ 141 280 probe exit__pause(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 142 /** Exit -XSETBV instruction. */281 /** VM Exit: XSETBV instruction. */ 143 282 probe exit__xsetbv(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 144 /** Exit -SIDT instruction. */283 /** VM Exit: SIDT instruction. */ 145 284 probe exit__sidt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 146 /** Exit -LIDT instruction. */285 /** VM Exit: LIDT instruction. */ 147 286 probe exit__lidt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 148 /** Exit -SGDT instruction. */287 /** VM Exit: SGDT instruction. */ 149 288 probe exit__sgdt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 150 /** Exit -LGDT instruction. */289 /** VM Exit: LGDT instruction. */ 151 290 probe exit__lgdt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 152 /** Exit -SLDT instruction. */291 /** VM Exit: SLDT instruction. */ 153 292 probe exit__sldt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 154 /** Exit -LLDT instruction. */293 /** VM Exit: LLDT instruction. */ 155 294 probe exit__lldt(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 156 /** Exit -STR instruction. */295 /** VM Exit: STR instruction. */ 157 296 probe exit__str(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 158 /** Exit -LTR instruction. */297 /** VM Exit: LTR instruction. */ 159 298 probe exit__ltr(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 160 /** Exit -GETSEC instruction. */299 /** VM Exit: GETSEC instruction. */ 161 300 probe exit__getsec(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 162 /** Exit -RSM instruction. */301 /** VM Exit: RSM instruction. */ 163 302 probe exit__rsm(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 164 /** Exit -RDRAND instruction. */303 /** VM Exit: RDRAND instruction. */ 165 304 probe exit__rdrand(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 166 /** Exit -RDSEED instruction. */305 /** VM Exit: RDSEED instruction. */ 167 306 probe exit__rdseed(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 168 /** Exit -XSAVES instruction. */307 /** VM Exit: XSAVES instruction. */ 169 308 probe exit__xsaves(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 170 /** Exit -XRSTORS instruction. */309 /** VM Exit: XRSTORS instruction. */ 171 310 probe exit__xrstors(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 172 /** Exit -VMCALL (intel) or VMMCALL (AMD) instruction. */311 /** VM Exit: VMCALL (intel) or VMMCALL (AMD) instruction. */ 173 312 probe exit__vmm__call(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 174 313 175 /** Exit -VT-x VMCLEAR instruction. */314 /** VM Exit: VT-x VMCLEAR instruction. */ 176 315 probe exit__vmx__vmclear(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 177 /** Exit -VT-x VMLAUNCH instruction. */316 /** VM Exit: VT-x VMLAUNCH instruction. */ 178 317 probe exit__vmx__vmlaunch(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 179 /** Exit -VT-x VMPTRLD instruction. */318 /** VM Exit: VT-x VMPTRLD instruction. */ 180 319 probe exit__vmx__vmptrld(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 181 /** Exit -VT-x VMPTRST instruction. */320 /** VM Exit: VT-x VMPTRST instruction. */ 182 321 probe exit__vmx__vmptrst(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 183 /** Exit -VT-x VMREAD instruction. */322 /** VM Exit: VT-x VMREAD instruction. */ 184 323 probe exit__vmx__vmread(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 185 /** Exit -VT-x VMRESUME instruction. */324 /** VM Exit: VT-x VMRESUME instruction. */ 186 325 probe exit__vmx__vmresume(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 187 /** Exit -VT-x VMWRITE instruction. */326 /** VM Exit: VT-x VMWRITE instruction. */ 188 327 probe exit__vmx__vmwrite(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 189 /** Exit -VT-x VMXOFF instruction. */328 /** VM Exit: VT-x VMXOFF instruction. */ 190 329 probe exit__vmx__vmxoff(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 191 /** Exit -VT-x VMXON instruction. */330 /** VM Exit: VT-x VMXON instruction. */ 192 331 probe exit__vmx__vmxon(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 193 /** Exit -VT-x VMFUNC instruction. */332 /** VM Exit: VT-x VMFUNC instruction. */ 194 333 probe exit__vmx__vmfunc(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 195 /** Exit -VT-x INVEPT instruction. */334 /** VM Exit: VT-x INVEPT instruction. */ 196 335 probe exit__vmx__invept(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 197 /** Exit -VT-x INVVPID instruction. */336 /** VM Exit: VT-x INVVPID instruction. */ 198 337 probe exit__vmx__invvpid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 199 /** Exit -VT-x INVPCID instruction. */338 /** VM Exit: VT-x INVPCID instruction. */ 200 339 probe exit__vmx__invpcid(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 201 /** Exit -VT-x EPT violation. */340 /** VM Exit: VT-x EPT violation. */ 202 341 probe exit__vmx__ept__violation(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 203 /** Exit -VT-x EPT misconfiguration. */342 /** VM Exit: VT-x EPT misconfiguration. */ 204 343 probe exit__vmx__ept__misconfig(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 205 /** Exit -VT-x Virtual APIC page access. */344 /** VM Exit: VT-x Virtual APIC page access. */ 206 345 probe exit__vmx__vapic__access(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 207 /** Exit -VT-x Virtual APIC page write needing virtualizing. */346 /** VM Exit: VT-x Virtual APIC page write needing virtualizing. */ 208 347 probe exit__vmx__vapic__write(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 209 348 210 /** Exit -AMD-V VMRUN instruction. */349 /** VM Exit: AMD-V VMRUN instruction. */ 211 350 probe exit__svm__vmrun(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 212 /** Exit -AMD-V VMLOAD instruction. */351 /** VM Exit: AMD-V VMLOAD instruction. */ 213 352 probe exit__svm__vmload(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 214 /** Exit -AMD-V VMSAVE instruction. */353 /** VM Exit: AMD-V VMSAVE instruction. */ 215 354 probe exit__svm__vmsave(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 216 /** Exit -AMD-V STGI instruction. */355 /** VM Exit: AMD-V STGI instruction. */ 217 356 probe exit__svm__stgi(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 218 /** Exit -AMD-V CLGI instruction. */357 /** VM Exit: AMD-V CLGI instruction. */ 219 358 probe exit__svm__clgi(struct VMCPU *a_pVCpu, struct CPUMCTX *a_pCtx); 359 /** @} */ 220 360 }; 221 361 -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r59003 r59004 9145 9145 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */ 9146 9146 9147 SET_ONLY_XBM_IF_EITHER_EN(EXIT_CPUID, VMX_EXIT_CPUID); /* unconditional */ 9148 SET_ONLY_XBM_IF_EITHER_EN(EXIT_GETSEC, VMX_EXIT_GETSEC); /* unconditional */ 9149 SET_CPE1_XBM_IF_EITHER_EN(EXIT_HALT, VMX_EXIT_HLT, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */ 9150 SET_ONLY_XBM_IF_EITHER_EN(EXIT_INVD, VMX_EXIT_INVD); /* unconditional */ 9151 SET_CPE1_XBM_IF_EITHER_EN(EXIT_INVLPG, VMX_EXIT_INVLPG, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT); 9152 SET_CPE1_XBM_IF_EITHER_EN(EXIT_RDPMC, VMX_EXIT_RDPMC, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT); 9153 SET_CPE1_XBM_IF_EITHER_EN(EXIT_RDTSC, VMX_EXIT_RDTSC, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT); 9154 SET_ONLY_XBM_IF_EITHER_EN(EXIT_RSM, VMX_EXIT_RSM); /* unconditional */ 9155 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */ 9156 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */ 9157 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */ 9158 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */ 9159 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */ 9160 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */ 9161 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */ 9162 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */ 9163 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */ 9164 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */ 9165 9166 if ( IS_EITHER_ENABLED(pVM, EXIT_CRX_READ) 9167 || IS_EITHER_ENABLED(pVM, EXIT_CRX_WRITE)) 9147 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */ 9148 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID); 9149 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */ 9150 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC); 9151 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */ 9152 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT); 9153 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */ 9154 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD); 9155 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT); 9156 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG); 9157 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT); 9158 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC); 9159 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT); 9160 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC); 9161 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */ 9162 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM); 9163 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */ 9164 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL); 9165 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */ 9166 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); 9167 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */ 9168 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); 9169 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */ 9170 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); 9171 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */ 9172 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST); 9173 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */ 9174 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD); 9175 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */ 9176 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME); 9177 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */ 9178 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE); 9179 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */ 9180 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF); 9181 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */ 9182 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON); 9183 9184 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ) 9185 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE)) 9168 9186 { 9169 9187 int rc2 = hmR0VmxSaveGuestCR0(pVCpu, pCtx); … … 9176 9194 pDbgState->fClearCr4Mask = true; 9177 9195 #endif 9178 if (IS_EITHER_ENABLED(pVM, EXIT_CRX_READ))9196 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)) 9179 9197 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT; 9180 if (IS_EITHER_ENABLED(pVM, EXIT_CRX_WRITE))9198 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE)) 9181 9199 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT; 9182 9200 pDbgState->fCpe1Unwanted |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* risky? */ … … 9198 9216 } 9199 9217 } 9200 9201 if ( IS_EITHER_ENABLED(pVM, EXIT_DRX_READ) 9202 || IS_EITHER_ENABLED(pVM, EXIT_DRX_WRITE)) 9218 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX); 9219 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX); 9220 9221 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ) 9222 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE)) 9203 9223 { 9204 9224 /** @todo later, need to fix handler as it assumes this won't usually happen. */ 9205 9225 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX); 9206 9226 } 9207 9208 SET_CPEU_XBM_IF_EITHER_EN(EXIT_RDMSR, VMX_EXIT_RDMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */ 9209 SET_CPEU_XBM_IF_EITHER_EN(EXIT_WRMSR, VMX_EXIT_WRMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); 9210 SET_CPE1_XBM_IF_EITHER_EN(EXIT_MWAIT, VMX_EXIT_MWAIT, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT); /* parnoia */ 9211 SET_CPE1_XBM_IF_EITHER_EN(EXIT_MONITOR, VMX_EXIT_MONITOR, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* parnoia */ 9227 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX); 9228 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX); 9229 9230 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */ 9231 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR); 9232 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); 9233 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR); 9234 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT); /* parnoia */ 9235 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT); 9236 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* parnoia */ 9237 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR); 9212 9238 #if 0 /** @todo too slow, fix handler. */ 9213 SET_CPE1_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);9239 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT); 9214 9240 #endif 9215 9216 if ( IS_EITHER_ENABLED(pVM, EXIT_SGDT) 9217 || IS_EITHER_ENABLED(pVM, EXIT_SIDT) 9218 || IS_EITHER_ENABLED(pVM, EXIT_LGDT) 9219 || IS_EITHER_ENABLED(pVM, EXIT_LIDT)) 9241 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE); 9242 9243 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT) 9244 || IS_EITHER_ENABLED(pVM, INSTR_SIDT) 9245 || IS_EITHER_ENABLED(pVM, INSTR_LGDT) 9246 || IS_EITHER_ENABLED(pVM, INSTR_LIDT)) 9220 9247 { 9221 9248 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT; 9222 9249 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS); 9223 9250 } 9224 9225 if ( IS_EITHER_ENABLED(pVM, EXIT_SLDT) 9226 || IS_EITHER_ENABLED(pVM, EXIT_STR) 9227 || IS_EITHER_ENABLED(pVM, EXIT_LLDT) 9228 || IS_EITHER_ENABLED(pVM, EXIT_LTR)) 9251 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_XDTR_ACCESS); 9252 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_XDTR_ACCESS); 9253 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_XDTR_ACCESS); 9254 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_XDTR_ACCESS); 9255 9256 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT) 9257 || IS_EITHER_ENABLED(pVM, INSTR_STR) 9258 || IS_EITHER_ENABLED(pVM, INSTR_LLDT) 9259 || IS_EITHER_ENABLED(pVM, INSTR_LTR)) 9229 9260 { 9230 9261 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT; 9231 9262 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS); 9232 9263 } 9233 9234 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */ 9235 SET_CPE1_XBM_IF_EITHER_EN(EXIT_RDTSCP, VMX_EXIT_RDTSCP, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT); 9236 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */ 9237 SET_CPE2_XBM_IF_EITHER_EN(EXIT_WBINVD, VMX_EXIT_WBINVD, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT); 9238 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSETBV, VMX_EXIT_XSETBV); /* unconditional */ 9239 SET_CPE2_XBM_IF_EITHER_EN(EXIT_RDRAND, VMX_EXIT_RDRAND, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT); 9240 SET_CPE1_XBM_IF_EITHER_EN(EXIT_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT); 9241 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */ 9242 SET_CPE2_XBM_IF_EITHER_EN(EXIT_RDSEED, VMX_EXIT_RDSEED, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT); 9243 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */ 9244 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */ 9264 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_TR_ACCESS); 9265 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_TR_ACCESS); 9266 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_TR_ACCESS); 9267 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_TR_ACCESS); 9268 9269 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */ 9270 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT); 9271 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT); 9272 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP); 9273 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */ 9274 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID); 9275 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT); 9276 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD); 9277 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */ 9278 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV); 9279 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT); 9280 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND); 9281 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT); 9282 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID); 9283 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */ 9284 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC); 9285 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT); 9286 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED); 9287 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */ 9288 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES); 9289 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */ 9290 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS); 9245 9291 9246 9292 #undef IS_EITHER_ENABLED … … 9301 9347 * where we dispatch dtrace events. 9302 9348 */ 9303 bool fDtrace = false; 9304 DBGFEVENTTYPE enmEvent = DBGFEVENT_END; 9305 uint32_t uEventArg = 0; 9349 bool fDtrace1 = false; 9350 bool fDtrace2 = false; 9351 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END; 9352 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END; 9353 uint32_t uEventArg = 0; 9354 #define SET_EXIT(a_EventSubName) \ 9355 do { \ 9356 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \ 9357 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \ 9358 } while (0) 9306 9359 #define SET_BOTH(a_EventSubName) \ 9307 do { enmEvent = RT_CONCAT(DBGFEVENT_, a_EventSubName); \ 9308 fDtrace = RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)(); \ 9360 do { \ 9361 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \ 9362 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \ 9363 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \ 9364 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \ 9309 9365 } while (0) 9310 9366 switch (uExitReason) … … 9328 9384 uEventArg = pVmxTransient->uExitIntErrorCode; 9329 9385 } 9330 enmEvent = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);9331 switch (enmEvent )9386 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector); 9387 switch (enmEvent1) 9332 9388 { 9333 case DBGFEVENT_XCPT_DE: fDtrace = VBOXVMM_XCPT_DE_ENABLED(); break;9334 case DBGFEVENT_XCPT_DB: fDtrace = VBOXVMM_XCPT_DB_ENABLED(); break;9335 case DBGFEVENT_XCPT_BP: fDtrace = VBOXVMM_XCPT_BP_ENABLED(); break;9336 case DBGFEVENT_XCPT_OF: fDtrace = VBOXVMM_XCPT_OF_ENABLED(); break;9337 case DBGFEVENT_XCPT_BR: fDtrace = VBOXVMM_XCPT_BR_ENABLED(); break;9338 case DBGFEVENT_XCPT_UD: fDtrace = VBOXVMM_XCPT_UD_ENABLED(); break;9339 case DBGFEVENT_XCPT_NM: fDtrace = VBOXVMM_XCPT_NM_ENABLED(); break;9340 case DBGFEVENT_XCPT_DF: fDtrace = VBOXVMM_XCPT_DF_ENABLED(); break;9341 case DBGFEVENT_XCPT_TS: fDtrace = VBOXVMM_XCPT_TS_ENABLED(); break;9342 case DBGFEVENT_XCPT_NP: fDtrace = VBOXVMM_XCPT_NP_ENABLED(); break;9343 case DBGFEVENT_XCPT_SS: fDtrace = VBOXVMM_XCPT_SS_ENABLED(); break;9344 case DBGFEVENT_XCPT_GP: fDtrace = VBOXVMM_XCPT_GP_ENABLED(); break;9345 case DBGFEVENT_XCPT_PF: fDtrace = VBOXVMM_XCPT_PF_ENABLED(); break;9346 case DBGFEVENT_XCPT_MF: fDtrace = VBOXVMM_XCPT_MF_ENABLED(); break;9347 case DBGFEVENT_XCPT_AC: fDtrace = VBOXVMM_XCPT_AC_ENABLED(); break;9348 case DBGFEVENT_XCPT_XF: fDtrace = VBOXVMM_XCPT_XF_ENABLED(); break;9349 case DBGFEVENT_XCPT_VE: fDtrace = VBOXVMM_XCPT_VE_ENABLED(); break;9350 case DBGFEVENT_XCPT_SX: fDtrace = VBOXVMM_XCPT_SX_ENABLED(); break;9351 default: break;9389 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break; 9390 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break; 9391 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break; 9392 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break; 9393 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break; 9394 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break; 9395 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break; 9396 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break; 9397 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break; 9398 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break; 9399 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break; 9400 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break; 9401 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break; 9402 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break; 9403 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break; 9404 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break; 9405 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break; 9406 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break; 9407 default: break; 9352 9408 } 9353 9409 } … … 9358 9414 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT: 9359 9415 uEventArg = idxVector; 9360 enmEvent 9361 fDtrace 9416 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE; 9417 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED(); 9362 9418 break; 9363 9419 } … … 9366 9422 9367 9423 case VMX_EXIT_TRIPLE_FAULT: 9368 enmEvent = DBGFEVENT_TRIPLE_FAULT;9369 //fDtrace = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();9424 enmEvent1 = DBGFEVENT_TRIPLE_FAULT; 9425 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED(); 9370 9426 break; 9371 case VMX_EXIT_TASK_SWITCH: SET_ BOTH(EXIT_TASK_SWITCH); break;9372 case VMX_EXIT_EPT_VIOLATION: SET_ BOTH(EXIT_VMX_EPT_VIOLATION); break;9373 case VMX_EXIT_EPT_MISCONFIG: SET_ BOTH(EXIT_VMX_EPT_MISCONFIG); break;9374 case VMX_EXIT_APIC_ACCESS: SET_ BOTH(EXIT_VMX_VAPIC_ACCESS); break;9375 case VMX_EXIT_APIC_WRITE: SET_ BOTH(EXIT_VMX_VAPIC_WRITE); break;9427 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break; 9428 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break; 9429 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break; 9430 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break; 9431 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break; 9376 9432 9377 9433 /* Instruction specific VM-exits: */ 9378 case VMX_EXIT_CPUID: SET_BOTH( EXIT_CPUID); break;9379 case VMX_EXIT_GETSEC: SET_BOTH( EXIT_GETSEC); break;9380 case VMX_EXIT_HLT: SET_BOTH( EXIT_HALT); break;9381 case VMX_EXIT_INVD: SET_BOTH( EXIT_INVD); break;9382 case VMX_EXIT_INVLPG: SET_BOTH( EXIT_INVLPG); break;9383 case VMX_EXIT_RDPMC: SET_BOTH( EXIT_RDPMC); break;9384 case VMX_EXIT_RDTSC: SET_BOTH( EXIT_RDTSC); break;9385 case VMX_EXIT_RSM: SET_BOTH( EXIT_RSM); break;9386 case VMX_EXIT_VMCALL: SET_BOTH( EXIT_VMM_CALL); break;9387 case VMX_EXIT_VMCLEAR: SET_BOTH( EXIT_VMX_VMCLEAR); break;9388 case VMX_EXIT_VMLAUNCH: SET_BOTH( EXIT_VMX_VMLAUNCH); break;9389 case VMX_EXIT_VMPTRLD: SET_BOTH( EXIT_VMX_VMPTRLD); break;9390 case VMX_EXIT_VMPTRST: SET_BOTH( EXIT_VMX_VMPTRST); break;9391 case VMX_EXIT_VMREAD: SET_BOTH( EXIT_VMX_VMREAD); break;9392 case VMX_EXIT_VMRESUME: SET_BOTH( EXIT_VMX_VMRESUME); break;9393 case VMX_EXIT_VMWRITE: SET_BOTH( EXIT_VMX_VMWRITE); break;9394 case VMX_EXIT_VMXOFF: SET_BOTH( EXIT_VMX_VMXOFF); break;9395 case VMX_EXIT_VMXON: SET_BOTH( EXIT_VMX_VMXON); break;9434 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break; 9435 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break; 9436 case VMX_EXIT_HLT: SET_BOTH(HALT); break; 9437 case VMX_EXIT_INVD: SET_BOTH(INVD); break; 9438 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break; 9439 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break; 9440 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break; 9441 case VMX_EXIT_RSM: SET_BOTH(RSM); break; 9442 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break; 9443 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break; 9444 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break; 9445 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break; 9446 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break; 9447 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break; 9448 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break; 9449 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break; 9450 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break; 9451 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break; 9396 9452 case VMX_EXIT_MOV_CRX: 9397 9453 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient); … … 9400 9456 if ( VMX_EXIT_QUALIFICATION_CRX_ACCESS(pVmxTransient->uExitQualification) 9401 9457 == VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ) 9402 SET_BOTH( EXIT_CRX_READ);9458 SET_BOTH(CRX_READ); 9403 9459 else 9404 SET_BOTH( EXIT_CRX_WRITE);9460 SET_BOTH(CRX_WRITE); 9405 9461 uEventArg = VMX_EXIT_QUALIFICATION_CRX_REGISTER(pVmxTransient->uExitQualification); 9406 9462 break; … … 9409 9465 if ( VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) 9410 9466 == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ) 9411 SET_BOTH( EXIT_DRX_READ);9467 SET_BOTH(DRX_READ); 9412 9468 else 9413 SET_BOTH( EXIT_DRX_WRITE);9469 SET_BOTH(DRX_WRITE); 9414 9470 uEventArg = VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification); 9415 9471 break; 9416 case VMX_EXIT_RDMSR: SET_BOTH( EXIT_RDMSR); break;9417 case VMX_EXIT_WRMSR: SET_BOTH( EXIT_WRMSR); break;9418 case VMX_EXIT_MWAIT: SET_BOTH( EXIT_MWAIT); break;9419 case VMX_EXIT_MONITOR: SET_BOTH( EXIT_MONITOR); break;9420 case VMX_EXIT_PAUSE: SET_BOTH( EXIT_PAUSE); break;9472 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break; 9473 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break; 9474 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break; 9475 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break; 9476 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break; 9421 9477 case VMX_EXIT_XDTR_ACCESS: 9422 9478 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient); 9423 9479 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_XDTR_INSINFO_INSTR_ID)) 9424 9480 { 9425 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH( EXIT_SGDT); break;9426 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH( EXIT_SIDT); break;9427 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH( EXIT_LGDT); break;9428 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH( EXIT_LIDT); break;9481 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break; 9482 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break; 9483 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break; 9484 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break; 9429 9485 } 9430 9486 break; … … 9434 9490 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_YYTR_INSINFO_INSTR_ID)) 9435 9491 { 9436 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH( EXIT_SLDT); break;9437 case VMX_YYTR_INSINFO_II_STR: SET_BOTH( EXIT_STR); break;9438 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH( EXIT_LLDT); break;9439 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH( EXIT_LTR); break;9492 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break; 9493 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break; 9494 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break; 9495 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break; 9440 9496 } 9441 9497 break; 9442 9498 9443 case VMX_EXIT_INVEPT: SET_BOTH( EXIT_VMX_INVEPT); break;9444 case VMX_EXIT_RDTSCP: SET_BOTH( EXIT_RDTSCP); break;9445 case VMX_EXIT_INVVPID: SET_BOTH( EXIT_VMX_INVVPID); break;9446 case VMX_EXIT_WBINVD: SET_BOTH( EXIT_WBINVD); break;9447 case VMX_EXIT_XSETBV: SET_BOTH( EXIT_XSETBV); break;9448 case VMX_EXIT_RDRAND: SET_BOTH( EXIT_RDRAND); break;9449 case VMX_EXIT_INVPCID: SET_BOTH( EXIT_VMX_INVPCID); break;9450 case VMX_EXIT_VMFUNC: SET_BOTH( EXIT_VMX_VMFUNC); break;9451 case VMX_EXIT_RDSEED: SET_BOTH( EXIT_RDSEED); break;9452 case VMX_EXIT_XSAVES: SET_BOTH( EXIT_XSAVES); break;9453 case VMX_EXIT_XRSTORS: SET_BOTH( EXIT_XRSTORS); break;9499 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break; 9500 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break; 9501 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break; 9502 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break; 9503 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break; 9504 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break; 9505 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break; 9506 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break; 9507 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break; 9508 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break; 9509 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break; 9454 9510 9455 9511 /* Events that aren't relevant at this point. */ … … 9477 9533 } 9478 9534 #undef SET_BOTH 9535 #undef SET_EXIT 9479 9536 9480 9537 /* … … 9484 9541 * we use enmEvent since the probes are a subset of what DBGF does. 9485 9542 */ 9486 if (fDtrace )9543 if (fDtrace1 || fDtrace2) 9487 9544 { 9488 9545 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient); 9489 9546 hmR0VmxSaveGuestState(pVCpu, pMixedCtx); 9490 switch (enmEvent )9547 switch (enmEvent1) 9491 9548 { 9492 9549 /** @todo consider which extra parameters would be helpful for each probe. */ 9550 case DBGFEVENT_END: break; 9493 9551 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pMixedCtx); break; 9494 9552 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pMixedCtx, pMixedCtx->dr[6]); break; … … 9510 9568 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pMixedCtx, uEventArg); break; 9511 9569 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break; 9570 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break; 9571 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pMixedCtx); break; 9572 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pMixedCtx); break; 9573 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pMixedCtx); break; 9574 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pMixedCtx); break; 9575 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pMixedCtx); break; 9576 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pMixedCtx); break; 9577 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pMixedCtx); break; 9578 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break; 9579 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break; 9580 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break; 9581 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break; 9582 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break; 9583 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx, 9584 RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break; 9585 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pMixedCtx); break; 9586 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pMixedCtx); break; 9587 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pMixedCtx); break; 9588 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pMixedCtx); break; 9589 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pMixedCtx); break; 9590 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pMixedCtx); break; 9591 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pMixedCtx); break; 9592 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pMixedCtx); break; 9593 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pMixedCtx); break; 9594 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pMixedCtx); break; 9595 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pMixedCtx); break; 9596 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pMixedCtx); break; 9597 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pMixedCtx); break; 9598 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pMixedCtx); break; 9599 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pMixedCtx); break; 9600 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pMixedCtx); break; 9601 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pMixedCtx); break; 9602 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pMixedCtx); break; 9603 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pMixedCtx); break; 9604 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pMixedCtx); break; 9605 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pMixedCtx); break; 9606 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pMixedCtx); break; 9607 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pMixedCtx); break; 9608 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pMixedCtx); break; 9609 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pMixedCtx); break; 9610 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pMixedCtx); break; 9611 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pMixedCtx); break; 9612 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pMixedCtx); break; 9613 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pMixedCtx); break; 9614 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pMixedCtx); break; 9615 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pMixedCtx); break; 9616 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pMixedCtx); break; 9617 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break; 9618 } 9619 switch (enmEvent2) 9620 { 9621 /** @todo consider which extra parameters would be helpful for each probe. */ 9622 case DBGFEVENT_END: break; 9512 9623 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pMixedCtx); break; 9513 9624 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break; … … 9562 9673 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pMixedCtx); break; 9563 9674 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pMixedCtx); break; 9564 default: AssertMsgFailed(("enmEvent=%d uExitReason=%d\n", enmEvent, uExitReason)); break;9675 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break; 9565 9676 } 9566 9677 } … … 9571 9682 * 9572 9683 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap. 9684 * Note! If we have to events, we prioritize the first, i.e. the instruction 9685 * one, in order to avoid event nesting. 9573 9686 */ 9574 if ( enmEvent != DBGFEVENT_END 9575 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent)) 9576 { 9577 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent, uEventArg); 9687 if ( enmEvent1 != DBGFEVENT_END 9688 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1)) 9689 { 9690 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent1, uEventArg); 9691 if (rcStrict != VINF_SUCCESS) 9692 return rcStrict; 9693 } 9694 else if ( enmEvent2 != DBGFEVENT_END 9695 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2)) 9696 { 9697 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent2, uEventArg); 9578 9698 if (rcStrict != VINF_SUCCESS) 9579 9699 return rcStrict; … … 9906 10026 Since the variables are in an array and the probes are next to one 9907 10027 another (more or less), we have good locality. So, better read 9908 four-five cache lines ever time and only have one conditional, than9909 70+ conditionals, right? */10028 eight-nine cache lines ever time and only have one conditional, than 10029 128+ conditionals, right? */ 9910 10030 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */ 9911 10031 | VBOXVMM_XCPT_DE_ENABLED_RAW() … … 9929 10049 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW() 9930 10050 | VBOXVMM_INT_HARDWARE_ENABLED_RAW() 9931 | VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW() 10051 ) != 0 10052 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW() 10053 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW() 10054 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW() 10055 | VBOXVMM_INSTR_CPUID_ENABLED_RAW() 10056 | VBOXVMM_INSTR_INVD_ENABLED_RAW() 10057 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW() 10058 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW() 10059 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW() 10060 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW() 10061 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW() 10062 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW() 10063 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW() 10064 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW() 10065 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW() 10066 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW() 10067 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW() 10068 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW() 10069 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW() 10070 | VBOXVMM_INSTR_SIDT_ENABLED_RAW() 10071 | VBOXVMM_INSTR_LIDT_ENABLED_RAW() 10072 | VBOXVMM_INSTR_SGDT_ENABLED_RAW() 10073 | VBOXVMM_INSTR_LGDT_ENABLED_RAW() 10074 | VBOXVMM_INSTR_SLDT_ENABLED_RAW() 10075 | VBOXVMM_INSTR_LLDT_ENABLED_RAW() 10076 | VBOXVMM_INSTR_STR_ENABLED_RAW() 10077 | VBOXVMM_INSTR_LTR_ENABLED_RAW() 10078 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW() 10079 | VBOXVMM_INSTR_RSM_ENABLED_RAW() 10080 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW() 10081 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW() 10082 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW() 10083 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW() 10084 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW() 10085 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW() 10086 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW() 10087 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW() 10088 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW() 10089 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW() 10090 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW() 10091 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW() 10092 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW() 10093 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW() 10094 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW() 10095 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW() 10096 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW() 10097 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW() 10098 ) != 0 10099 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW() 9932 10100 | VBOXVMM_EXIT_HALT_ENABLED_RAW() 9933 10101 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
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