VirtualBox

Changeset 61776 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Jun 20, 2016 11:25:06 PM (9 years ago)
Author:
vboxsync
Message:

CPUM,APIC: Per-CPU APIC CPUID feature bit and MSR_IA32_APICBASE GP mask adjustments.

  • Changed the PDMAPICHLPR3::pfnChangeFeature to pfnSetFeatureLevel, removing the RC and R0 versions.
  • Only use pfnSetFeatureLevel from the APIC constructor to communicate to CPUM the max APIC feature level, not to globally flip CPUID[1].EDX[9].
  • Renamed APIC enmOriginalMode to enmMaxMode, changing the type of it and the corresponding config values to PDMAPICMODE. This makes the above simpler and eliminates two conversion functions. It also makes APICMODE private to the APIC again.
  • Introduced CPUMSetGuestCpuIdPerCpuApicFeature for the per-CPU APIC feature bit management.
  • Introduced CPUMCPUIDLEAF_F_CONTAINS_APIC which works same as CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE and CPUMCPUIDLEAF_F_CONTAINS_APIC_ID. Updated existing CPU profiles with this.
  • Made the patch manager helper function actually handle CPUMCPUIDLEAF_F_CONTAINS_APIC and CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE (the latter previously relied on CPUMSetGuestCpuIdFeature/CPUMClearGuestCpuIdFeature from CPUMSetGuestCR4).
  • Pushed CPUMSetGuestCpuIdFeature, CPUMGetGuestCpuIdFeature and CPUMClearGuestCpuIdFeature down to ring-3 only (now CPUMR3*). The latter two function are deprecated.
  • Added call to CPUMSetGuestCpuIdPerCpuApicFeature from load function just in case the APIC is disabled by the guest at the time of saving.
  • CPUMSetGuestCpuIdFeature ensures we've got a MSR_IA32_APICBASE register when enabling the APIC.
  • CPUMSetGuestCpuIdFeature adjust the MSR_IA32_APICBASE GP mask when enabling x2APIC so setting MSR_IA32_APICBASE_EXTD does not trap.
Location:
trunk/src/VBox/VMM/VMMR3
Files:
24 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r61769 r61776  
    262262    PAPICCPU pApicCpu     = VMCPU_TO_APICCPU(pVCpu);
    263263    PAPIC    pApic        = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    264     uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;;
     264    uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
    265265    if (pVCpu->idCpu == 0)
    266266        uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
    267267
    268     /* If the VM was configured with disabled mode, don't enable xAPIC mode. */
    269     if (pApic->enmOriginalMode != APICMODE_DISABLED)
     268    /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
     269    if (pApic->enmMaxMode != PDMAPICMODE_NONE)
    270270    {
    271271        uApicBaseMsr |= MSR_IA32_APICBASE_EN;
    … …  
    276276         * See Intel spec. 10.12.5.1 "x2APIC States".
    277277         */
    278         /** @todo CPUID bits needs to be done on a per-VCPU basis! */
    279         if (!CPUMGetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC))
    280         {
     278        if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
    281279            LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
    282             CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
    283         }
    284280    }
    285281
    … …  
    773769
    774770
    775 /**
    776  * Converts legacy PDMAPICMODE to the new APICMODE enum.
    777  *
    778  * @returns The new APIC mode.
    779  * @param   enmLegacyMode       The legacy mode to convert.
    780  */
    781 static APICMODE apicR3ConvertFromLegacyApicMode(PDMAPICMODE enmLegacyMode)
    782 {
    783     switch (enmLegacyMode)
    784     {
    785         case PDMAPICMODE_NONE:      return APICMODE_DISABLED;
    786         case PDMAPICMODE_APIC:      return APICMODE_XAPIC;
    787         case PDMAPICMODE_X2APIC:    return APICMODE_X2APIC;
    788         case PDMAPICMODE_INVALID:   return APICMODE_INVALID;
    789         default:                    break;
    790     }
    791     return (APICMODE)enmLegacyMode;
    792 }
    793 
    794 
    795 /**
    796  * Converts the new APICMODE enum to the legacy PDMAPICMODE enum.
    797  *
    798  * @returns The legacy APIC mode.
    799  * @param   enmMode       The APIC mode to convert.
    800  */
    801 static PDMAPICMODE apicR3ConvertToLegacyApicMode(APICMODE enmMode)
    802 {
    803     switch (enmMode)
    804     {
    805         case APICMODE_DISABLED:  return PDMAPICMODE_NONE;
    806         case APICMODE_XAPIC:     return PDMAPICMODE_APIC;
    807         case APICMODE_X2APIC:    return PDMAPICMODE_X2APIC;
    808         case APICMODE_INVALID:   return PDMAPICMODE_INVALID;
    809         default:                 break;
    810     }
    811     return (PDMAPICMODE)enmMode;
    812 }
    813 
    814 
    815771#ifdef APIC_FUZZY_SSM_COMPAT_TEST
     772
    816773/**
    817774 * Reads a 32-bit register at a specified offset.
    … …  
    923880    }
    924881}
     882
    925883#endif  /* APIC_FUZZY_SSM_COMPAT_TEST */
    926 
    927884
    928885/**
    … …  
    938895    SSMR3PutU32(pSSM,  pVM->cCpus);
    939896    SSMR3PutBool(pSSM, pApic->fIoApicPresent);
    940     return SSMR3PutU32(pSSM, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode));
     897    return SSMR3PutU32(pSSM, pApic->enmMaxMode);
    941898}
    942899
    … …  
    968925                                fIoApicPresent, pApic->fIoApicPresent);
    969926
    970     /* Load and verify configured APIC mode. */
    971     uint32_t uLegacyApicMode;
    972     rc = SSMR3GetU32(pSSM, &uLegacyApicMode);
     927    /* Load and verify configured max APIC mode. */
     928    uint32_t uSavedMaxApicMode;
     929    rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
    973930    AssertRCReturn(rc, rc);
    974     APICMODE const enmApicMode = apicR3ConvertFromLegacyApicMode((PDMAPICMODE)uLegacyApicMode);
    975     if (enmApicMode != pApic->enmOriginalMode)
    976         return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u (%u) config=%u (%u)"),
    977                                 uLegacyApicMode, enmApicMode, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode),
    978                                 pApic->enmOriginalMode);
     931    if (uSavedMaxApicMode != pApic->enmMaxMode)
     932        return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
     933                                uSavedMaxApicMode, pApic->enmMaxMode);
    979934    return VINF_SUCCESS;
    980935}
    … …  
    12051160        PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    12061161
     1162        /** @todo r=bird: This is reckless saved state version handling that will break as soon as APIC_SAVED_STATE_VERSION
     1163         * is bumped the next time.  You should test: uVersion > APIC_SAVED_STATE_VERSION_VBOX_50
     1164         * or alternativly always name the new version and do the test: uVersion >= APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 */
    12071165        if (   uVersion == APIC_SAVED_STATE_VERSION
    12081166            || uVersion == APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
    … …  
    12431201            AssertRCReturn(rc, rc);
    12441202        }
     1203
     1204        /*
     1205         * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
     1206         */
     1207        rc = SSMR3HandleGetStatus(pSSM);
     1208        AssertRCReturn(rc, rc);
     1209        CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
    12451210
    12461211#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
    … …  
    16291594
    16301595    /*
     1596     * Init the data.
     1597     */
     1598    pApicDev->pDevInsR3 = pDevIns;
     1599    pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     1600    pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     1601
     1602    pApic->pApicDevR0   = PDMINS_2_DATA_R0PTR(pDevIns);
     1603    pApic->pApicDevR3   = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
     1604    pApic->pApicDevRC   = PDMINS_2_DATA_RCPTR(pDevIns);
     1605
     1606    /*
    16311607     * Validate APIC settings.
    16321608     */
    … …  
    16461622    AssertLogRelRCReturn(rc, rc);
    16471623
    1648     uint8_t uOriginalMode;
    1649     rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
     1624    /* Max APIC feature level. */
     1625    uint8_t uMaxMode;
     1626    rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
    16501627    AssertLogRelRCReturn(rc, rc);
    1651 
    1652     /* Validate APIC modes. */
    1653     APICMODE const enmOriginalMode = (APICMODE)uOriginalMode;
    1654     switch (enmOriginalMode)
    1655     {
    1656         case APICMODE_DISABLED:
    1657         {
     1628    switch ((PDMAPICMODE)uMaxMode)
     1629    {
     1630        case PDMAPICMODE_NONE:
     1631#if 1
    16581632            /** @todo permanently disabling the APIC won't really work (needs
    16591633             *        fixing in HM, CPUM, PDM and possibly other places). See
    16601634             *        @bugref{8353}. */
    1661 #if 0
    1662             pApic->enmOriginalMode = enmOriginalMode;
    1663             CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
    1664             CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
     1635            return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'none' is not supported yet.");
     1636#endif
     1637        case PDMAPICMODE_APIC:
     1638        case PDMAPICMODE_X2APIC:
    16651639            break;
    1666 #else
    1667             return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'disabled' is not supported yet.");
    1668 #endif
    1669         }
    1670 
    1671         case APICMODE_X2APIC:
    1672         {
    1673             pApic->enmOriginalMode = enmOriginalMode;
    1674             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
    1675 
    1676             /* Insert the MSR range of the x2APIC. */
    1677             rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
    1678             AssertLogRelRCReturn(rc, rc);
    1679             break;
    1680         }
    1681 
    1682         case APICMODE_XAPIC:
    1683             pApic->enmOriginalMode = enmOriginalMode;
    1684             /* The CPUID bit will be updated in apicR3ResetBaseMsr(). */
    1685             break;
    1686 
    16871640        default:
    1688             return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);
    1689     }
    1690 
    1691     /*
    1692      * Initialize the APIC state.
    1693      */
    1694     pApicDev->pDevInsR3 = pDevIns;
    1695     pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    1696     pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    1697 
    1698     pApic->pApicDevR0   = PDMINS_2_DATA_R0PTR(pDevIns);
    1699     pApic->pApicDevR3   = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
    1700     pApic->pApicDevRC   = PDMINS_2_DATA_RCPTR(pDevIns);
    1701 
    1702     rc = apicR3InitState(pVM);
    1703     AssertRCReturn(rc, rc);
     1641            return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
     1642    }
     1643    pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
    17041644
    17051645    /*
    … …  
    17101650
    17111651    /*
    1712      * Register the APIC.
     1652     * Register the APIC with PDM.
    17131653     */
    17141654    PDMAPICREG ApicReg;
    … …  
    17581698    AssertLogRelRCReturn(rc, rc);
    17591699    pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
     1700
     1701    /*
     1702     * Initialize the APIC state.
     1703     */
     1704    /* First insert the MSR range of the x2APIC if enabled. */
     1705    if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
     1706    {
     1707        rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
     1708        AssertLogRelRCReturn(rc, rc);
     1709    }
     1710
     1711    /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
     1712    pApicDev->pApicHlpR3->pfnSetFeatureLevel(pDevIns, pApic->enmMaxMode);
     1713
     1714    /* Initialize the state. */
     1715    rc = apicR3InitState(pVM);
     1716    AssertRCReturn(rc, rc);
    17601717
    17611718    /*

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r60996 r61776  
    11881188                    fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
    11891189
     1190                /* The APIC bit is per-VCpu and needs flagging. */
     1191                if (uLeaf == 1)
     1192                    fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
     1193                else if (   uLeaf == UINT32_C(0x80000001)
     1194                         && (   (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
     1195                             || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
     1196                    fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC;
    11901197
    11911198                /* Check three times here to reduce the chance of CPU migration
    … …  
    31443151     * Clear them all as we don't currently implement extended CPU state.
    31453152     */
    3146     /* Figure out the supported XCR0/XSS mask component. */
     3153    /* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
    31473154    uint64_t fGuestXcr0Mask = 0;
    31483155    pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
    … …  
    31563163            fGuestXcr0Mask |= XSAVE_C_ZMM_16HI | XSAVE_C_ZMM_HI256 | XSAVE_C_OPMASK;
    31573164        fGuestXcr0Mask &= pCpum->fXStateHostMask;
     3165
     3166        pStdFeatureLeaf->fFlags |= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
    31583167    }
    31593168    pStdFeatureLeaf = NULL;
    … …  
    39573966
    39583967    /*
     3968     * Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
     3969     * on construction and manage everything from here on.
     3970     */
     3971    for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
     3972        pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
     3973
     3974    /*
    39593975     * Read the configuration.
    39603976     */
    … …  
    40724088        AssertRCReturn(rc, rc);
    40734089        if (fEnable)
    4074             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
     4090            CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
    40754091
    40764092        /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
    … …  
    40784094        AssertRCReturn(rc, rc);
    40794095        if (fEnable)
    4080             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
     4096            CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
    40814097
    40824098        /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
    … …  
    40844100        AssertRCReturn(rc, rc);
    40854101        if (fEnable)
    4086             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
     4102            CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
    40874103
    40884104        return VINF_SUCCESS;
    … …  
    40974113    pCpum->GuestInfo.paMsrRangesR3 = NULL;
    40984114    return rc;
     4115}
     4116
     4117
     4118/**
     4119 * Sets a CPUID feature bit during VM initialization.
     4120 *
     4121 * Since the CPUID feature bits are generally related to CPU features, other
     4122 * CPUM configuration like MSRs can also be modified by calls to this API.
     4123 *
     4124 * @param   pVM             The cross context VM structure.
     4125 * @param   enmFeature      The feature to set.
     4126 */
     4127VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
     4128{
     4129    PCPUMCPUIDLEAF pLeaf;
     4130    PCPUMMSRRANGE  pMsrRange;
     4131
     4132    switch (enmFeature)
     4133    {
     4134        /*
     4135         * Set the APIC bit in both feature masks.
     4136         */
     4137        case CPUMCPUIDFEATURE_APIC:
     4138            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4139            if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
     4140                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_APIC;
     4141
     4142            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4143            if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
     4144                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
     4145
     4146            pVM->cpum.s.GuestFeatures.fApic = 1;
     4147
     4148            /* Make sure we've got the APICBASE MSR present. */
     4149            pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
     4150            if (!pMsrRange)
     4151            {
     4152                static CPUMMSRRANGE const s_ApicBase =
     4153                {
     4154                    /*.uFirst =*/ MSR_IA32_APICBASE, /*.uLast =*/ MSR_IA32_APICBASE,
     4155                    /*.enmRdFn =*/ kCpumMsrRdFn_Ia32ApicBase, /*.enmWrFn =*/ kCpumMsrWrFn_Ia32ApicBase,
     4156                    /*.offCpumCpu =*/ UINT16_MAX, /*.fReserved =*/ 0, /*.uValue =*/ 0, /*.fWrIgnMask =*/ 0, /*.fWrGpMask =*/ 0,
     4157                    /*.szName = */ "IA32_APIC_BASE"
     4158                };
     4159                int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
     4160                AssertLogRelRC(rc);
     4161RTLogPrintf("XXXX: CPUMCPUIDFEATURE_APIC !!!\n");
     4162            }
     4163else RTLogPrintf("XXXX: CPUMCPUIDFEATURE_APIC Gp=%RX64 Ign=%RX64\n", pMsrRange->fWrGpMask, pMsrRange->fWrIgnMask);
     4164
     4165            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
     4166            break;
     4167
     4168        /*
     4169         * Set the x2APIC bit in the standard feature mask.
     4170         * Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
     4171         */
     4172        case CPUMCPUIDFEATURE_X2APIC:
     4173            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4174            if (pLeaf)
     4175                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_X2APIC;
     4176            pVM->cpum.s.GuestFeatures.fX2Apic = 1;
     4177
     4178            /* Make sure the MSR doesn't GP or ignore the EXTD bit. */
     4179            pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
     4180            if (pMsrRange)
     4181            {
     4182                pMsrRange->fWrGpMask  &= ~MSR_IA32_APICBASE_EXTD;
     4183                pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
     4184            }
     4185
     4186            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
     4187            break;
     4188
     4189        /*
     4190         * Set the sysenter/sysexit bit in the standard feature mask.
     4191         * Assumes the caller knows what it's doing! (host must support these)
     4192         */
     4193        case CPUMCPUIDFEATURE_SEP:
     4194            if (!pVM->cpum.s.HostFeatures.fSysEnter)
     4195            {
     4196                AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
     4197                return;
     4198            }
     4199
     4200            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4201            if (pLeaf)
     4202                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_SEP;
     4203            pVM->cpum.s.GuestFeatures.fSysEnter = 1;
     4204            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
     4205            break;
     4206
     4207        /*
     4208         * Set the syscall/sysret bit in the extended feature mask.
     4209         * Assumes the caller knows what it's doing! (host must support these)
     4210         */
     4211        case CPUMCPUIDFEATURE_SYSCALL:
     4212            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4213            if (   !pLeaf
     4214                || !pVM->cpum.s.HostFeatures.fSysCall)
     4215            {
     4216#if HC_ARCH_BITS == 32
     4217                /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
     4218                   mode by Intel, even when the cpu is capable of doing so in
     4219                   64-bit mode.  Long mode requires syscall support. */
     4220                if (!pVM->cpum.s.HostFeatures.fLongMode)
     4221#endif
     4222                {
     4223                    LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
     4224                    return;
     4225                }
     4226            }
     4227
     4228            /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
     4229            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
     4230            pVM->cpum.s.GuestFeatures.fSysCall = 1;
     4231            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
     4232            break;
     4233
     4234        /*
     4235         * Set the PAE bit in both feature masks.
     4236         * Assumes the caller knows what it's doing! (host must support these)
     4237         */
     4238        case CPUMCPUIDFEATURE_PAE:
     4239            if (!pVM->cpum.s.HostFeatures.fPae)
     4240            {
     4241                LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
     4242                return;
     4243            }
     4244
     4245            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4246            if (pLeaf)
     4247                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAE;
     4248
     4249            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4250            if (    pLeaf
     4251                &&  pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
     4252                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
     4253
     4254            pVM->cpum.s.GuestFeatures.fPae = 1;
     4255            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
     4256            break;
     4257
     4258        /*
     4259         * Set the LONG MODE bit in the extended feature mask.
     4260         * Assumes the caller knows what it's doing! (host must support these)
     4261         */
     4262        case CPUMCPUIDFEATURE_LONG_MODE:
     4263            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4264            if (   !pLeaf
     4265                || !pVM->cpum.s.HostFeatures.fLongMode)
     4266            {
     4267                LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
     4268                return;
     4269            }
     4270
     4271            /* Valid for both Intel and AMD. */
     4272            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
     4273            pVM->cpum.s.GuestFeatures.fLongMode = 1;
     4274            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
     4275            break;
     4276
     4277        /*
     4278         * Set the NX/XD bit in the extended feature mask.
     4279         * Assumes the caller knows what it's doing! (host must support these)
     4280         */
     4281        case CPUMCPUIDFEATURE_NX:
     4282            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4283            if (   !pLeaf
     4284                || !pVM->cpum.s.HostFeatures.fNoExecute)
     4285            {
     4286                LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
     4287                return;
     4288            }
     4289
     4290            /* Valid for both Intel and AMD. */
     4291            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_NX;
     4292            pVM->cpum.s.GuestFeatures.fNoExecute = 1;
     4293            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
     4294            break;
     4295
     4296
     4297        /*
     4298         * Set the LAHF/SAHF support in 64-bit mode.
     4299         * Assumes the caller knows what it's doing! (host must support this)
     4300         */
     4301        case CPUMCPUIDFEATURE_LAHF:
     4302            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4303            if (   !pLeaf
     4304                || !pVM->cpum.s.HostFeatures.fLahfSahf)
     4305            {
     4306                LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
     4307                return;
     4308            }
     4309
     4310            /* Valid for both Intel and AMD. */
     4311            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
     4312            pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
     4313            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
     4314            break;
     4315
     4316        /*
     4317         * Set the page attribute table bit.  This is alternative page level
     4318         * cache control that doesn't much matter when everything is
     4319         * virtualized, though it may when passing thru device memory.
     4320         */
     4321        case CPUMCPUIDFEATURE_PAT:
     4322            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4323            if (pLeaf)
     4324                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx |= X86_CPUID_FEATURE_EDX_PAT;
     4325
     4326            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4327            if (   pLeaf
     4328                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
     4329                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
     4330
     4331            pVM->cpum.s.GuestFeatures.fPat = 1;
     4332            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
     4333            break;
     4334
     4335        /*
     4336         * Set the RDTSCP support bit.
     4337         * Assumes the caller knows what it's doing! (host must support this)
     4338         */
     4339        case CPUMCPUIDFEATURE_RDTSCP:
     4340            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4341            if (   !pLeaf
     4342                || !pVM->cpum.s.HostFeatures.fRdTscP
     4343                || pVM->cpum.s.u8PortableCpuIdLevel > 0)
     4344            {
     4345                if (!pVM->cpum.s.u8PortableCpuIdLevel)
     4346                    LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
     4347                return;
     4348            }
     4349
     4350            /* Valid for both Intel and AMD. */
     4351            pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
     4352            pVM->cpum.s.HostFeatures.fRdTscP = 1;
     4353            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
     4354            break;
     4355
     4356       /*
     4357        * Set the Hypervisor Present bit in the standard feature mask.
     4358        */
     4359        case CPUMCPUIDFEATURE_HVP:
     4360            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4361            if (pLeaf)
     4362                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx |= X86_CPUID_FEATURE_ECX_HVP;
     4363            pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
     4364            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
     4365            break;
     4366
     4367        /*
     4368         * Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
     4369         * This currently includes the Present bit and MWAITBREAK bit as well.
     4370         */
     4371        case CPUMCPUIDFEATURE_MWAIT_EXTS:
     4372            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
     4373            if (   !pLeaf
     4374                || !pVM->cpum.s.HostFeatures.fMWaitExtensions)
     4375            {
     4376                LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
     4377                return;
     4378            }
     4379
     4380            /* Valid for both Intel and AMD. */
     4381            pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx |= X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
     4382            pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
     4383            LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
     4384            break;
     4385
     4386        default:
     4387            AssertMsgFailed(("enmFeature=%d\n", enmFeature));
     4388            break;
     4389    }
     4390
     4391    /** @todo can probably kill this as this API is now init time only... */
     4392    for (VMCPUID i = 0; i < pVM->cCpus; i++)
     4393    {
     4394        PVMCPU pVCpu = &pVM->aCpus[i];
     4395        pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
     4396    }
     4397}
     4398
     4399
     4400/**
     4401 * Queries a CPUID feature bit.
     4402 *
     4403 * @returns boolean for feature presence
     4404 * @param   pVM             The cross context VM structure.
     4405 * @param   enmFeature      The feature to query.
     4406 * @deprecated Use the cpum.ro.GuestFeatures directly instead.
     4407 */
     4408VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
     4409{
     4410    switch (enmFeature)
     4411    {
     4412        case CPUMCPUIDFEATURE_APIC:         return pVM->cpum.s.GuestFeatures.fApic;
     4413        case CPUMCPUIDFEATURE_X2APIC:       return pVM->cpum.s.GuestFeatures.fX2Apic;
     4414        case CPUMCPUIDFEATURE_SYSCALL:      return pVM->cpum.s.GuestFeatures.fSysCall;
     4415        case CPUMCPUIDFEATURE_SEP:          return pVM->cpum.s.GuestFeatures.fSysEnter;
     4416        case CPUMCPUIDFEATURE_PAE:          return pVM->cpum.s.GuestFeatures.fPae;
     4417        case CPUMCPUIDFEATURE_NX:           return pVM->cpum.s.GuestFeatures.fNoExecute;
     4418        case CPUMCPUIDFEATURE_LAHF:         return pVM->cpum.s.GuestFeatures.fLahfSahf;
     4419        case CPUMCPUIDFEATURE_LONG_MODE:    return pVM->cpum.s.GuestFeatures.fLongMode;
     4420        case CPUMCPUIDFEATURE_PAT:          return pVM->cpum.s.GuestFeatures.fPat;
     4421        case CPUMCPUIDFEATURE_RDTSCP:       return pVM->cpum.s.GuestFeatures.fRdTscP;
     4422        case CPUMCPUIDFEATURE_HVP:          return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
     4423        case CPUMCPUIDFEATURE_MWAIT_EXTS:   return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
     4424
     4425        case CPUMCPUIDFEATURE_INVALID:
     4426        case CPUMCPUIDFEATURE_32BIT_HACK:
     4427            break;
     4428    }
     4429    AssertFailed();
     4430    return false;
     4431}
     4432
     4433
     4434/**
     4435 * Clears a CPUID feature bit.
     4436 *
     4437 * @param   pVM             The cross context VM structure.
     4438 * @param   enmFeature      The feature to clear.
     4439 *
     4440 * @deprecated Probably better to default the feature to disabled and only allow
     4441 *             setting (enabling) it during construction.
     4442 */
     4443VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
     4444{
     4445    PCPUMCPUIDLEAF pLeaf;
     4446    switch (enmFeature)
     4447    {
     4448        case CPUMCPUIDFEATURE_APIC:
     4449            Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
     4450            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4451            if (pLeaf)
     4452                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
     4453
     4454            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4455            if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
     4456                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
     4457
     4458            pVM->cpum.s.GuestFeatures.fApic = 0;
     4459            Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
     4460            break;
     4461
     4462        case CPUMCPUIDFEATURE_X2APIC:
     4463            Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
     4464            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4465            if (pLeaf)
     4466                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
     4467            pVM->cpum.s.GuestFeatures.fX2Apic = 0;
     4468            Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
     4469            break;
     4470
     4471        case CPUMCPUIDFEATURE_PAE:
     4472            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4473            if (pLeaf)
     4474                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
     4475
     4476            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4477            if (   pLeaf
     4478                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
     4479                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
     4480
     4481            pVM->cpum.s.GuestFeatures.fPae = 0;
     4482            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
     4483            break;
     4484
     4485        case CPUMCPUIDFEATURE_PAT:
     4486            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4487            if (pLeaf)
     4488                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
     4489
     4490            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4491            if (   pLeaf
     4492                && pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
     4493                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
     4494
     4495            pVM->cpum.s.GuestFeatures.fPat = 0;
     4496            Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
     4497            break;
     4498
     4499        case CPUMCPUIDFEATURE_LONG_MODE:
     4500            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4501            if (pLeaf)
     4502                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
     4503            pVM->cpum.s.GuestFeatures.fLongMode = 0;
     4504            break;
     4505
     4506        case CPUMCPUIDFEATURE_LAHF:
     4507            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4508            if (pLeaf)
     4509                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
     4510            pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
     4511            break;
     4512
     4513        case CPUMCPUIDFEATURE_RDTSCP:
     4514            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
     4515            if (pLeaf)
     4516                pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
     4517            pVM->cpum.s.GuestFeatures.fRdTscP = 0;
     4518            Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
     4519            break;
     4520
     4521        case CPUMCPUIDFEATURE_HVP:
     4522            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
     4523            if (pLeaf)
     4524                pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
     4525            pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
     4526            break;
     4527
     4528        case CPUMCPUIDFEATURE_MWAIT_EXTS:
     4529            pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
     4530            if (pLeaf)
     4531                pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
     4532            pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
     4533            Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
     4534            break;
     4535
     4536        default:
     4537            AssertMsgFailed(("enmFeature=%d\n", enmFeature));
     4538            break;
     4539    }
     4540
     4541    for (VMCPUID i = 0; i < pVM->cCpus; i++)
     4542    {
     4543        PVMCPU pVCpu = &pVM->aCpus[i];
     4544        pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
     4545    }
    40994546}
    41004547

  • trunk/src/VBox/VMM/VMMR3/GIMHv.cpp

    r61771 r61776  
    330330     * Expose HVP (Hypervisor Present) bit to the guest.
    331331     */
    332     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
     332    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
    333333
    334334    /*

  • trunk/src/VBox/VMM/VMMR3/GIMKvm.cpp

    r61632 r61776  
    121121     * Expose HVP (Hypervisor Present) bit to the guest.
    122122     */
    123     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
     123    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
    124124
    125125    /*

  • trunk/src/VBox/VMM/VMMR3/GIMMinimal.cpp

    r61632 r61776  
    5252     * Enable the Hypervisor Present.
    5353     */
    54     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
     54    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
    5555
    5656    return VINF_SUCCESS;

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r61763 r61776  
    14041404     */
    14051405    if (   !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    1406         && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
    1407     {
    1408         CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
     1406        && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
     1407    {
     1408        CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
    14091409        LogRel(("HM: Disabled RDTSCP\n"));
    14101410    }
    … …  
    15001500     * Change the CPU features.
    15011501     */
    1502     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
     1502    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
    15031503    if (pVM->hm.s.fAllow64BitGuests)
    15041504    {
    1505         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
    1506         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
    1507         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);            /* 64 bits only on Intel CPUs */
    1508         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
    1509         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
     1505        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
     1506        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
     1507        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);            /* 64 bits only on Intel CPUs */
     1508        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
     1509        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
    15101510    }
    15111511    /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
    15121512       (we reuse the host EFER in the switcher). */
    15131513    /** @todo this needs to be fixed properly!! */
    1514     else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
     1514    else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
    15151515    {
    15161516        if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
    1517             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
     1517            CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
    15181518        else
    15191519            LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
    … …  
    16941694     * Change the CPU features.
    16951695     */
    1696     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
    1697     CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
     1696    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
     1697    CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
    16981698    if (pVM->hm.s.fAllow64BitGuests)
    16991699    {
    1700         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
    1701         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
    1702         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
    1703         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
     1700        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
     1701        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
     1702        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
     1703        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
    17041704    }
    17051705    /* Turn on NXE if PAE has been enabled. */
    1706     else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
    1707         CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
     1706    else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
     1707        CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
    17081708
    17091709    LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));

  • trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

    r61735 r61776  
    311311
    312312
    313 /** @interface_method_impl{PDMAPICHLPR3,pfnChangeFeature} */
    314 static DECLCALLBACK(void) pdmR3ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICMODE enmMode)
    315 {
    316 #ifdef VBOX_WITH_NEW_APIC
    317     /*
    318      * The old code is also most likely incorrect with regards to changing the CPUID bits,
    319      * see @bugref{8245#c32}.
    320      *
    321      * The new code should directly invoke APICUpdateCpuIdForMode() instead of using this
    322      * indirect helper.
    323      */
    324     AssertMsgFailed(("pdmR3ApicHlp_ChangeFeature unsupported in VBOX_WITH_NEW_APIC!"));
    325 #else
    326     PDMDEV_ASSERT_DEVINS(pDevIns);
    327     LogFlow(("pdmR3ApicHlp_ChangeFeature: caller='%s'/%d: mode=%d\n",
     313/** @interface_method_impl{PDMAPICHLPR3,pfnSetFeatureLevel} */
     314static DECLCALLBACK(void) pdmR3ApicHlp_SetFeatureLevel(PPDMDEVINS pDevIns, PDMAPICMODE enmMode)
     315{
     316    PDMDEV_ASSERT_DEVINS(pDevIns);
     317    LogFlow(("pdmR3ApicHlp_SetFeatureLevel: caller='%s'/%d: mode=%d\n",
    328318             pDevIns->pReg->szName, pDevIns->iInstance, (int)enmMode));
    329319    switch (enmMode)
    330320    {
    331321        case PDMAPICMODE_NONE:
    332             CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
    333             CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
     322            CPUMR3ClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
     323            CPUMR3ClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
    334324            break;
    335325        case PDMAPICMODE_APIC:
    336             CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
    337             CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
     326            CPUMR3ClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
     327            CPUMR3SetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
    338328            break;
    339329        case PDMAPICMODE_X2APIC:
    340             CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
    341             CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
     330            CPUMR3SetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC);
     331            CPUMR3SetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_X2APIC);
    342332            break;
    343333        default:
    344334            AssertMsgFailed(("Unknown APIC mode: %d\n", (int)enmMode));
    345335    }
    346 #endif
    347336}
    348337
    … …  
    453442    pdmR3ApicHlp_BusBroadcastEoi,
    454443    pdmR3ApicHlp_CalcIrqTag,
    455     pdmR3ApicHlp_ChangeFeature,
     444    pdmR3ApicHlp_SetFeatureLevel,
    456445    pdmR3ApicHlp_GetCpuId,
    457446    pdmR3ApicHlp_SendStartupIpi,

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_3200.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00000f48, 0x00000800, 0x00000000, 0x078bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00000f48, 0x00000800, 0x00000000, 0x078bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x80000000, 0x00000000, 0x00000000, 0x80000018, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    32     { 0x80000001, 0x00000000, 0x00000000, 0x00000f48, 0x0000010a, 0x00000000, 0xe1d3fbff, 0 },
     32    { 0x80000001, 0x00000000, 0x00000000, 0x00000f48, 0x0000010a, 0x00000000, 0xe1d3fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3333    { 0x80000002, 0x00000000, 0x00000000, 0x20444d41, 0x6c687441, 0x74286e6f, 0x3620296d, 0 },
    3434    { 0x80000003, 0x00000000, 0x00000000, 0x72502034, 0x7365636f, 0x20726f73, 0x30303233, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Athlon_64_X2_Dual_Core_4200.h

    r54737 r61776  
    3333{
    3434    { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    35     { 0x00000001, 0x00000000, 0x00000000, 0x00040fb2, 0x01020800, 0x00002001, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     35    { 0x00000001, 0x00000000, 0x00000000, 0x00040fb2, 0x01020800, 0x00002001, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3636    { 0x80000000, 0x00000000, 0x00000000, 0x80000018, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    37     { 0x80000001, 0x00000000, 0x00000000, 0x00040fb2, 0x000008d1, 0x0000001f, 0xebd3fbff, 0 },
     37    { 0x80000001, 0x00000000, 0x00000000, 0x00040fb2, 0x000008d1, 0x0000001f, 0xebd3fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3838    { 0x80000002, 0x00000000, 0x00000000, 0x20444d41, 0x6c687441, 0x74286e6f, 0x3620296d, 0 },
    3939    { 0x80000003, 0x00000000, 0x00000000, 0x32582034, 0x61754420, 0x6f43206c, 0x50206572, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_FX_8150_Eight_Core.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00600f12, 0x02080800, 0x1e98220b, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00600f12, 0x02080800, 0x1e98220b, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    … …  
    4343    { 0x0000000d, 0x00000001, UINT32_MAX, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    4444    { 0x80000000, 0x00000000, 0x00000000, 0x8000001e, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    45     { 0x80000001, 0x00000000, 0x00000000, 0x00600f12, 0x10000000, 0x01c9bfff, 0x2fd3fbff, 0 },
     45    { 0x80000001, 0x00000000, 0x00000000, 0x00600f12, 0x10000000, 0x01c9bfff, 0x2fd3fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    4646    { 0x80000002, 0x00000000, 0x00000000, 0x20444d41, 0x74285846, 0x382d296d, 0x20303531, 0 },
    4747    { 0x80000003, 0x00000000, 0x00000000, 0x68676945, 0x6f432d74, 0x50206572, 0x65636f72, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/AMD_Phenom_II_X6_1100T.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000006, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00100fa0, 0x01060800, 0x00802009, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00100fa0, 0x01060800, 0x00802009, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    … …  
    3535    { 0x00000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0 },
    3636    { 0x80000000, 0x00000000, 0x00000000, 0x8000001b, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    37     { 0x80000001, 0x00000000, 0x00000000, 0x00100fa0, 0x100000a1, 0x000837ff, 0xefd3fbff, 0 },
     37    { 0x80000001, 0x00000000, 0x00000000, 0x00100fa0, 0x100000a1, 0x000837ff, 0xefd3fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3838    { 0x80000002, 0x00000000, 0x00000000, 0x20444d41, 0x6e656850, 0x74286d6f, 0x4920296d, 0 },
    3939    { 0x80000003, 0x00000000, 0x00000000, 0x36582049, 0x30313120, 0x50205430, 0x65636f72, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Atom_330_1_60GHz.h

    r58572 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000a, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000106c2, 0x01040800, 0x0040e31d, 0xbfe9fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000106c2, 0x01040800, 0x0040e31d, 0xbfe9fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x4fba5901, 0x0e3080c0, 0x00000000, 0x00000000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i5_3570.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000306a9, 0x04100800, 0x7fbae3ff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000306a9, 0x04100800, 0x7fbae3ff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76035a01, 0x00f0b0ff, 0x00000000, 0x00ca0000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_2635QM.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000206a7, 0x04100800, 0x1fbae3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000206a7, 0x04100800, 0x1fbae3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76035a01, 0x00f0b2ff, 0x00000000, 0x00ca0000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_3820QM.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000306a9, 0x02100800, 0x7fbae3ff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000306a9, 0x02100800, 0x7fbae3ff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76035a01, 0x00f0b2ff, 0x00000000, 0x00ca0000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_3960X.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000206d6, 0x02200800, 0x1fbee3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000206d6, 0x02200800, 0x1fbee3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76035a01, 0x00f0b2ff, 0x00000000, 0x00ca0000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_5600U.h

    r60762 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000014, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000306d4, 0x00100800, 0x7ffafbff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000306d4, 0x00100800, 0x7ffafbff, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76036301, 0x00f0b5ff, 0x00000000, 0x00c30000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_6700K.h

    r60762 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000016, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000506e3, 0x02100800, 0x7ffafbbf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000506e3, 0x02100800, 0x7ffafbbf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x76036301, 0x00f0b5ff, 0x00000000, 0x00c30000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_4_3_00GHz.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000005, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00000f43, 0x00020800, 0x0000649d, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00000f43, 0x00020800, 0x0000649d, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x605b5001, 0x00000000, 0x00000000, 0x007d7040, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_M_processor_2_00GHz.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000006d6, 0x00000816, 0x00000180, 0xafe9f9bf, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000006d6, 0x00000816, 0x00000180, 0xafe9f9bf, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x02b3b001, 0x000000f0, 0x00000000, 0x2c04307d, 0 },
    3232    { 0x80000000, 0x00000000, 0x00000000, 0x80000004, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Pentium_N3530_2_16GHz.h

    r60762 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000b, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00030678, 0x02100800, 0x41d8e3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00030678, 0x02100800, 0x41d8e3bf, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x61b3a001, 0x0000ffc2, 0x00000000, 0x00000000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_Xeon_X5482_3_20GHz.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000a, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00010676, 0x04040800, 0x000ce3bd, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00010676, 0x04040800, 0x000ce3bd, 0xbfebfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x05b0b101, 0x005657f0, 0x00000000, 0x2cb4304e, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/Quad_Core_AMD_Opteron_2384.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x00000005, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x00100f42, 0x06040800, 0x00802009, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x00100f42, 0x06040800, 0x00802009, 0x178bfbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    … …  
    3434    { 0x00000005, 0x00000000, 0x00000000, 0x00000040, 0x00000040, 0x00000003, 0x00000000, 0 },
    3535    { 0x80000000, 0x00000000, 0x00000000, 0x8000001b, 0x68747541, 0x444d4163, 0x69746e65, 0 },
    36     { 0x80000001, 0x00000000, 0x00000000, 0x00100f42, 0x00000d4f, 0x000037ff, 0xefd3fbff, 0 },
     36    { 0x80000001, 0x00000000, 0x00000000, 0x00100f42, 0x00000d4f, 0x000037ff, 0xefd3fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3737    { 0x80000002, 0x00000000, 0x00000000, 0x64617551, 0x726f432d, 0x4d412065, 0x704f2044, 0 },
    3838    { 0x80000003, 0x00000000, 0x00000000, 0x6f726574, 0x6d74286e, 0x72502029, 0x7365636f, 0 },

  • trunk/src/VBox/VMM/VMMR3/cpus/VIA_QuadCore_L4700_1_2_GHz.h

    r54737 r61776  
    2828{
    2929    { 0x00000000, 0x00000000, 0x00000000, 0x0000000a, 0x746e6543, 0x736c7561, 0x48727561, 0 },
    30     { 0x00000001, 0x00000000, 0x00000000, 0x000006fd, 0x06080800, 0x008863a9, 0xbfc9fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID },
     30    { 0x00000001, 0x00000000, 0x00000000, 0x000006fd, 0x06080800, 0x008863a9, 0xbfc9fbff, 0 | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID | CPUMCPUIDLEAF_F_CONTAINS_APIC },
    3131    { 0x00000002, 0x00000000, 0x00000000, 0x02b3b001, 0x00000000, 0x00000000, 0x2c04307d, 0 },
    3232    { 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette