Changeset 61795 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Jun 21, 2016 2:18:04 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

108193

Message:

VMM/APIC: Cleanup.

File:

• trunk/src/VBox/VMM/VMMAll/APICAll.cpp (modified) (11 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -2091 +2091 @@
                  *
                  * We'll also manually manage the APIC base MSR here. We want a single-point of commit
-                 * at the end of this function rather than touching it in APICR3Reset. This means we also
+                 * at the end of this function rather than updating it in apicR3ResetCpu. This means we also
                  * need to update the CPUID leaf ourselves.
                  */
-                apicR3ResetEx(pVCpu, false /* fResetApicBaseMsr */);
+                apicR3ResetCpu(pVCpu, false /* fResetApicBaseMsr */);
                 uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
                 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, false /*fVisible*/);
@@ -2398 +2398 @@
                 case XAPICDELIVERYMODE_EXTINT:
                 {
-                    Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
+                    Log2(("APIC%u: apicLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
                           u8Level ? "Raising" : "Lowering", u8Pin));
                     if (u8Level)
@@ -2426 +2426 @@
         {
             /* LINT0 behaves as an external interrupt pin. */
-            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
+            Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
                   u8Level ? "raising" : "lowering"));
             if (u8Level)
@@ -2436 +2436 @@
         {
             /* LINT1 behaves as NMI. */
-            Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
+            Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
             apicSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
         }
@@ -2454 +2454 @@
     NOREF(pu32TagSrc);
 
-    LogFlow(("APIC%u: APICGetInterrupt:\n", pVCpu->idCpu));
+    LogFlow(("APIC%u: apicGetInterrupt:\n", pVCpu->idCpu));
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
@@ -2475 +2475 @@
                 && XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
             {
-                Log2(("APIC%u: APICGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
+                Log2(("APIC%u: apicGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
                       uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
                 *pu8Vector = uVector;
@@ -2496 +2496 @@
                 apicSignalNextPendingIntr(pVCpu);
 
-                Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
+                Log2(("APIC%u: apicGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
                 *pu8Vector = uVector;
                 return VINF_SUCCESS;
@@ -2503 +2503 @@
             {
                 STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
-                Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
+                Log2(("APIC%u: apicGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
                       pVCpu->idCpu, uVector, uPpr));
             }
         }
         else
-            Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
+            Log2(("APIC%u: apicGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
     }
     else
-        Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
+        Log2(("APIC%u: apicGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
 
     return VERR_APIC_INTR_NOT_PENDING;
@@ -2536 +2536 @@
     *(uint32_t *)pv = uValue;
 
-    Log2(("APIC%u: APICReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    Log2(("APIC%u: apicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     return rc;
 }
@@ -2694 +2694 @@
     uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
 
-    Log2(("APIC%u: APICStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
+    Log2(("APIC%u: apicStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
           uTimerShift, cTicksToNext));
 
@@ -2721 +2721 @@
     Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
 
-    Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
+    Log2(("APIC%u: apicStopTimer\n", pVCpu->idCpu));
 
     PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);