Changeset 61903 in vbox for trunk/src/VBox/Devices/Audio
- Timestamp:
- Jun 27, 2016 4:02:59 PM (9 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (56 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r61888 r61903 46 46 *********************************************************************************************************************************/ 47 47 48 #if def DEBUG_andy48 #if 0 49 49 /* 50 50 * AC97_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data … … 58 58 # define AC97_DEBUG_DUMP_PCM_DATA_PATH "/tmp/" 59 59 # endif 60 #endif /* DEBUG_andy */60 #endif 61 61 62 62 /** Current saved state version. */ … … 67 67 68 68 /** @todo Use AC97_ prefixes! */ 69 #define SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */70 #define SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */71 #define SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */72 #define SR_CELV RT_BIT(1) /* ro, Current equals last valid. */73 #define SR_DCH RT_BIT(0) /* ro, Controller halted. */74 #define SR_VALID_MASK (RT_BIT(5) - 1)75 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS |SR_LVBCI)76 #define SR_RO_MASK (SR_DCH |SR_CELV)77 #define SR_INT_MASK (SR_FIFOE | SR_BCIS |SR_LVBCI)78 79 #define CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */80 #define CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */81 #define CR_LVBIE RT_BIT(2) /* rw Last Valid Buffer Interrupt Enable. */82 #define CR_RR RT_BIT(1) /* rw Reset Registers. */83 #define CR_RPBM RT_BIT(0) /* rw Run/Pause Bus Master. */84 #define CR_VALID_MASK (RT_BIT(5) - 1)85 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE |CR_LVBIE)86 87 #define GC_WR 4 /* rw */88 #define GC_CR 2 /* rw */89 #define GC_VALID_MASK (RT_BIT(6) - 1)90 91 #define GS_MD3 RT_BIT(17) /* rw */92 #define GS_AD3 RT_BIT(16) /* rw */93 #define GS_RCS RT_BIT(15) /* rwc */94 #define GS_B3S12 RT_BIT(14) /* ro */95 #define GS_B2S12 RT_BIT(13) /* ro */96 #define GS_B1S12 RT_BIT(12) /* ro */97 #define GS_S1R1 RT_BIT(11) /* rwc */98 #define GS_S0R1 RT_BIT(10) /* rwc */99 #define GS_S1CR RT_BIT(9) /* ro */100 #define GS_S0CR RT_BIT(8) /* ro */101 #define GS_MINT RT_BIT(7) /* ro */102 #define GS_POINT RT_BIT(6) /* ro */103 #define GS_PIINT RT_BIT(5) /* ro */104 #define GS_RSRVD (RT_BIT(4)|RT_BIT(3))105 #define GS_MOINT RT_BIT(2) /* ro */106 #define GS_MIINT RT_BIT(1) /* ro */107 #define GS_GSCI RT_BIT(0) /* rwc */108 #define GS_RO_MASK (GS_B3S12 | \109 GS_B2S12 | \110 GS_B1S12 | \111 GS_S1CR |\112 GS_S0CR |\113 GS_MINT |\114 GS_POINT | \115 GS_PIINT | \116 GS_RSRVD | \117 GS_MOINT | \118 GS_MIINT)119 #define GS_VALID_MASK (RT_BIT(18) - 1)120 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)69 #define AC97_SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */ 70 #define AC97_SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */ 71 #define AC97_SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */ 72 #define AC97_SR_CELV RT_BIT(1) /* ro, Current equals last valid. */ 73 #define AC97_SR_DCH RT_BIT(0) /* ro, Controller halted. */ 74 #define AC97_SR_VALID_MASK (RT_BIT(5) - 1) 75 #define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 76 #define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV) 77 #define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 78 79 #define AC97_CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */ 80 #define AC97_CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */ 81 #define AC97_CR_LVBIE RT_BIT(2) /* rw Last Valid Buffer Interrupt Enable. */ 82 #define AC97_CR_RR RT_BIT(1) /* rw Reset Registers. */ 83 #define AC97_CR_RPBM RT_BIT(0) /* rw Run/Pause Bus Master. */ 84 #define AC97_CR_VALID_MASK (RT_BIT(5) - 1) 85 #define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE) 86 87 #define AC97_GC_WR 4 /* rw */ 88 #define AC97_GC_CR 2 /* rw */ 89 #define AC97_GC_VALID_MASK (RT_BIT(6) - 1) 90 91 #define AC97_GS_MD3 RT_BIT(17) /* rw */ 92 #define AC97_GS_AD3 RT_BIT(16) /* rw */ 93 #define AC97_GS_RCS RT_BIT(15) /* rwc */ 94 #define AC97_GS_B3S12 RT_BIT(14) /* ro */ 95 #define AC97_GS_B2S12 RT_BIT(13) /* ro */ 96 #define AC97_GS_B1S12 RT_BIT(12) /* ro */ 97 #define AC97_GS_S1R1 RT_BIT(11) /* rwc */ 98 #define AC97_GS_S0R1 RT_BIT(10) /* rwc */ 99 #define AC97_GS_S1CR RT_BIT(9) /* ro */ 100 #define AC97_GS_S0CR RT_BIT(8) /* ro */ 101 #define AC97_GS_MINT RT_BIT(7) /* ro */ 102 #define AC97_GS_POINT RT_BIT(6) /* ro */ 103 #define AC97_GS_PIINT RT_BIT(5) /* ro */ 104 #define AC97_GS_RSRVD (RT_BIT(4)|RT_BIT(3)) 105 #define AC97_GS_MOINT RT_BIT(2) /* ro */ 106 #define AC97_GS_MIINT RT_BIT(1) /* ro */ 107 #define AC97_GS_GSCI RT_BIT(0) /* rwc */ 108 #define AC97_GS_RO_MASK (AC97_GS_B3S12 | \ 109 AC97_GS_B2S12 | \ 110 AC97_GS_B1S12 | \ 111 AC97_GS_S1CR | \ 112 AC97_GS_S0CR | \ 113 AC97_GS_MINT | \ 114 AC97_GS_POINT | \ 115 AC97_GS_PIINT | \ 116 AC97_GS_RSRVD | \ 117 AC97_GS_MOINT | \ 118 AC97_GS_MIINT) 119 #define AC97_GS_VALID_MASK (RT_BIT(18) - 1) 120 #define AC97_GS_WCLEAR_MASK (AC97_GS_RCS|AC97_GS_S1R1|AC97_GS_S0R1|AC97_GS_GSCI) 121 121 122 122 /** @name Buffer Descriptor (BD). 123 123 * @{ */ 124 #define BD_IOC RT_BIT(31) /**< Interrupt on Completion. */125 #define BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */126 127 #define BD_MAX_LEN_MASK 0xFFFE124 #define AC97_BD_IOC RT_BIT(31) /**< Interrupt on Completion. */ 125 #define AC97_BD_BUP RT_BIT(30) /**< Buffer Underrun Policy. */ 126 127 #define AC97_BD_MAX_LEN_MASK 0xFFFE 128 128 /** @} */ 129 129 130 130 /** @name Extended Audio Status and Control Register (EACS). 131 131 * @{ */ 132 #define EACS_VRA 1 /**< Variable Rate Audio (4.2.1.1). */133 #define EACS_VRM 8 /**< Variable Rate Mic Audio (4.2.1.1). */132 #define AC97_EACS_VRA 1 /**< Variable Rate Audio (4.2.1.1). */ 133 #define AC97_EACS_VRM 8 /**< Variable Rate Mic Audio (4.2.1.1). */ 134 134 /** @} */ 135 135 … … 147 147 /** @} */ 148 148 149 #define REC_MASK 7149 #define AC97_REC_MASK 7 150 150 enum 151 151 { 152 REC_MIC = 0,153 REC_CD,154 REC_VIDEO,155 REC_AUX,156 REC_LINE_IN,157 REC_STEREO_MIX,158 REC_MONO_MIX,159 REC_PHONE152 AC97_REC_MIC = 0, 153 AC97_REC_CD, 154 AC97_REC_VIDEO, 155 AC97_REC_AUX, 156 AC97_REC_LINE_IN, 157 AC97_REC_STEREO_MIX, 158 AC97_REC_MONO_MIX, 159 AC97_REC_PHONE 160 160 }; 161 161 … … 198 198 199 199 /* Codec models. */ 200 enum { 201 Codec_STAC9700 = 0, /* SigmaTel STAC9700 */ 202 Codec_AD1980, /* Analog Devices AD1980 */ 203 Codec_AD1981B /* Analog Devices AD1981B */ 204 }; 200 typedef enum 201 { 202 AC97_CODEC_STAC9700 = 0, /* SigmaTel STAC9700 */ 203 AC97_CODEC_AD1980, /* Analog Devices AD1980 */ 204 AC97_CODEC_AD1981B /* Analog Devices AD1981B */ 205 } AC97CODEC; 205 206 206 207 /* Analog Devices miscellaneous regiter bits used in AD1980. */ 207 #define A D_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */208 #define A D_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */208 #define AC97_AD_MISC_LOSEL RT_BIT(5) /* Surround (rear) goes to line out outputs. */ 209 #define AC97_AD_MISC_HPSEL RT_BIT(10) /* PCM (front) goes to headphone outputs. */ 209 210 210 211 #define ICHAC97STATE_2_DEVINS(a_pAC97) ((a_pAC97)->pDevInsR3) … … 231 232 typedef enum 232 233 { 233 PI_INDEX = 0, /** PCM in */234 PO_INDEX, /** PCM out */235 MC_INDEX, /** Mic in */236 LAST_INDEX234 AC97SOUNDSOURCE_PI_INDEX = 0, /** PCM in */ 235 AC97SOUNDSOURCE_PO_INDEX, /** PCM out */ 236 AC97SOUNDSOURCE_MC_INDEX, /** Mic in */ 237 AC97SOUNDSOURCE_LAST_INDEX 237 238 } AC97SOUNDSOURCE; 238 239 239 AC97_NABMBAR_REGS(PI, PI_INDEX * 16);240 AC97_NABMBAR_REGS(PO, PO_INDEX * 16);241 AC97_NABMBAR_REGS(MC, MC_INDEX * 16);240 AC97_NABMBAR_REGS(PI, AC97SOUNDSOURCE_PI_INDEX * 16); 241 AC97_NABMBAR_REGS(PO, AC97SOUNDSOURCE_PO_INDEX * 16); 242 AC97_NABMBAR_REGS(MC, AC97SOUNDSOURCE_MC_INDEX * 16); 242 243 #endif 243 244 … … 245 246 { 246 247 /** NABMBAR: Global Control Register. */ 247 GLOB_CNT = 0x2c,248 AC97_GLOB_CNT = 0x2c, 248 249 /** NABMBAR Global Status. */ 249 GLOB_STA = 0x30,250 AC97_GLOB_STA = 0x30, 250 251 /** Codec Access Semaphore Register. */ 251 CAS = 0x34252 AC97_CAS = 0x34 252 253 }; 253 254 … … 454 455 switch (uIndex) 455 456 { 456 case PI_INDEX: return pThis->pSinkLineIn; break;457 case PO_INDEX: return pThis->pSinkOutput; break;458 case MC_INDEX: return pThis->pSinkMicIn; break;457 case AC97SOUNDSOURCE_PI_INDEX: return pThis->pSinkLineIn; break; 458 case AC97SOUNDSOURCE_PO_INDEX: return pThis->pSinkOutput; break; 459 case AC97SOUNDSOURCE_MC_INDEX: return pThis->pSinkMicIn; break; 459 460 default: break; 460 461 } … … 480 481 pRegs->bd.ctl_len = RT_H2LE_U32(u32[1]); 481 482 #endif 482 pRegs->picb = pRegs->bd.ctl_len & BD_MAX_LEN_MASK;483 pRegs->picb = pRegs->bd.ctl_len & AC97_BD_MAX_LEN_MASK; 483 484 LogFlowFunc(("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n", 484 485 pRegs->civ, pRegs->bd.addr, pRegs->bd.ctl_len >> 16, 485 pRegs->bd.ctl_len & BD_MAX_LEN_MASK,486 (pRegs->bd.ctl_len & BD_MAX_LEN_MASK) << 1)); /** @todo r=andy Assumes 16bit samples. */486 pRegs->bd.ctl_len & AC97_BD_MAX_LEN_MASK, 487 (pRegs->bd.ctl_len & AC97_BD_MAX_LEN_MASK) << 1)); /** @todo r=andy Assumes 16bit samples. */ 487 488 } 488 489 … … 498 499 int iIRQL; 499 500 500 uint32_t new_mask = new_sr & SR_INT_MASK;501 uint32_t old_mask = pRegs->sr & SR_INT_MASK;502 503 static uint32_t const masks[] = { GS_PIINT, GS_POINT,GS_MINT };501 uint32_t new_mask = new_sr & AC97_SR_INT_MASK; 502 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK; 503 504 static uint32_t const masks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT }; 504 505 505 506 if (new_mask ^ old_mask) … … 511 512 iIRQL = 0; 512 513 } 513 else if ((new_mask & SR_LVBCI) && (pRegs->cr &CR_LVBIE))514 else if ((new_mask & AC97_SR_LVBCI) && (pRegs->cr & AC97_CR_LVBIE)) 514 515 { 515 516 fSignal = true; 516 517 iIRQL = 1; 517 518 } 518 else if ((new_mask & SR_BCIS) && (pRegs->cr &CR_IOCE))519 else if ((new_mask & AC97_SR_BCIS) && (pRegs->cr & AC97_CR_IOCE)) 519 520 { 520 521 fSignal = true; … … 526 527 527 528 LogFlowFunc(("IOC%d, LVB%d, sr=%#x, fSignal=%RTbool, IRQL=%d\n", 528 pRegs->sr & SR_BCIS, pRegs->sr &SR_LVBCI, pRegs->sr, fSignal, iIRQL));529 pRegs->sr & AC97_SR_BCIS, pRegs->sr & AC97_SR_LVBCI, pRegs->sr, fSignal, iIRQL)); 529 530 530 531 if (fSignal) … … 596 597 pRegs->lvi = 0; 597 598 598 ichac97StreamUpdateStatus(pThis, pStream, SR_DCH); /** @todo Do we need to do that? */599 ichac97StreamUpdateStatus(pThis, pStream, AC97_SR_DCH); /** @todo Do we need to do that? */ 599 600 600 601 pRegs->picb = 0; 601 602 pRegs->piv = 0; 602 pRegs->cr = pRegs->cr & CR_DONT_CLEAR_MASK;603 pRegs->cr = pRegs->cr & AC97_CR_DONT_CLEAR_MASK; 603 604 pRegs->bd_valid = 0; 604 605 … … 640 641 LogFlowFuncEnter(); 641 642 642 ichac97StreamInit(pThis, &pThis->StreamLineIn, PI_INDEX);643 ichac97StreamInit(pThis, &pThis->StreamMicIn, MC_INDEX);644 ichac97StreamInit(pThis, &pThis->StreamOut, PO_INDEX);643 ichac97StreamInit(pThis, &pThis->StreamLineIn, AC97SOUNDSOURCE_PI_INDEX); 644 ichac97StreamInit(pThis, &pThis->StreamMicIn, AC97SOUNDSOURCE_MC_INDEX); 645 ichac97StreamInit(pThis, &pThis->StreamOut, AC97SOUNDSOURCE_PO_INDEX); 645 646 646 647 return VINF_SUCCESS; … … 845 846 AssertPtrReturn(pThis, VERR_INVALID_POINTER); 846 847 AssertPtrReturn(pStream, VERR_INVALID_POINTER); 847 AssertReturn(u8Strm <= LAST_INDEX, VERR_INVALID_PARAMETER);848 AssertReturn(u8Strm <= AC97SOUNDSOURCE_LAST_INDEX, VERR_INVALID_PARAMETER); 848 849 AssertPtrReturn(pCfg, VERR_INVALID_POINTER); 849 850 … … 856 857 switch (pStream->u8Strm) 857 858 { 858 case PI_INDEX:859 case AC97SOUNDSOURCE_PI_INDEX: 859 860 rc = ichac97CreateIn(pThis, "ac97.pi", PDMAUDIORECSOURCE_LINE, pCfg); 860 861 break; 861 862 862 case MC_INDEX:863 case AC97SOUNDSOURCE_MC_INDEX: 863 864 rc = ichac97CreateIn(pThis, "ac97.mc", PDMAUDIORECSOURCE_MIC, pCfg); 864 865 break; 865 866 866 case PO_INDEX:867 case AC97SOUNDSOURCE_PO_INDEX: 867 868 rc = ichac97CreateOut(pThis, "ac97.po", pCfg); 868 869 break; … … 889 890 switch (u8Strm) 890 891 { 891 case PI_INDEX:892 case AC97SOUNDSOURCE_PI_INDEX: 892 893 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_LR_ADC_Rate); 893 894 streamCfg.enmDir = PDMAUDIODIR_IN; … … 895 896 break; 896 897 897 case MC_INDEX:898 case AC97SOUNDSOURCE_MC_INDEX: 898 899 streamCfg.uHz = ichac97MixerGet(pThis, AC97_MIC_ADC_Rate); 899 900 streamCfg.enmDir = PDMAUDIODIR_IN; … … 901 902 break; 902 903 903 case PO_INDEX:904 case AC97SOUNDSOURCE_PO_INDEX: 904 905 streamCfg.uHz = ichac97MixerGet(pThis, AC97_PCM_Front_DAC_Rate); 905 906 streamCfg.enmDir = PDMAUDIODIR_OUT; … … 1086 1087 switch (i) 1087 1088 { 1088 case REC_MIC: return PDMAUDIORECSOURCE_MIC;1089 case REC_CD: return PDMAUDIORECSOURCE_CD;1090 case REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO;1091 case REC_AUX: return PDMAUDIORECSOURCE_AUX;1092 case REC_LINE_IN: return PDMAUDIORECSOURCE_LINE;1093 case REC_PHONE: return PDMAUDIORECSOURCE_PHONE;1089 case AC97_REC_MIC: return PDMAUDIORECSOURCE_MIC; 1090 case AC97_REC_CD: return PDMAUDIORECSOURCE_CD; 1091 case AC97_REC_VIDEO: return PDMAUDIORECSOURCE_VIDEO; 1092 case AC97_REC_AUX: return PDMAUDIORECSOURCE_AUX; 1093 case AC97_REC_LINE_IN: return PDMAUDIORECSOURCE_LINE; 1094 case AC97_REC_PHONE: return PDMAUDIORECSOURCE_PHONE; 1094 1095 default: 1095 1096 break; … … 1104 1105 switch (rs) 1105 1106 { 1106 case PDMAUDIORECSOURCE_MIC: return REC_MIC;1107 case PDMAUDIORECSOURCE_CD: return REC_CD;1108 case PDMAUDIORECSOURCE_VIDEO: return REC_VIDEO;1109 case PDMAUDIORECSOURCE_AUX: return REC_AUX;1110 case PDMAUDIORECSOURCE_LINE: return REC_LINE_IN;1111 case PDMAUDIORECSOURCE_PHONE: return REC_PHONE;1107 case PDMAUDIORECSOURCE_MIC: return AC97_REC_MIC; 1108 case PDMAUDIORECSOURCE_CD: return AC97_REC_CD; 1109 case PDMAUDIORECSOURCE_VIDEO: return AC97_REC_VIDEO; 1110 case PDMAUDIORECSOURCE_AUX: return AC97_REC_AUX; 1111 case PDMAUDIORECSOURCE_LINE: return AC97_REC_LINE_IN; 1112 case PDMAUDIORECSOURCE_PHONE: return AC97_REC_PHONE; 1112 1113 default: 1113 1114 break; … … 1115 1116 1116 1117 LogFlowFunc(("Unknown audio recording source %d using MIC\n", rs)); 1117 return REC_MIC;1118 return AC97_REC_MIC; 1118 1119 } 1119 1120 1120 1121 static void ichac97RecordSelect(PAC97STATE pThis, uint32_t val) 1121 1122 { 1122 uint8_t rs = val & REC_MASK;1123 uint8_t ls = (val >> 8) & REC_MASK;1123 uint8_t rs = val & AC97_REC_MASK; 1124 uint8_t ls = (val >> 8) & AC97_REC_MASK; 1124 1125 PDMAUDIORECSOURCE ars = ichac97IndextoRecSource(rs); 1125 1126 PDMAUDIORECSOURCE als = ichac97IndextoRecSource(ls); … … 1160 1161 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate , 0xbb80); 1161 1162 1162 if (pThis->uCodecModel == Codec_AD1980)1163 if (pThis->uCodecModel == AC97_CODEC_AD1980) 1163 1164 { 1164 1165 /* Analog Devices 1980 (AD1980) */ … … 1168 1169 ichac97MixerSet(pThis, AC97_Headphone_Volume_Mute , 0x8000); 1169 1170 } 1170 else if (pThis->uCodecModel == Codec_AD1981B)1171 else if (pThis->uCodecModel == AC97_CODEC_AD1981B) 1171 1172 { 1172 1173 /* Analog Devices 1981B (AD1981B) */ … … 1337 1338 1338 1339 /* Select audio sink to process. */ 1339 AssertMsg(pStream->u8Strm != PO_INDEX, ("Can't read from output\n"));1340 PAUDMIXSINK pSink = pStream->u8Strm == MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn;1340 AssertMsg(pStream->u8Strm != AC97SOUNDSOURCE_PO_INDEX, ("Can't read from output\n")); 1341 PAUDMIXSINK pSink = pStream->u8Strm == AC97SOUNDSOURCE_MC_INDEX ? pThis->pSinkMicIn : pThis->pSinkLineIn; 1341 1342 AssertPtr(pSink); 1342 1343 … … 1494 1495 PAC97BMREGS pRegs = &pStream->Regs; 1495 1496 1496 if (pRegs->sr & SR_DCH) /* Controller halted? */1497 { 1498 if (pRegs->cr & CR_RPBM) /* Bus master operation starts. */1497 if (pRegs->sr & AC97_SR_DCH) /* Controller halted? */ 1498 { 1499 if (pRegs->cr & AC97_CR_RPBM) /* Bus master operation starts. */ 1499 1500 { 1500 1501 switch (pStream->u8Strm) 1501 1502 { 1502 case PO_INDEX:1503 case AC97SOUNDSOURCE_PO_INDEX: 1503 1504 ichac97WriteBUP(pThis, cbToProcess); 1504 1505 break; … … 1515 1516 1516 1517 /* BCIS flag still set? Skip iteration. */ 1517 if (pRegs->sr & SR_BCIS)1518 if (pRegs->sr & AC97_SR_BCIS) 1518 1519 { 1519 1520 Log3Func(("[SD%RU8] BCIS set\n", pStream->u8Strm)); … … 1544 1545 if (pRegs->civ == pRegs->lvi) 1545 1546 { 1546 pRegs->sr |= SR_DCH; /** @todo r=andy Also set CELV? */1547 pRegs->sr |= AC97_SR_DCH; /** @todo r=andy Also set CELV? */ 1547 1548 pThis->bup_flag = 0; 1548 1549 … … 1551 1552 } 1552 1553 1553 pRegs->sr &= ~ SR_CELV;1554 pRegs->sr &= ~AC97_SR_CELV; 1554 1555 pRegs->civ = pRegs->piv; 1555 1556 pRegs->piv = (pRegs->piv + 1) % 32; /** @todo r=andy Define for max BDLEs? */ … … 1562 1563 switch (pStream->u8Strm) 1563 1564 { 1564 case PO_INDEX:1565 case AC97SOUNDSOURCE_PO_INDEX: 1565 1566 { 1566 1567 cbToTransfer = RT_MIN((uint32_t)(pRegs->picb << 1), cbLeft); /** @todo r=andy Assumes 16bit samples. */ … … 1579 1580 } 1580 1581 1581 case PI_INDEX:1582 case MC_INDEX:1582 case AC97SOUNDSOURCE_PI_INDEX: 1583 case AC97SOUNDSOURCE_MC_INDEX: 1583 1584 { 1584 1585 cbToTransfer = RT_MIN((uint32_t)(pRegs->picb << 1), cbLeft); /** @todo r=andy Assumes 16bit samples. */ … … 1607 1608 if (!pRegs->picb) 1608 1609 { 1609 uint32_t new_sr = pRegs->sr & ~ SR_CELV;1610 1611 if (pRegs->bd.ctl_len & BD_IOC)1610 uint32_t new_sr = pRegs->sr & ~AC97_SR_CELV; 1611 1612 if (pRegs->bd.ctl_len & AC97_BD_IOC) 1612 1613 { 1613 new_sr |= SR_BCIS;1614 new_sr |= AC97_SR_BCIS; 1614 1615 } 1615 1616 … … 1619 1620 LogFunc(("Underrun CIV (%RU8) == LVI (%RU8)\n", pRegs->civ, pRegs->lvi)); 1620 1621 1621 new_sr |= SR_LVBCI | SR_DCH |SR_CELV;1622 pThis->bup_flag = (pRegs->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;1622 new_sr |= AC97_SR_LVBCI | AC97_SR_DCH | AC97_SR_CELV; 1623 pThis->bup_flag = (pRegs->bd.ctl_len & AC97_BD_BUP) ? BUP_LAST : 0; 1623 1624 1624 1625 rc = VINF_EOF; … … 1668 1669 switch (uPortIdx) 1669 1670 { 1670 case CAS:1671 case AC97_CAS: 1671 1672 /* Codec Access Semaphore Register */ 1672 1673 LogFlowFunc(("CAS %d\n", pThis->cas)); … … 1774 1775 AC97_PORT2IDX(uPortIdx), *pu32Val, pRegs->picb, pRegs->piv, pRegs->cr)); 1775 1776 break; 1776 case GLOB_CNT:1777 case AC97_GLOB_CNT: 1777 1778 /* Global Control */ 1778 1779 *pu32Val = pThis->glob_cnt; 1779 1780 LogFlowFunc(("glob_cnt -> %#x\n", *pu32Val)); 1780 1781 break; 1781 case GLOB_STA:1782 case AC97_GLOB_STA: 1782 1783 /* Global Status */ 1783 *pu32Val = pThis->glob_sta | GS_S0CR;1784 *pu32Val = pThis->glob_sta | AC97_GS_S0CR; 1784 1785 LogFlowFunc(("glob_sta -> %#x\n", *pu32Val)); 1785 1786 break; … … 1822 1823 case MC_LVI: 1823 1824 /* Last Valid Index */ 1824 if ((pRegs->cr & CR_RPBM) && (pRegs->sr &SR_DCH))1825 if ((pRegs->cr & AC97_CR_RPBM) && (pRegs->sr & AC97_SR_DCH)) 1825 1826 { 1826 pRegs->sr &= ~( SR_DCH |SR_CELV);1827 pRegs->sr &= ~(AC97_SR_DCH | AC97_SR_CELV); 1827 1828 pRegs->civ = pRegs->piv; 1828 1829 pRegs->piv = (pRegs->piv + 1) % 32; … … 1838 1839 { 1839 1840 /* Control Register */ 1840 if (u32Val & CR_RR) /* Busmaster reset */1841 if (u32Val & AC97_CR_RR) /* Busmaster reset */ 1841 1842 { 1842 1843 ichac97StreamResetBMRegs(pThis, pStream); … … 1844 1845 else 1845 1846 { 1846 pRegs->cr = u32Val & CR_VALID_MASK;1847 if (!(pRegs->cr & CR_RPBM))1847 pRegs->cr = u32Val & AC97_CR_VALID_MASK; 1848 if (!(pRegs->cr & AC97_CR_RPBM)) 1848 1849 { 1849 1850 ichac97StreamSetActive(pThis, pStream, false /* fActive */); 1850 pRegs->sr |= SR_DCH;1851 pRegs->sr |= AC97_SR_DCH; 1851 1852 } 1852 1853 else … … 1857 1858 ichac97StreamFetchBDLE(pThis, pStream); 1858 1859 1859 pRegs->sr &= ~ SR_DCH;1860 pRegs->sr &= ~AC97_SR_DCH; 1860 1861 ichac97StreamSetActive(pThis, pStream, true /* fActive */); 1861 1862 } … … 1868 1869 case MC_SR: 1869 1870 /* Status Register */ 1870 pRegs->sr |= u32Val & ~( SR_RO_MASK |SR_WCLEAR_MASK);1871 ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));1871 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK); 1872 ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK)); 1872 1873 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr)); 1873 1874 break; … … 1887 1888 case MC_SR: 1888 1889 /* Status Register */ 1889 pRegs->sr |= u32Val & ~( SR_RO_MASK |SR_WCLEAR_MASK);1890 ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & SR_WCLEAR_MASK));1890 pRegs->sr |= u32Val & ~(AC97_SR_RO_MASK | AC97_SR_WCLEAR_MASK); 1891 ichac97StreamUpdateStatus(pThis, pStream, pRegs->sr & ~(u32Val & AC97_SR_WCLEAR_MASK)); 1891 1892 LogFlowFunc(("SR[%d] <- %#x (sr %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->sr)); 1892 1893 break; … … 1909 1910 LogFlowFunc(("BDBAR[%d] <- %#x (bdbar %#x)\n", AC97_PORT2IDX(uPortIdx), u32Val, pRegs->bdbar)); 1910 1911 break; 1911 case GLOB_CNT:1912 case AC97_GLOB_CNT: 1912 1913 /* Global Control */ 1913 if (u32Val & GC_WR)1914 if (u32Val & AC97_GC_WR) 1914 1915 ichac97WarmReset(pThis); 1915 if (u32Val & GC_CR)1916 if (u32Val & AC97_GC_CR) 1916 1917 ichac97ColdReset(pThis); 1917 if (!(u32Val & ( GC_WR |GC_CR)))1918 pThis->glob_cnt = u32Val & GC_VALID_MASK;1918 if (!(u32Val & (AC97_GC_WR | AC97_GC_CR))) 1919 pThis->glob_cnt = u32Val & AC97_GC_VALID_MASK; 1919 1920 LogFlowFunc(("glob_cnt <- %#x (glob_cnt %#x)\n", u32Val, pThis->glob_cnt)); 1920 1921 break; 1921 case GLOB_STA:1922 case AC97_GLOB_STA: 1922 1923 /* Global Status */ 1923 pThis->glob_sta &= ~(u32Val & GS_WCLEAR_MASK);1924 pThis->glob_sta |= (u32Val & ~( GS_WCLEAR_MASK | GS_RO_MASK)) &GS_VALID_MASK;1924 pThis->glob_sta &= ~(u32Val & AC97_GS_WCLEAR_MASK); 1925 pThis->glob_sta |= (u32Val & ~(AC97_GS_WCLEAR_MASK | AC97_GS_RO_MASK)) & AC97_GS_VALID_MASK; 1925 1926 LogFlowFunc(("glob_sta <- %#x (glob_sta %#x)\n", u32Val, pThis->glob_sta)); 1926 1927 break; … … 2017 2018 break; 2018 2019 case AC97_Master_Volume_Mute: 2019 if (pThis->uCodecModel == Codec_AD1980)2020 if (pThis->uCodecModel == AC97_CODEC_AD1980) 2020 2021 { 2021 if (ichac97MixerGet(pThis, AC97_AD_Misc) & A D_MISC_LOSEL)2022 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_LOSEL) 2022 2023 break; /* Register controls surround (rear), do nothing. */ 2023 2024 } … … 2025 2026 break; 2026 2027 case AC97_Headphone_Volume_Mute: 2027 if (pThis->uCodecModel == Codec_AD1980)2028 if (pThis->uCodecModel == AC97_CODEC_AD1980) 2028 2029 { 2029 if (ichac97MixerGet(pThis, AC97_AD_Misc) & A D_MISC_HPSEL)2030 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL) 2030 2031 { 2031 2032 /* Register controls PCM (front) outputs. */ … … 2051 2052 break; 2052 2053 case AC97_Extended_Audio_Ctrl_Stat: 2053 if (!(u32Val & EACS_VRA))2054 if (!(u32Val & AC97_EACS_VRA)) 2054 2055 { 2055 2056 ichac97MixerSet(pThis, AC97_PCM_Front_DAC_Rate, 48000); … … 2059 2060 ichac97StreamReInit(pThis, &pThis->StreamLineIn); 2060 2061 } 2061 if (!(u32Val & EACS_VRM))2062 if (!(u32Val & AC97_EACS_VRM)) 2062 2063 { 2063 2064 ichac97MixerSet(pThis, AC97_MIC_ADC_Rate, 48000); … … 2068 2069 break; 2069 2070 case AC97_PCM_Front_DAC_Rate: 2070 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)2071 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA) 2071 2072 { 2072 2073 ichac97MixerSet(pThis, index, u32Val); … … 2078 2079 break; 2079 2080 case AC97_MIC_ADC_Rate: 2080 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM)2081 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRM) 2081 2082 { 2082 2083 ichac97MixerSet(pThis, index, u32Val); … … 2088 2089 break; 2089 2090 case AC97_PCM_LR_ADC_Rate: 2090 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA)2091 if (ichac97MixerGet(pThis, AC97_Extended_Audio_Ctrl_Stat) & AC97_EACS_VRA) 2091 2092 { 2092 2093 ichac97MixerSet(pThis, index, u32Val); … … 2157 2158 switch (uID) 2158 2159 { 2159 case PI_INDEX: return &pThis->StreamLineIn;2160 case MC_INDEX: return &pThis->StreamMicIn;2161 case PO_INDEX: return &pThis->StreamOut;2160 case AC97SOUNDSOURCE_PI_INDEX: return &pThis->StreamLineIn; 2161 case AC97SOUNDSOURCE_MC_INDEX: return &pThis->StreamMicIn; 2162 case AC97SOUNDSOURCE_PO_INDEX: return &pThis->StreamOut; 2162 2163 default: break; 2163 2164 } … … 2209 2210 SSMR3PutMem(pSSM, pThis->mixer_data, sizeof(pThis->mixer_data)); 2210 2211 2211 uint8_t active[ LAST_INDEX];2212 2213 active[ PI_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamLineIn) ? 1 : 0;2214 active[ PO_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamOut) ? 1 : 0;2215 active[ MC_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamMicIn) ? 1 : 0;2212 uint8_t active[AC97SOUNDSOURCE_LAST_INDEX]; 2213 2214 active[AC97SOUNDSOURCE_PI_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamLineIn) ? 1 : 0; 2215 active[AC97SOUNDSOURCE_PO_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamOut) ? 1 : 0; 2216 active[AC97SOUNDSOURCE_MC_INDEX] = ichac97StreamIsActive(pThis, &pThis->StreamMicIn) ? 1 : 0; 2216 2217 2217 2218 SSMR3PutMem(pSSM, active, sizeof(active)); … … 2267 2268 2268 2269 /** @todo r=andy Stream IDs are hardcoded to certain streams. */ 2269 uint8_t uaStrmsActive[ LAST_INDEX];2270 uint8_t uaStrmsActive[AC97SOUNDSOURCE_LAST_INDEX]; 2270 2271 SSMR3GetMem(pSSM, uaStrmsActive, sizeof(uaStrmsActive)); 2271 2272 … … 2277 2278 V_(AC97_Mic_Volume_Mute, PDMAUDIOMIXERCTL_MIC_IN); 2278 2279 # undef V_ 2279 if (pThis->uCodecModel == Codec_AD1980)2280 if (ichac97MixerGet(pThis, AC97_AD_Misc) & A D_MISC_HPSEL)2280 if (pThis->uCodecModel == AC97_CODEC_AD1980) 2281 if (ichac97MixerGet(pThis, AC97_AD_Misc) & AC97_AD_MISC_HPSEL) 2281 2282 ichac97MixerSetVolume(pThis, AC97_Headphone_Volume_Mute, PDMAUDIOMIXERCTL_VOLUME_MASTER, 2282 2283 ichac97MixerGet(pThis, AC97_Headphone_Volume_Mute)); … … 2286 2287 { 2287 2288 /** @todo r=andy Stream IDs are hardcoded to certain streams. */ 2288 rc = ichac97StreamSetActive(pThis, &pThis->StreamLineIn, RT_BOOL(uaStrmsActive[ PI_INDEX]));2289 rc = ichac97StreamSetActive(pThis, &pThis->StreamLineIn, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_PI_INDEX])); 2289 2290 if (RT_SUCCESS(rc)) 2290 rc = ichac97StreamSetActive(pThis, &pThis->StreamMicIn, RT_BOOL(uaStrmsActive[ MC_INDEX]));2291 rc = ichac97StreamSetActive(pThis, &pThis->StreamMicIn, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_MC_INDEX])); 2291 2292 if (RT_SUCCESS(rc)) 2292 rc = ichac97StreamSetActive(pThis, &pThis->StreamOut, RT_BOOL(uaStrmsActive[ PO_INDEX]));2293 rc = ichac97StreamSetActive(pThis, &pThis->StreamOut, RT_BOOL(uaStrmsActive[AC97SOUNDSOURCE_PO_INDEX])); 2293 2294 } 2294 2295 … … 2615 2616 bool fChipAD1980 = false; 2616 2617 if (!strcmp(szCodec, "STAC9700")) 2617 pThis->uCodecModel = Codec_STAC9700;2618 pThis->uCodecModel = AC97_CODEC_STAC9700; 2618 2619 else if (!strcmp(szCodec, "AD1980")) 2619 pThis->uCodecModel = Codec_AD1980;2620 pThis->uCodecModel = AC97_CODEC_AD1980; 2620 2621 else if (!strcmp(szCodec, "AD1981B")) 2621 pThis->uCodecModel = Codec_AD1981B;2622 pThis->uCodecModel = AC97_CODEC_AD1981B; 2622 2623 else 2623 2624 { … … 2651 2652 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.config[0x3d] == 0x01); 2652 2653 2653 if (pThis->uCodecModel == Codec_AD1980)2654 if (pThis->uCodecModel == AC97_CODEC_AD1980) 2654 2655 { 2655 2656 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */ 2656 2657 PCIDevSetSubSystemId (&pThis->PciDev, 0x0177); /* 2e ro. */ 2657 2658 } 2658 else if (pThis->uCodecModel == Codec_AD1981B)2659 else if (pThis->uCodecModel == AC97_CODEC_AD1981B) 2659 2660 { 2660 2661 PCIDevSetSubSystemVendorId(&pThis->PciDev, 0x1028); /* 2c ro - Dell.) */
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