Changeset 65951 in vbox for trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
- Timestamp:
- Mar 6, 2017 4:14:35 PM (8 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r65947 r65951 33 33 """ 34 34 __version__ = "$Revision$" 35 36 # pylint: disable=anomalous-backslash-in-string 35 37 36 38 # Standard python imports. … … 278 280 'interrupt': 'DISOPTYPE_INTERRUPT', ##< 279 281 'illegal': 'DISOPTYPE_ILLEGAL', ##< 280 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. */281 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. */282 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. 283 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. 282 284 'inhibit_irqs': 'DISOPTYPE_INHIBIT_IRQS', ##< Will or can inhibit irqs (sti, pop ss, mov ss) */ 283 285 'portio_read': 'DISOPTYPE_PORTIO_READ', ##< 284 286 'portio_write': 'DISOPTYPE_PORTIO_WRITE', ##< 285 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode */ 286 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode */ 287 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size */ 288 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes */ 289 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte */ 290 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b */ 291 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */ 292 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */ 293 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */ 294 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! */ 287 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode 288 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode 289 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size 290 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes 291 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte 292 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b 293 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes 294 ## (only in 16 & 32 bits mode!) 295 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! 296 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! 297 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! 295 298 'ignores_op_size': '', ##< Ignores both operand size prefixes. 296 299 }; … … 567 570 Checks if sValue is a pair. 568 571 """ 572 _ = sValue; 569 573 return False; 570 574 … … 595 599 if fClear != 0: 596 600 aoClear = TestType.get(self, '%#x' % (~fClear)) 597 assert self.isAndOrPair(sValue) ==True;601 assert self.isAndOrPair(sValue) is True; 598 602 return (aoClear[0], aoSet[0]); 599 assert self.isAndOrPair(sValue) ==False;603 assert self.isAndOrPair(sValue) is False; 600 604 return aoSet; 601 605 … … 842 846 843 847 844 class Instruction(object): 848 class Instruction(object): # pylint: disable=too-many-instance-attributes 845 849 """ 846 850 Instruction. … … 856 860 self.aoOperands = []; # type: list(Operand) 857 861 self.sPrefix = None; ##< Single prefix: None, 0x66, 0xf3, 0xf2 858 self.sOpcode = None; 862 self.sOpcode = None; # type: str 859 863 self.sEncoding = None; 860 864 self.asFlTest = None; … … 959 963 if self.sOpcode is None: 960 964 raise Exception('No opcode byte for %s!' % (self,)); 965 sOpcode = str(self.sOpcode); # pylint type confusion workaround. 961 966 962 967 # Full hex byte form. 963 if s elf.sOpcode[:2] == '0x':964 return int(s elf.sOpcode, 16);968 if sOpcode[:2] == '0x': 969 return int(sOpcode, 16); 965 970 966 971 # The /r form: 967 if self.sOpcode[0] == '/' and self.sOpcode[1].isdigit() and len(self.sOpcode) == 2: 968 return int(self.sOpcode[1:]) << 3; 969 970 raise Exception('unsupported opcode byte spec "%s" for %s' % (self.sOpcode, self,)); 971 return -1; 972 if sOpcode[0] == '/' and sOpcode[1].isdigit() and len(sOpcode) == 2: 973 return int(sOpcode[1:]) << 3; 974 975 raise Exception('unsupported opcode byte spec "%s" for %s' % (sOpcode, self,)); 972 976 973 977 … … 1014 1018 'grpP': InstructionMap('grpP', asLeadOpcodes = ['0x0f', '0x0d',], sSelector = '/r'), # AMD: prefetch 1015 1019 1016 'three0f38': InstructionMap('three0f38', asLeadOpcodes = ['0x0f', '0x38',]),1017 1020 'three0f38': InstructionMap('three0f38', asLeadOpcodes = ['0x0f', '0x38',]), 1018 1021 'three0f3a': InstructionMap('three0f3a', asLeadOpcodes = ['0x0f', '0x3a',]), … … 1152 1155 def debug(self, sMessage): 1153 1156 """ 1157 For debugging. 1154 1158 """ 1155 1159 if self.fDebug: … … 1335 1339 """ 1336 1340 asRet = []; 1337 for asLines in a ssSections:1341 for asLines in aasSections: 1338 1342 if len(asLines) > 0: 1339 1343 asRet.append(' '.join([sLine.strip() for sLine in asLines])); … … 1401 1405 """ 1402 1406 oInstr = self.ensureInstructionForOpTag(iTagLine); 1403 if len( self.aoInstructions) > 0 and len(aasSections) > 0:1407 if len(aasSections) > 0: 1404 1408 oInstr.asDescSections.extend(self.flattenSections(aasSections)); 1405 1409 return True; … … 1467 1471 elif sWhere not in g_kdOpLocations: 1468 1472 return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s' 1469 % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),) , iTagLine);1473 % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),)); 1470 1474 1471 1475 # Insert the operand, refusing to overwrite an existing one. … … 1642 1646 'sf': 'X86_EFL_SF', 1643 1647 'zf': 'X86_EFL_ZF', 1644 'cf': 'X86_EFL_CF',1645 1648 'pf': 'X86_EFL_PF', 1646 1649 'if': 'X86_EFL_IF', … … 1770 1773 sMinCpu = asCpus[0]; 1771 1774 if sMinCpu in g_kdCpuNames: 1772 self.sMinCpu = sMinCpu;1775 oInstr.sMinCpu = sMinCpu; 1773 1776 else: 1774 1777 return self.errorComment(iTagLine, '%s: invalid CPU name: %s (names: %s)' … … 1882 1885 return True; 1883 1886 1884 def parseTagOpTest(self, sTag, aasSections, iTagLine, iEndLine): 1887 def parseTagOpTest(self, sTag, aasSections, iTagLine, iEndLine): # pylint: disable=too-many-locals 1885 1888 """ 1886 1889 Tag: \@optest … … 2019 2022 % (sTag, asSelectors, asInputs, asOutputs,)); 2020 2023 2024 _ = iEndLine; 2021 2025 return True; 2022 2026 … … 2039 2043 if not self.oReFunctionName.match(sFunction): 2040 2044 return self.errorComment(iTagLine, '%s: invalid VMM function name: "%s" (valid: %s)' 2041 % (sTag, Name, self.oReFunctionName.pattern));2045 % (sTag, sFunction, self.oReFunctionName.pattern)); 2042 2046 2043 2047 if oInstr.sFunction is not None: 2044 2048 return self.errorComment(iTagLine, '%s: attempting to overwrite VMM function name "%s" with "%s"' 2045 % (sTag, oInstr.s Stats, sStats,));2049 % (sTag, oInstr.sFunction, sFunction,)); 2046 2050 oInstr.sFunction = sFunction; 2047 2051 … … 2067 2071 if not self.oReStatsName.match(sStats): 2068 2072 return self.errorComment(iTagLine, '%s: invalid VMM statistics name: "%s" (valid: %s)' 2069 % (sTag, Name, self.oReStatsName.pattern));2073 % (sTag, sStats, self.oReStatsName.pattern)); 2070 2074 2071 2075 if oInstr.sStats is not None: … … 2201 2205 offOpen = sInvocation.find('('); 2202 2206 if offOpen <= 0: 2203 raiseError("macro invocation open parenthesis not found");2207 self.raiseError("macro invocation open parenthesis not found"); 2204 2208 sName = sInvocation[:offOpen].strip(); 2205 2209 if not self.oReMacroName.match(sName): … … 2258 2262 return None; 2259 2263 2260 def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands): 2264 def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, # pylint: disable=too-many-arguments 2265 sDisHints, sIemHints, asOperands): 2261 2266 """ 2262 2267 Processes one of the a IEMOP_MNEMONIC0EX, IEMOP_MNEMONIC1EX, IEMOP_MNEMONIC2EX, … … 2289 2294 else: 2290 2295 self.error('%s: already saw a IEMOP_MNEMONIC* macro on line %u for this instruction' 2291 % (sMacro, self.iLineMnemonicMacro,));2296 % (sMacro, oInstr.iLineMnemonicMacro,)); 2292 2297 2293 2298 # Mnemonic … … 2300 2305 if len(oInstr.aoOperands) not in [0, len(asOperands)]: 2301 2306 self.error('%s: number of operands given by @opN does not match macro: %s vs %s' 2302 % (sMacro, len(oInstr.aoOperands), len(a oOperands),));2307 % (sMacro, len(oInstr.aoOperands), len(asOperands),)); 2303 2308 for iOperand, sType in enumerate(asOperands): 2304 2309 sWhere = g_kdOpTypes.get(sType, [None, None])[1]; … … 2368 2373 2369 2374 2375 _ = sAsm; 2370 2376 return True; 2371 2377 … … 2376 2382 """ 2377 2383 if asOperands == 0: 2378 return self.workerIemOpMnemonicEx(s Lower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands);2384 return self.workerIemOpMnemonicEx(sMacro, sLower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); 2379 2385 return self.workerIemOpMnemonicEx(sMacro, sLower + '_' + '_'.join(asOperands), sLower + ' ' + ','.join(asOperands), 2380 2386 sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); … … 2431 2437 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[7], asArgs[8], 2432 2438 [asArgs[6],]); 2433 # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \2439 # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) 2434 2440 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2EX'); 2435 2441 if asArgs is not None: 2436 2442 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[8], asArgs[9], 2437 2443 [asArgs[6], asArgs[7]]); 2438 # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \2444 # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) 2439 2445 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3EX'); 2440 2446 if asArgs is not None: 2441 2447 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[9], 2442 2448 asArgs[10], [asArgs[6], asArgs[7], asArgs[8],]); 2443 # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \ 2449 # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, 2450 # a_fIemHints) 2444 2451 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4EX'); 2445 2452 if asArgs is not None: … … 2455 2462 if asArgs is not None: 2456 2463 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[5], asArgs[6], [asArgs[4],]); 2457 # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \2464 # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) 2458 2465 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2'); 2459 2466 if asArgs is not None: 2460 2467 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[6], asArgs[7], 2461 2468 [asArgs[4], asArgs[5],]); 2462 # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \2469 # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) 2463 2470 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3'); 2464 2471 if asArgs is not None: 2465 2472 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[7], asArgs[8], 2466 2473 [asArgs[4], asArgs[5], asArgs[6],]); 2467 # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \2474 # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) 2468 2475 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4'); 2469 2476 if asArgs is not None: … … 2603 2610 """ 2604 2611 2605 for sName, oMap in sorted(iter(g_dInstructionMaps.items()), key = lambda k_v: k_v[1].sEncoding + ''.join(k_v[1].asLeadOpcodes)): 2612 for sName, oMap in sorted(iter(g_dInstructionMaps.items()), 2613 key = lambda aKV: aKV[1].sEncoding + ''.join(aKV[1].asLeadOpcodes)): 2614 assert oMap.sName == sName; 2606 2615 asLines = []; 2607 2616 … … 2743 2752 sLine += s; 2744 2753 2745 # OP("psrlw %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PSRLW, OP_PARM_Vdq, OP_PARM_Wdq, OP_PARM_NONE, DISOPTYPE_HARMLESS), 2754 # OP("psrlw %Vdq,%Wdq", IDX_ParseModRM, IDX_UseModRM, 0, OP_PSRLW, OP_PARM_Vdq, OP_PARM_Wdq, OP_PARM_NONE, 2755 # DISOPTYPE_HARMLESS), 2746 2756 # define OP(pszOpcode, idxParse1, idxParse2, idxParse3, opcode, param1, param2, param3, optype) \ 2747 2757 # { pszOpcode, idxParse1, idxParse2, idxParse3, 0, opcode, param1, param2, param3, 0, 0, optype }
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