Changeset 66323 in vbox for trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

Timestamp:

Mar 29, 2017 8:03:19 AM (8 years ago)

Author:

vboxsync

Message:

IEM: Implemented movq Wq,Vq (66 0f d6).

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (modified) (7 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

@@ -470 +470 @@
     /* [BS3CG1DST_XMM14_HI] = */    8,
     /* [BS3CG1DST_XMM15_HI] = */    8,
+    /* [BS3CG1DST_XMM0_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM1_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM2_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM3_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM4_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM5_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM6_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM7_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM8_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM9_LO_ZX] = */  8,
+    /* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
+    /* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
+    /* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
+    /* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
+    /* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
+    /* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
     /* [BS3CG1DST_XMM0_DW0] = */    4,
     /* [BS3CG1DST_XMM1_DW0] = */    4,
@@ -683 +699 @@
     /* [BS3CG1DST_XMM14_HI] = */    sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
     /* [BS3CG1DST_XMM15_HI] = */    sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
+    /* [BS3CG1DST_XMM0_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
+    /* [BS3CG1DST_XMM1_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
+    /* [BS3CG1DST_XMM2_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
+    /* [BS3CG1DST_XMM3_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
+    /* [BS3CG1DST_XMM4_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
+    /* [BS3CG1DST_XMM5_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
+    /* [BS3CG1DST_XMM6_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
+    /* [BS3CG1DST_XMM7_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
+    /* [BS3CG1DST_XMM8_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
+    /* [BS3CG1DST_XMM9_LO_ZX] = */  sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
+    /* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
+    /* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
+    /* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
+    /* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
+    /* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
+    /* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
     /* [BS3CG1DST_XMM0_DW0] = */    sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
     /* [BS3CG1DST_XMM1_DW0] = */    sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
@@ -723 +755 @@
 #ifdef BS3CG1_DEBUG_CTX_MOD
 /** Destination field names. */
-static const struct { char sz[10]; } g_aszBs3Cg1DstFields[] =
+static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
 {
     { "INVALID" },
@@ -896 +928 @@
     { "XMM14_HI" },
     { "XMM15_HI" },
+    { "XMM0_LO_ZX" },
+    { "XMM1_LO_ZX" },
+    { "XMM2_LO_ZX" },
+    { "XMM3_LO_ZX" },
+    { "XMM4_LO_ZX" },
+    { "XMM5_LO_ZX" },
+    { "XMM6_LO_ZX" },
+    { "XMM7_LO_ZX" },
+    { "XMM8_LO_ZX" },
+    { "XMM9_LO_ZX" },
+    { "XMM10_LO_ZX" },
+    { "XMM11_LO_ZX" },
+    { "XMM12_LO_ZX" },
+    { "XMM13_LO_ZX" },
+    { "XMM14_LO_ZX" },
+    { "XMM15_LO_ZX" },
     { "XMM0_DW0" },
     { "XMM1_DW0" },
@@ -1362 +1410 @@
             break;
 
+        case BS3CG1ENC_MODRM_WqZxReg_Vq:
+            if (iEncoding == 0)
+            {
+                off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
+                pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
+                pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO_ZX;
+                pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
+            }
+            else if (iEncoding == 1)
+            {
+                pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
+                off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
+                off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_RW);
+            }
+            else if (iEncoding == 2)
+            {
+                pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
+                off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
+                off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW);
+            }
+            else
+                break;
+            pThis->cbCurInstr = off;
+            iEncoding++;
+            break;
+
         case BS3CG1ENC_MODRM_Vq_UqHi:
             if (iEncoding == 0)
@@ -1687 +1761 @@
 
         case BS3CG1ENC_MODRM_Wsd_Vsd:
+        case BS3CG1ENC_MODRM_WqZxReg_Vq:
             pThis->iRmOp             = 0;
             pThis->iRegOp            = 1;
@@ -2308 +2383 @@
 
                 case 8:
+                    if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
+                        PtrField.pu64[1] = 0;
                     switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
                     {